arch/m68k/include/asm/fec.h

   1 /*
   2  * fec.h -- Fast Ethernet Controller definitions
   3  *
   4  * Some definitions copied from commproc.h for MPC8xx:
   5  * MPC8xx Communication Processor Module.
   6  * Copyright (c) 1997 Dan Malek (dmalek@jlc.net)
   7  *
   8  * Add FEC Structure and definitions
   9  * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
  10  * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
  11  *
  12  * SPDX-License-Identifier:     GPL-2.0+
  13  */
  14
  15 #ifndef fec_h
  16 #define fec_h
  17
  18 /* Buffer descriptors used FEC.
  19 */
  20 typedef struct cpm_buf_desc {
  21         ushort cbd_sc;          /* Status and Control */
  22         ushort cbd_datlen;      /* Data length in buffer */
  23         uint cbd_bufaddr;       /* Buffer address in host memory */
  24 } cbd_t;
  25
  26 #define BD_SC_EMPTY             ((ushort)0x8000)        /* Receive is empty */
  27 #define BD_SC_READY             ((ushort)0x8000)        /* Transmit is ready */
  28 #define BD_SC_WRAP              ((ushort)0x2000)        /* Last buffer descriptor */
  29 #define BD_SC_INTRPT            ((ushort)0x1000)        /* Interrupt on change */
  30 #define BD_SC_LAST              ((ushort)0x0800)        /* Last buffer in frame */
  31 #define BD_SC_TC                ((ushort)0x0400)        /* Transmit CRC */
  32 #define BD_SC_CM                ((ushort)0x0200)        /* Continous mode */
  33 #define BD_SC_ID                ((ushort)0x0100)        /* Rec'd too many idles */
  34 #define BD_SC_P                 ((ushort)0x0100)        /* xmt preamble */
  35 #define BD_SC_BR                ((ushort)0x0020)        /* Break received */
  36 #define BD_SC_FR                ((ushort)0x0010)        /* Framing error */
  37 #define BD_SC_PR                ((ushort)0x0008)        /* Parity error */
  38 #define BD_SC_OV                ((ushort)0x0002)        /* Overrun */
  39 #define BD_SC_CD                ((ushort)0x0001)        /* Carrier Detect lost */
  40
  41 /* Buffer descriptor control/status used by Ethernet receive.
  42 */
  43 #define BD_ENET_RX_EMPTY        ((ushort)0x8000)
  44 #define BD_ENET_RX_RO1          ((ushort)0x4000)
  45 #define BD_ENET_RX_WRAP         ((ushort)0x2000)
  46 #define BD_ENET_RX_INTR         ((ushort)0x1000)
  47 #define BD_ENET_RX_RO2          BD_ENET_RX_INTR
  48 #define BD_ENET_RX_LAST         ((ushort)0x0800)
  49 #define BD_ENET_RX_FIRST        ((ushort)0x0400)
  50 #define BD_ENET_RX_MISS         ((ushort)0x0100)
  51 #define BD_ENET_RX_BC           ((ushort)0x0080)
  52 #define BD_ENET_RX_MC           ((ushort)0x0040)
  53 #define BD_ENET_RX_LG           ((ushort)0x0020)
  54 #define BD_ENET_RX_NO           ((ushort)0x0010)
  55 #define BD_ENET_RX_SH           ((ushort)0x0008)
  56 #define BD_ENET_RX_CR           ((ushort)0x0004)
  57 #define BD_ENET_RX_OV           ((ushort)0x0002)
  58 #define BD_ENET_RX_CL           ((ushort)0x0001)
  59 #define BD_ENET_RX_TR           BD_ENET_RX_CL
  60 #define BD_ENET_RX_STATS        ((ushort)0x013f)        /* All status bits */
  61
  62 /* Buffer descriptor control/status used by Ethernet transmit.
  63 */
  64 #define BD_ENET_TX_READY        ((ushort)0x8000)
  65 #define BD_ENET_TX_PAD          ((ushort)0x4000)
  66 #define BD_ENET_TX_TO1          BD_ENET_TX_PAD
  67 #define BD_ENET_TX_WRAP         ((ushort)0x2000)
  68 #define BD_ENET_TX_INTR         ((ushort)0x1000)
  69 #define BD_ENET_TX_TO2          BD_ENET_TX_INTR_
  70 #define BD_ENET_TX_LAST         ((ushort)0x0800)
  71 #define BD_ENET_TX_TC           ((ushort)0x0400)
  72 #define BD_ENET_TX_DEF          ((ushort)0x0200)
  73 #define BD_ENET_TX_ABC          BD_ENET_TX_DEF
  74 #define BD_ENET_TX_HB           ((ushort)0x0100)
  75 #define BD_ENET_TX_LC           ((ushort)0x0080)
  76 #define BD_ENET_TX_RL           ((ushort)0x0040)
  77 #define BD_ENET_TX_RCMASK       ((ushort)0x003c)
  78 #define BD_ENET_TX_UN           ((ushort)0x0002)
  79 #define BD_ENET_TX_CSL          ((ushort)0x0001)
  80 #define BD_ENET_TX_STATS        ((ushort)0x03ff)        /* All status bits */
  81
  82 /*********************************************************************
  83 * Fast Ethernet Controller (FEC)
  84 *********************************************************************/
  85 /* FEC private information */
  86 struct fec_info_s {
  87         int index;
  88         u32 iobase;
  89         u32 pinmux;
  90         u32 miibase;
  91         int phy_addr;
  92         int dup_spd;
  93         char *phy_name;
  94         int phyname_init;
  95         cbd_t *rxbd;            /* Rx BD */
  96         cbd_t *txbd;            /* Tx BD */
  97         uint rxIdx;
  98         uint txIdx;
  99         char *txbuf;
 100         int initialized;
 101         struct fec_info_s *next;
 102 };
 103
 104 #ifdef CONFIG_MCFFEC
 105 /* Register read/write struct */
 106 typedef struct fec {
 107 #ifdef CONFIG_M5272
 108         u32 ecr;                /* 0x00 */
 109         u32 eir;                /* 0x04 */
 110         u32 eimr;               /* 0x08 */
 111         u32 ivsr;               /* 0x0C */
 112         u32 rdar;               /* 0x10 */
 113         u32 tdar;               /* 0x14 */
 114         u8 resv1[0x28];         /* 0x18 */
 115         u32 mmfr;               /* 0x40 */
 116         u32 mscr;               /* 0x44 */
 117         u8 resv2[0x44];         /* 0x48 */
 118         u32 frbr;               /* 0x8C */
 119         u32 frsr;               /* 0x90 */
 120         u8 resv3[0x10];         /* 0x94 */
 121         u32 tfwr;               /* 0xA4 */
 122         u32 res4;               /* 0xA8 */
 123         u32 tfsr;               /* 0xAC */
 124         u8 resv4[0x50];         /* 0xB0 */
 125         u32 opd;                /* 0x100 - dummy  */
 126         u32 rcr;                /* 0x104 */
 127         u32 mibc;               /* 0x108 */
 128         u8 resv5[0x38];         /* 0x10C */
 129         u32 tcr;                /* 0x144 */
 130         u8 resv6[0x270];        /* 0x148 */
 131         u32 iaur;               /* 0x3B8 - dummy */
 132         u32 ialr;               /* 0x3BC - dummy  */
 133         u32 palr;               /* 0x3C0 */
 134         u32 paur;               /* 0x3C4 */
 135         u32 gaur;               /* 0x3C8 */
 136         u32 galr;               /* 0x3CC */
 137         u32 erdsr;              /* 0x3D0 */
 138         u32 etdsr;              /* 0x3D4 */
 139         u32 emrbr;              /* 0x3D8 */
 140         u8 resv12[0x74];        /* 0x18C */
 141 #else
 142         u8 resv0[0x4];
 143         u32 eir;
 144         u32 eimr;
 145         u8 resv1[0x4];
 146         u32 rdar;
 147         u32 tdar;
 148         u8 resv2[0xC];
 149         u32 ecr;
 150         u8 resv3[0x18];
 151         u32 mmfr;
 152         u32 mscr;
 153         u8 resv4[0x1C];
 154         u32 mibc;
 155         u8 resv5[0x1C];
 156         u32 rcr;
 157         u8 resv6[0x3C];
 158         u32 tcr;
 159         u8 resv7[0x1C];
 160         u32 palr;
 161         u32 paur;
 162         u32 opd;
 163         u8 resv8[0x28];
 164         u32 iaur;
 165         u32 ialr;
 166         u32 gaur;
 167         u32 galr;
 168         u8 resv9[0x1C];
 169         u32 tfwr;
 170         u8 resv10[0x4];
 171         u32 frbr;
 172         u32 frsr;
 173         u8 resv11[0x2C];
 174         u32 erdsr;
 175         u32 etdsr;
 176         u32 emrbr;
 177         u8 resv12[0x74];
 178 #endif
 179
 180         u32 rmon_t_drop;
 181         u32 rmon_t_packets;
 182         u32 rmon_t_bc_pkt;
 183         u32 rmon_t_mc_pkt;
 184         u32 rmon_t_crc_align;
 185         u32 rmon_t_undersize;
 186         u32 rmon_t_oversize;
 187         u32 rmon_t_frag;
 188         u32 rmon_t_jab;
 189         u32 rmon_t_col;
 190         u32 rmon_t_p64;
 191         u32 rmon_t_p65to127;
 192         u32 rmon_t_p128to255;
 193         u32 rmon_t_p256to511;
 194         u32 rmon_t_p512to1023;
 195         u32 rmon_t_p1024to2047;
 196         u32 rmon_t_p_gte2048;
 197         u32 rmon_t_octets;
 198
 199         u32 ieee_t_drop;
 200         u32 ieee_t_frame_ok;
 201         u32 ieee_t_1col;
 202         u32 ieee_t_mcol;
 203         u32 ieee_t_def;
 204         u32 ieee_t_lcol;
 205         u32 ieee_t_excol;
 206         u32 ieee_t_macerr;
 207         u32 ieee_t_cserr;
 208         u32 ieee_t_sqe;
 209         u32 ieee_t_fdxfc;
 210         u32 ieee_t_octets_ok;
 211         u8 resv13[0x8];
 212
 213         u32 rmon_r_drop;
 214         u32 rmon_r_packets;
 215         u32 rmon_r_bc_pkt;
 216         u32 rmon_r_mc_pkt;
 217         u32 rmon_r_crc_align;
 218         u32 rmon_r_undersize;
 219         u32 rmon_r_oversize;
 220         u32 rmon_r_frag;
 221         u32 rmon_r_jab;
 222         u32 rmon_r_resvd_0;
 223         u32 rmon_r_p64;
 224         u32 rmon_r_p65to127;
 225         u32 rmon_r_p128to255;
 226         u32 rmon_r_p256to511;
 227         u32 rmon_r_p512to1023;
 228         u32 rmon_r_p1024to2047;
 229         u32 rmon_r_p_gte2048;
 230         u32 rmon_r_octets;
 231
 232         u32 ieee_r_drop;
 233         u32 ieee_r_frame_ok;
 234         u32 ieee_r_crc;
 235         u32 ieee_r_align;
 236         u32 ieee_r_macerr;
 237         u32 ieee_r_fdxfc;
 238         u32 ieee_r_octets_ok;
 239 } fec_t;
 240 #endif                          /* CONFIG_MCFFEC */
 241
 242 /*********************************************************************
 243 * Fast Ethernet Controller (FEC)
 244 *********************************************************************/
 245 /* Bit definitions and macros for FEC_EIR */
 246 #define FEC_EIR_CLEAR_ALL               (0xFFF80000)
 247 #define FEC_EIR_HBERR                   (0x80000000)
 248 #define FEC_EIR_BABR                    (0x40000000)
 249 #define FEC_EIR_BABT                    (0x20000000)
 250 #define FEC_EIR_GRA                     (0x10000000)
 251 #define FEC_EIR_TXF                     (0x08000000)
 252 #define FEC_EIR_TXB                     (0x04000000)
 253 #define FEC_EIR_RXF                     (0x02000000)
 254 #define FEC_EIR_RXB                     (0x01000000)
 255 #define FEC_EIR_MII                     (0x00800000)
 256 #define FEC_EIR_EBERR                   (0x00400000)
 257 #define FEC_EIR_LC                      (0x00200000)
 258 #define FEC_EIR_RL                      (0x00100000)
 259 #define FEC_EIR_UN                      (0x00080000)
 260
 261 /* Bit definitions and macros for FEC_RDAR */
 262 #define FEC_RDAR_R_DES_ACTIVE           (0x01000000)
 263
 264 /* Bit definitions and macros for FEC_TDAR */
 265 #define FEC_TDAR_X_DES_ACTIVE           (0x01000000)
 266
 267 /* Bit definitions and macros for FEC_ECR */
 268 #define FEC_ECR_ETHER_EN                (0x00000002)
 269 #define FEC_ECR_RESET                   (0x00000001)
 270
 271 /* Bit definitions and macros for FEC_MMFR */
 272 #define FEC_MMFR_DATA(x)                (((x)&0xFFFF))
 273 #define FEC_MMFR_ST(x)                  (((x)&0x03)<<30)
 274 #define FEC_MMFR_ST_01                  (0x40000000)
 275 #define FEC_MMFR_OP_RD                  (0x20000000)
 276 #define FEC_MMFR_OP_WR                  (0x10000000)
 277 #define FEC_MMFR_PA(x)                  (((x)&0x1F)<<23)
 278 #define FEC_MMFR_RA(x)                  (((x)&0x1F)<<18)
 279 #define FEC_MMFR_TA(x)                  (((x)&0x03)<<16)
 280 #define FEC_MMFR_TA_10                  (0x00020000)
 281
 282 /* Bit definitions and macros for FEC_MSCR */
 283 #define FEC_MSCR_DIS_PREAMBLE           (0x00000080)
 284 #define FEC_MSCR_MII_SPEED(x)           (((x)&0x3F)<<1)
 285
 286 /* Bit definitions and macros for FEC_MIBC */
 287 #define FEC_MIBC_MIB_DISABLE            (0x80000000)
 288 #define FEC_MIBC_MIB_IDLE               (0x40000000)
 289
 290 /* Bit definitions and macros for FEC_RCR */
 291 #define FEC_RCR_MAX_FL(x)               (((x)&0x7FF)<<16)
 292 #define FEC_RCR_FCE                     (0x00000020)
 293 #define FEC_RCR_BC_REJ                  (0x00000010)
 294 #define FEC_RCR_PROM                    (0x00000008)
 295 #define FEC_RCR_MII_MODE                (0x00000004)
 296 #define FEC_RCR_DRT                     (0x00000002)
 297 #define FEC_RCR_LOOP                    (0x00000001)
 298
 299 /* Bit definitions and macros for FEC_TCR */
 300 #define FEC_TCR_RFC_PAUSE               (0x00000010)
 301 #define FEC_TCR_TFC_PAUSE               (0x00000008)
 302 #define FEC_TCR_FDEN                    (0x00000004)
 303 #define FEC_TCR_HBC                     (0x00000002)
 304 #define FEC_TCR_GTS                     (0x00000001)
 305
 306 /* Bit definitions and macros for FEC_PAUR */
 307 #define FEC_PAUR_PADDR2(x)              (((x)&0xFFFF)<<16)
 308 #define FEC_PAUR_TYPE(x)                ((x)&0xFFFF)
 309
 310 /* Bit definitions and macros for FEC_OPD */
 311 #define FEC_OPD_PAUSE_DUR(x)            (((x)&0x0000FFFF)<<0)
 312 #define FEC_OPD_OPCODE(x)               (((x)&0x0000FFFF)<<16)
 313
 314 /* Bit definitions and macros for FEC_TFWR */
 315 #define FEC_TFWR_X_WMRK(x)              ((x)&0x03)
 316 #define FEC_TFWR_X_WMRK_64              (0x01)
 317 #define FEC_TFWR_X_WMRK_128             (0x02)
 318 #define FEC_TFWR_X_WMRK_192             (0x03)
 319
 320 /* Bit definitions and macros for FEC_FRBR */
 321 #define FEC_FRBR_R_BOUND(x)             (((x)&0xFF)<<2)
 322
 323 /* Bit definitions and macros for FEC_FRSR */
 324 #define FEC_FRSR_R_FSTART(x)            (((x)&0xFF)<<2)
 325
 326 /* Bit definitions and macros for FEC_ERDSR */
 327 #define FEC_ERDSR_R_DES_START(x)        (((x)&0x3FFFFFFF)<<2)
 328
 329 /* Bit definitions and macros for FEC_ETDSR */
 330 #define FEC_ETDSR_X_DES_START(x)        (((x)&0x3FFFFFFF)<<2)
 331
 332 /* Bit definitions and macros for FEC_EMRBR */
 333 #define FEC_EMRBR_R_BUF_SIZE(x)         (((x)&0x7F)<<4)
 334
 335 #define FEC_RESET_DELAY                 100
 336 #define FEC_RX_TOUT                     100
 337
 338 int fecpin_setclear(struct eth_device *dev, int setclear);
 339
 340 #ifdef CONFIG_SYS_DISCOVER_PHY
 341 void __mii_init(void);
 342 uint mii_send(uint mii_cmd);
 343 int mii_discover_phy(struct eth_device *dev);
 344 int mcffec_miiphy_read(const char *devname, unsigned char addr,
 345                        unsigned char reg, unsigned short *value);
 346 int mcffec_miiphy_write(const char *devname, unsigned char addr,
 347                         unsigned char reg, unsigned short value);
 348 #endif
 349
 350 #endif                          /* fec_h */