arch/m68k/include/asm/immap_5275.h

   1 /*
   2  * MCF5274/5 Internal Memory Map
   3  *
   4  * Copyright (c) 2005 Arthur Shipkowski <art@videon-central.com>
   5  * Based on work Copyright (c) 2003 Josef Baumgartner
   6  *                                  <josef.baumgartner@telex.de>
   7  *
   8  * SPDX-License-Identifier:     GPL-2.0+
   9  */
  10
  11 #ifndef __IMMAP_5275__
  12 #define __IMMAP_5275__
  13
  14 #define MMAP_SCM        (CONFIG_SYS_MBAR + 0x00000000)
  15 #define MMAP_SDRAM      (CONFIG_SYS_MBAR + 0x00000040)
  16 #define MMAP_FBCS       (CONFIG_SYS_MBAR + 0x00000080)
  17 #define MMAP_DMA0       (CONFIG_SYS_MBAR + 0x00000100)
  18 #define MMAP_DMA1       (CONFIG_SYS_MBAR + 0x00000110)
  19 #define MMAP_DMA2       (CONFIG_SYS_MBAR + 0x00000120)
  20 #define MMAP_DMA3       (CONFIG_SYS_MBAR + 0x00000130)
  21 #define MMAP_UART0      (CONFIG_SYS_MBAR + 0x00000200)
  22 #define MMAP_UART1      (CONFIG_SYS_MBAR + 0x00000240)
  23 #define MMAP_UART2      (CONFIG_SYS_MBAR + 0x00000280)
  24 #define MMAP_I2C        (CONFIG_SYS_MBAR + 0x00000300)
  25 #define MMAP_QSPI       (CONFIG_SYS_MBAR + 0x00000340)
  26 #define MMAP_DTMR0      (CONFIG_SYS_MBAR + 0x00000400)
  27 #define MMAP_DTMR1      (CONFIG_SYS_MBAR + 0x00000440)
  28 #define MMAP_DTMR2      (CONFIG_SYS_MBAR + 0x00000480)
  29 #define MMAP_DTMR3      (CONFIG_SYS_MBAR + 0x000004C0)
  30 #define MMAP_INTC0      (CONFIG_SYS_MBAR + 0x00000C00)
  31 #define MMAP_INTC1      (CONFIG_SYS_MBAR + 0x00000D00)
  32 #define MMAP_INTCACK    (CONFIG_SYS_MBAR + 0x00000F00)
  33 #define MMAP_FEC0       (CONFIG_SYS_MBAR + 0x00001000)
  34 #define MMAP_FEC0FIFO   (CONFIG_SYS_MBAR + 0x00001400)
  35 #define MMAP_FEC1       (CONFIG_SYS_MBAR + 0x00001800)
  36 #define MMAP_FEC1FIFO   (CONFIG_SYS_MBAR + 0x00001C00)
  37 #define MMAP_GPIO       (CONFIG_SYS_MBAR + 0x00100000)
  38 #define MMAP_RCM        (CONFIG_SYS_MBAR + 0x00110000)
  39 #define MMAP_CCM        (CONFIG_SYS_MBAR + 0x00110004)
  40 #define MMAP_PLL        (CONFIG_SYS_MBAR + 0x00120000)
  41 #define MMAP_EPORT      (CONFIG_SYS_MBAR + 0x00130000)
  42 #define MMAP_WDOG       (CONFIG_SYS_MBAR + 0x00140000)
  43 #define MMAP_PIT0       (CONFIG_SYS_MBAR + 0x00150000)
  44 #define MMAP_PIT1       (CONFIG_SYS_MBAR + 0x00160000)
  45 #define MMAP_PIT2       (CONFIG_SYS_MBAR + 0x00170000)
  46 #define MMAP_PIT3       (CONFIG_SYS_MBAR + 0x00180000)
  47 #define MMAP_MDHA       (CONFIG_SYS_MBAR + 0x00190000)
  48 #define MMAP_RNG        (CONFIG_SYS_MBAR + 0x001A0000)
  49 #define MMAP_SKHA       (CONFIG_SYS_MBAR + 0x001B0000)
  50 #define MMAP_USB        (CONFIG_SYS_MBAR + 0x001C0000)
  51 #define MMAP_PWM0       (CONFIG_SYS_MBAR + 0x001D0000)
  52
  53 #include <asm/coldfire/eport.h>
  54 #include <asm/coldfire/flexbus.h>
  55 #include <asm/coldfire/intctrl.h>
  56 #include <asm/coldfire/mdha.h>
  57 #include <asm/coldfire/pwm.h>
  58 #include <asm/coldfire/qspi.h>
  59 #include <asm/coldfire/rng.h>
  60 #include <asm/coldfire/skha.h>
  61
  62 /* System configuration registers
  63 */
  64 typedef struct sys_ctrl {
  65         u32 ipsbar;
  66         u32 res1;
  67         u32 rambar;
  68         u32 res2;
  69         u8 crsr;
  70         u8 cwcr;
  71         u8 lpicr;
  72         u8 cwsr;
  73         u8 res3[8];
  74         u32 mpark;
  75         u8 mpr;
  76         u8 res4[3];
  77         u8 pacr0;
  78         u8 pacr1;
  79         u8 pacr2;
  80         u8 pacr3;
  81         u8 pacr4;
  82         u8 res5;
  83         u8 pacr5;
  84         u8 pacr6;
  85         u8 pacr7;
  86         u8 res6;
  87         u8 pacr8;
  88         u8 res7;
  89         u8 gpacr;
  90         u8 res8[3];
  91 } sysctrl_t;
  92 /* SDRAM controller registers, offset: 0x040
  93  */
  94 typedef struct sdram_ctrl {
  95         u32 sdmr;
  96         u32 sdcr;
  97         u32 sdcfg1;
  98         u32 sdcfg2;
  99         u32 sdbar0;
 100         u32 sdbmr0;
 101         u32 sdbar1;
 102         u32 sdbmr1;
 103 } sdramctrl_t;
 104
 105 /* DMA module registers, offset 0x100
 106  */
 107 typedef struct  dma_ctrl {
 108         u32 sar;
 109         u32 dar;
 110         u32 dsrbcr;
 111         u32 dcr;
 112 } dma_t;
 113
 114 /* GPIO port registers
 115 */
 116 typedef struct  gpio_ctrl {
 117         /* Port Output Data Registers */
 118         u8 podr_res1[4];
 119         u8 podr_busctl;
 120         u8 podr_addr;
 121         u8 podr_res2[2];
 122         u8 podr_cs;
 123         u8 podr_res3;
 124         u8 podr_fec0h;
 125         u8 podr_fec0l;
 126         u8 podr_feci2c;
 127         u8 podr_qspi;
 128         u8 podr_sdram;
 129         u8 podr_timerh;
 130         u8 podr_timerl;
 131         u8 podr_uartl;
 132         u8 podr_fec1h;
 133         u8 podr_fec1l;
 134         u8 podr_bs;
 135         u8 podr_res4;
 136         u8 podr_usbh;
 137         u8 podr_usbl;
 138         u8 podr_uarth;
 139         u8 podr_res5[3];
 140         /* Port Data Direction Registers */
 141         u8 pddr_res1[4];
 142         u8 pddr_busctl;
 143         u8 pddr_addr;
 144         u8 pddr_res2[2];
 145         u8 pddr_cs;
 146         u8 pddr_res3;
 147         u8 pddr_fec0h;
 148         u8 pddr_fec0l;
 149         u8 pddr_feci2c;
 150         u8 pddr_qspi;
 151         u8 pddr_sdram;
 152         u8 pddr_timerh;
 153         u8 pddr_timerl;
 154         u8 pddr_uartl;
 155         u8 pddr_fec1h;
 156         u8 pddr_fec1l;
 157         u8 pddr_bs;
 158         u8 pddr_res4;
 159         u8 pddr_usbh;
 160         u8 pddr_usbl;
 161         u8 pddr_uarth;
 162         u8 pddr_res5[3];
 163         /* Port Pin Data/Set Registers */
 164         u8 ppdsdr_res1[4];
 165         u8 ppdsdr_busctl;
 166         u8 ppdsdr_addr;
 167         u8 ppdsdr_res2[2];
 168         u8 ppdsdr_cs;
 169         u8 ppdsdr_res3;
 170         u8 ppdsdr_fec0h;
 171         u8 ppdsdr_fec0l;
 172         u8 ppdsdr_feci2c;
 173         u8 ppdsdr_qspi;
 174         u8 ppdsdr_sdram;
 175         u8 ppdsdr_timerh;
 176         u8 ppdsdr_timerl;
 177         u8 ppdsdr_uartl;
 178         u8 ppdsdr_fec1h;
 179         u8 ppdsdr_fec1l;
 180         u8 ppdsdr_bs;
 181         u8 ppdsdr_res4;
 182         u8 ppdsdr_usbh;
 183         u8 ppdsdr_usbl;
 184         u8 ppdsdr_uarth;
 185         u8 ppdsdr_res5[3];
 186         /* Port Clear Output Data Registers */
 187         u8 pclrr_res1[4];
 188         u8 pclrr_busctl;
 189         u8 pclrr_addr;
 190         u8 pclrr_res2[2];
 191         u8 pclrr_cs;
 192         u8 pclrr_res3;
 193         u8 pclrr_fec0h;
 194         u8 pclrr_fec0l;
 195         u8 pclrr_feci2c;
 196         u8 pclrr_qspi;
 197         u8 pclrr_sdram;
 198         u8 pclrr_timerh;
 199         u8 pclrr_timerl;
 200         u8 pclrr_uartl;
 201         u8 pclrr_fec1h;
 202         u8 pclrr_fec1l;
 203         u8 pclrr_bs;
 204         u8 pclrr_res4;
 205         u8 pclrr_usbh;
 206         u8 pclrr_usbl;
 207         u8 pclrr_uarth;
 208         u8 pclrr_res5[3];
 209         /* Pin Assignment Registers */
 210         u8 par_addr;
 211         u8 par_cs;
 212         u16 par_busctl;
 213         u8 par_res1[2];
 214         u16 par_usb;
 215         u8 par_fec0hl;
 216         u8 par_fec1hl;
 217         u16 par_timer;
 218         u16 par_uart;
 219         u16 par_qspi;
 220         u16 par_sdram;
 221         u16 par_feci2c;
 222         u8 par_bs;
 223         u8 par_res2[3];
 224 } gpio_t;
 225
 226
 227 /* Watchdog registers
 228  */
 229 typedef struct wdog_ctrl {
 230         u16 wcr;
 231         u16 wmr;
 232         u16 wcntr;
 233         u16 wsr;
 234         u8 res4[114];
 235 } wdog_t;
 236
 237 /* USB module registers
 238 */
 239 typedef struct usb {
 240         u16 res1;
 241         u16 fnr;
 242         u16 res2;
 243         u16 fnmr;
 244         u16 res3;
 245         u16 rfmr;
 246         u16 res4;
 247         u16 rfmmr;
 248         u8 res5[3];
 249         u8 far;
 250         u32 asr;
 251         u32 drr1;
 252         u32 drr2;
 253         u16 res6;
 254         u16 specr;
 255         u16 res7;
 256         u16 ep0sr;
 257         u32 iep0cfg;
 258         u32 oep0cfg;
 259         u32 ep1cfg;
 260         u32 ep2cfg;
 261         u32 ep3cfg;
 262         u32 ep4cfg;
 263         u32 ep5cfg;
 264         u32 ep6cfg;
 265         u32 ep7cfg;
 266         u32 ep0ctl;
 267         u16 res8;
 268         u16 ep1ctl;
 269         u16 res9;
 270         u16 ep2ctl;
 271         u16 res10;
 272         u16 ep3ctl;
 273         u16 res11;
 274         u16 ep4ctl;
 275         u16 res12;
 276         u16 ep5ctl;
 277         u16 res13;
 278         u16 ep6ctl;
 279         u16 res14;
 280         u16 ep7ctl;
 281         u32 ep0isr;
 282         u16 res15;
 283         u16 ep1isr;
 284         u16 res16;
 285         u16 ep2isr;
 286         u16 res17;
 287         u16 ep3isr;
 288         u16 res18;
 289         u16 ep4isr;
 290         u16 res19;
 291         u16 ep5isr;
 292         u16 res20;
 293         u16 ep6isr;
 294         u16 res21;
 295         u16 ep7isr;
 296         u32 ep0imr;
 297         u16 res22;
 298         u16 ep1imr;
 299         u16 res23;
 300         u16 ep2imr;
 301         u16 res24;
 302         u16 ep3imr;
 303         u16 res25;
 304         u16 ep4imr;
 305         u16 res26;
 306         u16 ep5imr;
 307         u16 res27;
 308         u16 ep6imr;
 309         u16 res28;
 310         u16 ep7imr;
 311         u32 ep0dr;
 312         u32 ep1dr;
 313         u32 ep2dr;
 314         u32 ep3dr;
 315         u32 ep4dr;
 316         u32 ep5dr;
 317         u32 ep6dr;
 318         u32 ep7dr;
 319         u16 res29;
 320         u16 ep0dpr;
 321         u16 res30;
 322         u16 ep1dpr;
 323         u16 res31;
 324         u16 ep2dpr;
 325         u16 res32;
 326         u16 ep3dpr;
 327         u16 res33;
 328         u16 ep4dpr;
 329         u16 res34;
 330         u16 ep5dpr;
 331         u16 res35;
 332         u16 ep6dpr;
 333         u16 res36;
 334         u16 ep7dpr;
 335         u8 res37[788];
 336         u8 cfgram[1024];
 337 } usb_t;
 338
 339 /* PLL module registers
 340  */
 341 typedef struct pll_ctrl {
 342         u32 syncr;
 343         u32 synsr;
 344 } pll_t;
 345
 346 typedef struct rcm {
 347         u8 rcr;
 348         u8 rsr;
 349 } rcm_t;
 350
 351 #endif /* __IMMAP_5275__ */