arch/m68k/include/asm/m5253.h

   1 /*
   2  * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
   3  * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  */
  23
  24 #ifndef m5253_h
  25 #define m5253_h
  26 /****************************************************************************/
  27
  28 /*
  29 * PLL Module (PLL)
  30 */
  31
  32 /* Register read/write macros */
  33 #define PLL_PLLCR               (0x000180)
  34
  35 #define SIM_RSR                 (0x000000)
  36 #define SIM_SYPCR               (0x000001)
  37 #define SIM_SWIVR               (0x000002)
  38 #define SIM_SWSR                (0x000003)
  39 #define SIM_MPARK               (0x00000C)
  40
  41 /* Bit definitions and macros for RSR */
  42 #define SIM_RSR_SWTR            (0x20)
  43 #define SIM_RSR_HRST            (0x80)
  44
  45 /* Register read/write macros */
  46 #define CIM_MISCCR              (0x000500)
  47 #define CIM_ATA_DADDR           (0x000504)
  48 #define CIM_ATA_DCOUNT          (0x000508)
  49 #define CIM_RTC_TIME            (0x00050C)
  50 #define CIM_USB_CANCLK          (0x000510)
  51
  52 /* Bit definitions and macros for MISCCR */
  53 #define CIM_MISCCR_ADTA         (0x00000001)
  54 #define CIM_MISCCR_ADTD         (0x00000002)
  55 #define CIM_MISCCR_ADIE         (0x00000004)
  56 #define CIM_MISCCR_ADIC         (0x00000008)
  57 #define CIM_MISCCR_ADIP         (0x00000010)
  58 #define CIM_MISCCR_CPUEND       (0x00000020)
  59 #define CIM_MISCCR_DMAEND       (0x00000040)
  60 #define CIM_MISCCR_RTCCLR       (0x00000080)
  61 #define CIM_MISCCR_RTCPL        (0x00000100)
  62 #define CIM_MISCCR_URIE         (0x00000800)
  63 #define CIM_MISCCR_URIC         (0x00001000)
  64 #define CIM_MISCCR_URIP         (0x00002000)
  65
  66 /* Bit definitions and macros for ATA_DADDR */
  67 #define CIM_ATA_DADDR_ATAADDR(x)        (((x)&0x00003FFF)<<2)
  68 #define CIM_ATA_DADDR_RAMADDR(x)        (((x)&0x00003FFF)<<18)
  69
  70 /* Bit definitions and macros for ATA_DCOUNT */
  71 #define CIM_ATA_DCOUNT_COUNT(x)         (((x)&0x0000FFFF))
  72
  73 #endif                          /* m5253_h */