arch/m68k/include/asm/m5282.h

   1 /*
   2  * mcf5282.h -- Definitions for Motorola Coldfire 5282
   3  *
   4  * See file CREDITS for list of people who contributed to this
   5  * project.
   6  *
   7  * This program is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU General Public License as
   9  * published by the Free Software Foundation; either version 2 of
  10  * the License, or (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  20  * MA 02111-1307 USA
  21  */
  22
  23 /****************************************************************************/
  24 #ifndef m5282_h
  25 #define m5282_h
  26
  27 /*********************************************************************
  28 * PLL Clock Module
  29 *********************************************************************/
  30 /* Bit definitions and macros for PLL_SYNCR */
  31 #define PLL_SYNCR_LOLRE                 (0x8000)
  32 #define PLL_SYNCR_MFD2                  (0x4000)
  33 #define PLL_SYNCR_MFD1                  (0x2000)
  34 #define PLL_SYNCR_MFD0                  (0x1000)
  35 #define PLL_SYNCR_LOCRE                 (0x0800)
  36 #define PLL_SYNCR_RFC2                  (0x0400)
  37 #define PLL_SYNCR_RFC1                  (0x0200)
  38 #define PLL_SYNCR_RFC0                  (0x0100)
  39 #define PLL_SYNCR_LOCEN                 (0x0080)
  40 #define PLL_SYNCR_DISCLK                (0x0040)
  41 #define PLL_SYNCR_FWKUP                 (0x0020)
  42 #define PLL_SYNCR_STPMD1                (0x0008)
  43 #define PLL_SYNCR_STPMD0                (0x0004)
  44
  45 /* Bit definitions and macros for PLL_SYNSR */
  46 #define PLL_SYNSR_MODE                  (0x0080)
  47 #define PLL_SYNSR_PLLSEL                (0x0040)
  48 #define PLL_SYNSR_PLLREF                (0x0020)
  49 #define PLL_SYNSR_LOCKS                 (0x0010)
  50 #define PLL_SYNSR_LOCK                  (0x0008)
  51 #define PLL_SYNSR_LOCS                  (0x0004)
  52
  53 /*********************************************************************
  54 * Interrupt Controller (INTC)
  55 *********************************************************************/
  56 #define INT0_LO_RSVD0                   (0)
  57 #define INT0_LO_EPORT1                  (1)
  58 #define INT0_LO_EPORT2                  (2)
  59 #define INT0_LO_EPORT3                  (3)
  60 #define INT0_LO_EPORT4                  (4)
  61 #define INT0_LO_EPORT5                  (5)
  62 #define INT0_LO_EPORT6                  (6)
  63 #define INT0_LO_EPORT7                  (7)
  64 #define INT0_LO_SCM_SWT1                (8)
  65 #define INT0_LO_DMA_00                  (9)
  66 #define INT0_LO_DMA_01                  (10)
  67 #define INT0_LO_DMA_02                  (11)
  68 #define INT0_LO_DMA_03                  (12)
  69 #define INT0_LO_UART0                   (13)
  70 #define INT0_LO_UART1                   (14)
  71 #define INT0_LO_UART2                   (15)
  72 #define INT0_LO_RSVD1                   (16)
  73 #define INT0_LO_I2C                     (17)
  74 #define INT0_LO_QSPI                    (18)
  75 #define INT0_LO_DTMR0                   (19)
  76 #define INT0_LO_DTMR1                   (20)
  77 #define INT0_LO_DTMR2                   (21)
  78 #define INT0_LO_DTMR3                   (22)
  79 #define INT0_LO_FEC_TXF                 (23)
  80 #define INT0_LO_FEC_TXB                 (24)
  81 #define INT0_LO_FEC_UN                  (25)
  82 #define INT0_LO_FEC_RL                  (26)
  83 #define INT0_LO_FEC_RXF                 (27)
  84 #define INT0_LO_FEC_RXB                 (28)
  85 #define INT0_LO_FEC_MII                 (29)
  86 #define INT0_LO_FEC_LC                  (30)
  87 #define INT0_LO_FEC_HBERR               (31)
  88 #define INT0_HI_FEC_GRA                 (32)
  89 #define INT0_HI_FEC_EBERR               (33)
  90 #define INT0_HI_FEC_BABT                (34)
  91 #define INT0_HI_FEC_BABR                (35)
  92 #define INT0_HI_PMM_LVDF                (36)
  93 #define INT0_HI_QADC_CF1                (37)
  94 #define INT0_HI_QADC_CF2                (38)
  95 #define INT0_HI_QADC_PF1                (39)
  96 #define INT0_HI_QADC_PF2                (40)
  97 #define INT0_HI_GPTA_TOF                (41)
  98 #define INT0_HI_GPTA_PAIF               (42)
  99 #define INT0_HI_GPTA_PAOVF              (43)
 100 #define INT0_HI_GPTA_C0F                (44)
 101 #define INT0_HI_GPTA_C1F                (45)
 102 #define INT0_HI_GPTA_C2F                (46)
 103 #define INT0_HI_GPTA_C3F                (47)
 104 #define INT0_HI_GPTB_TOF                (48)
 105 #define INT0_HI_GPTB_PAIF               (49)
 106 #define INT0_HI_GPTB_PAOVF              (50)
 107 #define INT0_HI_GPTB_C0F                (51)
 108 #define INT0_HI_GPTB_C1F                (52)
 109 #define INT0_HI_GPTB_C2F                (53)
 110 #define INT0_HI_GPTB_C3F                (54)
 111 #define INT0_HI_PIT0                    (55)
 112 #define INT0_HI_PIT1                    (56)
 113 #define INT0_HI_PIT2                    (57)
 114 #define INT0_HI_PIT3                    (58)
 115 #define INT0_HI_CFM_CBEIF               (59)
 116 #define INT0_HI_CFM_CCIF                (60)
 117 #define INT0_HI_CFM_PVIF                (61)
 118 #define INT0_HI_CFM_AEIF                (62)
 119
 120 /*
 121  * Size of internal RAM
 122  */
 123
 124 #define INT_RAM_SIZE    65536
 125
 126 /* General Purpose I/O Module GPIO */
 127
 128 #define MCFGPIO_PORTA           (*(vu_char *) (CONFIG_SYS_MBAR+0x100000))
 129 #define MCFGPIO_PORTB           (*(vu_char *) (CONFIG_SYS_MBAR+0x100001))
 130 #define MCFGPIO_PORTC           (*(vu_char *) (CONFIG_SYS_MBAR+0x100002))
 131 #define MCFGPIO_PORTD           (*(vu_char *) (CONFIG_SYS_MBAR+0x100003))
 132 #define MCFGPIO_PORTE           (*(vu_char *) (CONFIG_SYS_MBAR+0x100004))
 133 #define MCFGPIO_PORTF           (*(vu_char *) (CONFIG_SYS_MBAR+0x100005))
 134 #define MCFGPIO_PORTG           (*(vu_char *) (CONFIG_SYS_MBAR+0x100006))
 135 #define MCFGPIO_PORTH           (*(vu_char *) (CONFIG_SYS_MBAR+0x100007))
 136 #define MCFGPIO_PORTJ           (*(vu_char *) (CONFIG_SYS_MBAR+0x100008))
 137 #define MCFGPIO_PORTDD          (*(vu_char *) (CONFIG_SYS_MBAR+0x100009))
 138 #define MCFGPIO_PORTEH          (*(vu_char *) (CONFIG_SYS_MBAR+0x10000A))
 139 #define MCFGPIO_PORTEL          (*(vu_char *) (CONFIG_SYS_MBAR+0x10000B))
 140 #define MCFGPIO_PORTAS          (*(vu_char *) (CONFIG_SYS_MBAR+0x10000C))
 141 #define MCFGPIO_PORTQS          (*(vu_char *) (CONFIG_SYS_MBAR+0x10000D))
 142 #define MCFGPIO_PORTSD          (*(vu_char *) (CONFIG_SYS_MBAR+0x10000E))
 143 #define MCFGPIO_PORTTC          (*(vu_char *) (CONFIG_SYS_MBAR+0x10000F))
 144 #define MCFGPIO_PORTTD          (*(vu_char *) (CONFIG_SYS_MBAR+0x100010))
 145 #define MCFGPIO_PORTUA          (*(vu_char *) (CONFIG_SYS_MBAR+0x100011))
 146
 147 #define MCFGPIO_DDRA            (*(vu_char *) (CONFIG_SYS_MBAR+0x100014))
 148 #define MCFGPIO_DDRB            (*(vu_char *) (CONFIG_SYS_MBAR+0x100015))
 149 #define MCFGPIO_DDRC            (*(vu_char *) (CONFIG_SYS_MBAR+0x100016))
 150 #define MCFGPIO_DDRD            (*(vu_char *) (CONFIG_SYS_MBAR+0x100017))
 151 #define MCFGPIO_DDRE            (*(vu_char *) (CONFIG_SYS_MBAR+0x100018))
 152 #define MCFGPIO_DDRF            (*(vu_char *) (CONFIG_SYS_MBAR+0x100019))
 153 #define MCFGPIO_DDRG            (*(vu_char *) (CONFIG_SYS_MBAR+0x10001A))
 154 #define MCFGPIO_DDRH            (*(vu_char *) (CONFIG_SYS_MBAR+0x10001B))
 155 #define MCFGPIO_DDRJ            (*(vu_char *) (CONFIG_SYS_MBAR+0x10001C))
 156 #define MCFGPIO_DDRDD           (*(vu_char *) (CONFIG_SYS_MBAR+0x10001D))
 157 #define MCFGPIO_DDREH           (*(vu_char *) (CONFIG_SYS_MBAR+0x10001E))
 158 #define MCFGPIO_DDREL           (*(vu_char *) (CONFIG_SYS_MBAR+0x10001F))
 159 #define MCFGPIO_DDRAS           (*(vu_char *) (CONFIG_SYS_MBAR+0x100020))
 160 #define MCFGPIO_DDRQS           (*(vu_char *) (CONFIG_SYS_MBAR+0x100021))
 161 #define MCFGPIO_DDRSD           (*(vu_char *) (CONFIG_SYS_MBAR+0x100022))
 162 #define MCFGPIO_DDRTC           (*(vu_char *) (CONFIG_SYS_MBAR+0x100023))
 163 #define MCFGPIO_DDRTD           (*(vu_char *) (CONFIG_SYS_MBAR+0x100024))
 164 #define MCFGPIO_DDRUA           (*(vu_char *) (CONFIG_SYS_MBAR+0x100025))
 165
 166 #define MCFGPIO_PORTAP          (*(vu_char *) (CONFIG_SYS_MBAR+0x100028))
 167 #define MCFGPIO_PORTBP          (*(vu_char *) (CONFIG_SYS_MBAR+0x100029))
 168 #define MCFGPIO_PORTCP          (*(vu_char *) (CONFIG_SYS_MBAR+0x10002A))
 169 #define MCFGPIO_PORTDP          (*(vu_char *) (CONFIG_SYS_MBAR+0x10002B))
 170 #define MCFGPIO_PORTEP          (*(vu_char *) (CONFIG_SYS_MBAR+0x10002C))
 171 #define MCFGPIO_PORTFP          (*(vu_char *) (CONFIG_SYS_MBAR+0x10002D))
 172 #define MCFGPIO_PORTGP          (*(vu_char *) (CONFIG_SYS_MBAR+0x10002E))
 173 #define MCFGPIO_PORTHP          (*(vu_char *) (CONFIG_SYS_MBAR+0x10002F))
 174 #define MCFGPIO_PORTJP          (*(vu_char *) (CONFIG_SYS_MBAR+0x100030))
 175 #define MCFGPIO_PORTDDP         (*(vu_char *) (CONFIG_SYS_MBAR+0x100031))
 176 #define MCFGPIO_PORTEHP         (*(vu_char *) (CONFIG_SYS_MBAR+0x100032))
 177 #define MCFGPIO_PORTELP         (*(vu_char *) (CONFIG_SYS_MBAR+0x100033))
 178 #define MCFGPIO_PORTASP         (*(vu_char *) (CONFIG_SYS_MBAR+0x100034))
 179 #define MCFGPIO_PORTQSP         (*(vu_char *) (CONFIG_SYS_MBAR+0x100035))
 180 #define MCFGPIO_PORTSDP         (*(vu_char *) (CONFIG_SYS_MBAR+0x100036))
 181 #define MCFGPIO_PORTTCP         (*(vu_char *) (CONFIG_SYS_MBAR+0x100037))
 182 #define MCFGPIO_PORTTDP         (*(vu_char *) (CONFIG_SYS_MBAR+0x100038))
 183 #define MCFGPIO_PORTUAP         (*(vu_char *) (CONFIG_SYS_MBAR+0x100039))
 184
 185 #define MCFGPIO_SETA            (*(vu_char *) (CONFIG_SYS_MBAR+0x100028))
 186 #define MCFGPIO_SETB            (*(vu_char *) (CONFIG_SYS_MBAR+0x100029))
 187 #define MCFGPIO_SETC            (*(vu_char *) (CONFIG_SYS_MBAR+0x10002A))
 188 #define MCFGPIO_SETD            (*(vu_char *) (CONFIG_SYS_MBAR+0x10002B))
 189 #define MCFGPIO_SETE            (*(vu_char *) (CONFIG_SYS_MBAR+0x10002C))
 190 #define MCFGPIO_SETF            (*(vu_char *) (CONFIG_SYS_MBAR+0x10002D))
 191 #define MCFGPIO_SETG            (*(vu_char *) (CONFIG_SYS_MBAR+0x10002E))
 192 #define MCFGPIO_SETH            (*(vu_char *) (CONFIG_SYS_MBAR+0x10002F))
 193 #define MCFGPIO_SETJ            (*(vu_char *) (CONFIG_SYS_MBAR+0x100030))
 194 #define MCFGPIO_SETDD           (*(vu_char *) (CONFIG_SYS_MBAR+0x100031))
 195 #define MCFGPIO_SETEH           (*(vu_char *) (CONFIG_SYS_MBAR+0x100032))
 196 #define MCFGPIO_SETEL           (*(vu_char *) (CONFIG_SYS_MBAR+0x100033))
 197 #define MCFGPIO_SETAS           (*(vu_char *) (CONFIG_SYS_MBAR+0x100034))
 198 #define MCFGPIO_SETQS           (*(vu_char *) (CONFIG_SYS_MBAR+0x100035))
 199 #define MCFGPIO_SETSD           (*(vu_char *) (CONFIG_SYS_MBAR+0x100036))
 200 #define MCFGPIO_SETTC           (*(vu_char *) (CONFIG_SYS_MBAR+0x100037))
 201 #define MCFGPIO_SETTD           (*(vu_char *) (CONFIG_SYS_MBAR+0x100038))
 202 #define MCFGPIO_SETUA           (*(vu_char *) (CONFIG_SYS_MBAR+0x100039))
 203
 204 #define MCFGPIO_CLRA            (*(vu_char *) (CONFIG_SYS_MBAR+0x10003C))
 205 #define MCFGPIO_CLRB            (*(vu_char *) (CONFIG_SYS_MBAR+0x10003D))
 206 #define MCFGPIO_CLRC            (*(vu_char *) (CONFIG_SYS_MBAR+0x10003E))
 207 #define MCFGPIO_CLRD            (*(vu_char *) (CONFIG_SYS_MBAR+0x10003F))
 208 #define MCFGPIO_CLRE            (*(vu_char *) (CONFIG_SYS_MBAR+0x100040))
 209 #define MCFGPIO_CLRF            (*(vu_char *) (CONFIG_SYS_MBAR+0x100041))
 210 #define MCFGPIO_CLRG            (*(vu_char *) (CONFIG_SYS_MBAR+0x100042))
 211 #define MCFGPIO_CLRH            (*(vu_char *) (CONFIG_SYS_MBAR+0x100043))
 212 #define MCFGPIO_CLRJ            (*(vu_char *) (CONFIG_SYS_MBAR+0x100044))
 213 #define MCFGPIO_CLRDD           (*(vu_char *) (CONFIG_SYS_MBAR+0x100045))
 214 #define MCFGPIO_CLREH           (*(vu_char *) (CONFIG_SYS_MBAR+0x100046))
 215 #define MCFGPIO_CLREL           (*(vu_char *) (CONFIG_SYS_MBAR+0x100047))
 216 #define MCFGPIO_CLRAS           (*(vu_char *) (CONFIG_SYS_MBAR+0x100048))
 217 #define MCFGPIO_CLRQS           (*(vu_char *) (CONFIG_SYS_MBAR+0x100049))
 218 #define MCFGPIO_CLRSD           (*(vu_char *) (CONFIG_SYS_MBAR+0x10004A))
 219 #define MCFGPIO_CLRTC           (*(vu_char *) (CONFIG_SYS_MBAR+0x10004B))
 220 #define MCFGPIO_CLRTD           (*(vu_char *) (CONFIG_SYS_MBAR+0x10004C))
 221 #define MCFGPIO_CLRUA           (*(vu_char *) (CONFIG_SYS_MBAR+0x10004D))
 222
 223 #define MCFGPIO_PBCDPAR (*(vu_char *) (CONFIG_SYS_MBAR+0x100050))
 224 #define MCFGPIO_PFPAR           (*(vu_char *) (CONFIG_SYS_MBAR+0x100051))
 225 #define MCFGPIO_PEPAR           (*(vu_short *)(CONFIG_SYS_MBAR+0x100052))
 226 #define MCFGPIO_PJPAR           (*(vu_char *) (CONFIG_SYS_MBAR+0x100054))
 227 #define MCFGPIO_PSDPAR          (*(vu_char *) (CONFIG_SYS_MBAR+0x100055))
 228 #define MCFGPIO_PASPAR          (*(vu_short *)(CONFIG_SYS_MBAR+0x100056))
 229 #define MCFGPIO_PEHLPAR         (*(vu_char *) (CONFIG_SYS_MBAR+0x100058))
 230 #define MCFGPIO_PQSPAR          (*(vu_char *) (CONFIG_SYS_MBAR+0x100059))
 231 #define MCFGPIO_PTCPAR          (*(vu_char *) (CONFIG_SYS_MBAR+0x10005A))
 232 #define MCFGPIO_PTDPAR          (*(vu_char *) (CONFIG_SYS_MBAR+0x10005B))
 233 #define MCFGPIO_PUAPAR          (*(vu_char *) (CONFIG_SYS_MBAR+0x10005C))
 234
 235 /* Bit level definitions and macros */
 236 #define MCFGPIO_PORT7                   (0x80)
 237 #define MCFGPIO_PORT6                   (0x40)
 238 #define MCFGPIO_PORT5                   (0x20)
 239 #define MCFGPIO_PORT4                   (0x10)
 240 #define MCFGPIO_PORT3                   (0x08)
 241 #define MCFGPIO_PORT2                   (0x04)
 242 #define MCFGPIO_PORT1                   (0x02)
 243 #define MCFGPIO_PORT0                   (0x01)
 244 #define MCFGPIO_PORT(x)                 (0x01<<x)
 245
 246 #define MCFGPIO_DDR7                    (0x80)
 247 #define MCFGPIO_DDR6                    (0x40)
 248 #define MCFGPIO_DDR5                    (0x20)
 249 #define MCFGPIO_DDR4                    (0x10)
 250 #define MCFGPIO_DDR3                    (0x08)
 251 #define MCFGPIO_DDR2                    (0x04)
 252 #define MCFGPIO_DDR1                    (0x02)
 253 #define MCFGPIO_DDR0                    (0x01)
 254 #define MCFGPIO_DDR(x)                  (0x01<<x)
 255
 256 #define MCFGPIO_Px7                     (0x80)
 257 #define MCFGPIO_Px6                     (0x40)
 258 #define MCFGPIO_Px5                     (0x20)
 259 #define MCFGPIO_Px4                     (0x10)
 260 #define MCFGPIO_Px3                     (0x08)
 261 #define MCFGPIO_Px2                     (0x04)
 262 #define MCFGPIO_Px1                     (0x02)
 263 #define MCFGPIO_Px0                     (0x01)
 264 #define MCFGPIO_Px(x)                   (0x01<<x)
 265
 266 #define MCFGPIO_PBCDPAR_PBPA            (0x80)
 267 #define MCFGPIO_PBCDPAR_PCDPA           (0x40)
 268
 269 #define MCFGPIO_PEPAR_PEPA7             (0x4000)
 270 #define MCFGPIO_PEPAR_PEPA6             (0x1000)
 271 #define MCFGPIO_PEPAR_PEPA5             (0x0400)
 272 #define MCFGPIO_PEPAR_PEPA4             (0x0100)
 273 #define MCFGPIO_PEPAR_PEPA3             (0x0040)
 274 #define MCFGPIO_PEPAR_PEPA2             (0x0010)
 275 #define MCFGPIO_PEPAR_PEPA1(x)          (((x)&0x3)<<2)
 276 #define MCFGPIO_PEPAR_PEPA0(x)          (((x)&0x3))
 277
 278 #define MCFGPIO_PFPAR_PFPA7             (0x80)
 279 #define MCFGPIO_PFPAR_PFPA6             (0x40)
 280 #define MCFGPIO_PFPAR_PFPA5             (0x20)
 281
 282 #define MCFGPIO_PJPAR_PJPA7             (0x80)
 283 #define MCFGPIO_PJPAR_PJPA6             (0x40)
 284 #define MCFGPIO_PJPAR_PJPA5             (0x20)
 285 #define MCFGPIO_PJPAR_PJPA4             (0x10)
 286 #define MCFGPIO_PJPAR_PJPA3             (0x08)
 287 #define MCFGPIO_PJPAR_PJPA2             (0x04)
 288 #define MCFGPIO_PJPAR_PJPA1             (0x02)
 289 #define MCFGPIO_PJPAR_PJPA0             (0x01)
 290 #define MCFGPIO_PJPAR_PJPA(x)           (0x01<<x)
 291
 292 #define MCFGPIO_PSDPAR_PSDPA            (0x80)
 293
 294 #define MCFGPIO_PASPAR_PASPA5(x)        (((x)&0x3)<<10)
 295 #define MCFGPIO_PASPAR_PASPA4(x)        (((x)&0x3)<<8)
 296 #define MCFGPIO_PASPAR_PASPA3(x)        (((x)&0x3)<<6)
 297 #define MCFGPIO_PASPAR_PASPA2(x)        (((x)&0x3)<<4)
 298 #define MCFGPIO_PASPAR_PASPA1(x)        (((x)&0x3)<<2)
 299 #define MCFGPIO_PASPAR_PASPA0(x)        (((x)&0x3))
 300
 301 #define MCFGPIO_PEHLPAR_PEHPA           (0x80)
 302 #define MCFGPIO_PEHLPAR_PELPA           (0x40)
 303
 304 #define MCFGPIO_PQSPAR_PQSPA6           (0x40)
 305 #define MCFGPIO_PQSPAR_PQSPA5           (0x20)
 306 #define MCFGPIO_PQSPAR_PQSPA4           (0x10)
 307 #define MCFGPIO_PQSPAR_PQSPA3           (0x08)
 308 #define MCFGPIO_PQSPAR_PQSPA2           (0x04)
 309 #define MCFGPIO_PQSPAR_PQSPA1           (0x02)
 310 #define MCFGPIO_PQSPAR_PQSPA0           (0x01)
 311 #define MCFGPIO_PQSPAR_PQSPA(x)         (0x01<<x)
 312
 313 #define MCFGPIO_PTCPAR_PTCPA3(x)        (((x)&0x3)<<6)
 314 #define MCFGPIO_PTCPAR_PTCPA2(x)        (((x)&0x3)<<4)
 315 #define MCFGPIO_PTCPAR_PTCPA1(x)        (((x)&0x3)<<2)
 316 #define MCFGPIO_PTCPAR_PTCPA0(x)        (((x)&0x3))
 317
 318 #define MCFGPIO_PTDPAR_PTDPA3(x)        (((x)&0x3)<<6)
 319 #define MCFGPIO_PTDPAR_PTDPA2(x)        (((x)&0x3)<<4)
 320 #define MCFGPIO_PTDPAR_PTDPA1(x)        (((x)&0x3)<<2)
 321 #define MCFGPIO_PTDPAR_PTDPA0(x)        (((x)&0x3))
 322
 323 #define MCFGPIO_PUAPAR_PUAPA3           (0x08)
 324 #define MCFGPIO_PUAPAR_PUAPA2           (0x04)
 325 #define MCFGPIO_PUAPAR_PUAPA1           (0x02)
 326 #define MCFGPIO_PUAPAR_PUAPA0           (0x01)
 327
 328 /* System Conrol Module SCM */
 329
 330 #define MCFSCM_RAMBAR           (*(vu_long *) (CONFIG_SYS_MBAR+0x00000008))
 331 #define MCFSCM_CRSR             (*(vu_char *) (CONFIG_SYS_MBAR+0x00000010))
 332 #define MCFSCM_CWCR             (*(vu_char *) (CONFIG_SYS_MBAR+0x00000011))
 333 #define MCFSCM_LPICR            (*(vu_char *) (CONFIG_SYS_MBAR+0x00000012))
 334 #define MCFSCM_CWSR             (*(vu_char *) (CONFIG_SYS_MBAR+0x00000013))
 335
 336 #define MCFSCM_MPARK            (*(vu_long *) (CONFIG_SYS_MBAR+0x0000001C))
 337 #define MCFSCM_MPR              (*(vu_char *) (CONFIG_SYS_MBAR+0x00000020))
 338 #define MCFSCM_PACR0            (*(vu_char *) (CONFIG_SYS_MBAR+0x00000024))
 339 #define MCFSCM_PACR1            (*(vu_char *) (CONFIG_SYS_MBAR+0x00000025))
 340 #define MCFSCM_PACR2            (*(vu_char *) (CONFIG_SYS_MBAR+0x00000026))
 341 #define MCFSCM_PACR3            (*(vu_char *) (CONFIG_SYS_MBAR+0x00000027))
 342 #define MCFSCM_PACR4            (*(vu_char *) (CONFIG_SYS_MBAR+0x00000028))
 343 #define MCFSCM_PACR5            (*(vu_char *) (CONFIG_SYS_MBAR+0x0000002A))
 344 #define MCFSCM_PACR6            (*(vu_char *) (CONFIG_SYS_MBAR+0x0000002B))
 345 #define MCFSCM_PACR7            (*(vu_char *) (CONFIG_SYS_MBAR+0x0000002C))
 346 #define MCFSCM_PACR8            (*(vu_char *) (CONFIG_SYS_MBAR+0x0000002E))
 347 #define MCFSCM_GPACR0           (*(vu_char *) (CONFIG_SYS_MBAR+0x00000030))
 348 #define MCFSCM_GPACR1           (*(vu_char *) (CONFIG_SYS_MBAR+0x00000031))
 349
 350 #define MCFSCM_CRSR_EXT         (0x80)
 351 #define MCFSCM_CRSR_CWDR        (0x20)
 352 #define MCFSCM_RAMBAR_BA(x)     ((x)&0xFFFF0000)
 353 #define MCFSCM_RAMBAR_BDE       (0x00000200)
 354
 355 /* Reset Controller Module RCM */
 356
 357 #define MCFRESET_RCR            (*(vu_char *) (CONFIG_SYS_MBAR+0x00110000))
 358 #define MCFRESET_RSR            (*(vu_char *) (CONFIG_SYS_MBAR+0x00110001))
 359
 360 #define MCFRESET_RCR_SOFTRST    (0x80)
 361 #define MCFRESET_RCR_FRCRSTOUT  (0x40)
 362 #define MCFRESET_RCR_LVDF       (0x10)
 363 #define MCFRESET_RCR_LVDIE      (0x08)
 364 #define MCFRESET_RCR_LVDRE      (0x04)
 365 #define MCFRESET_RCR_LVDE       (0x01)
 366
 367 #define MCFRESET_RSR_LVD        (0x40)
 368 #define MCFRESET_RSR_SOFT       (0x20)
 369 #define MCFRESET_RSR_WDR        (0x10)
 370 #define MCFRESET_RSR_POR        (0x08)
 371 #define MCFRESET_RSR_EXT        (0x04)
 372 #define MCFRESET_RSR_LOC        (0x02)
 373 #define MCFRESET_RSR_LOL        (0x01)
 374 #define MCFRESET_RSR_ALL        (0x7F)
 375 #define MCFRESET_RCR_SOFTRST    (0x80)
 376 #define MCFRESET_RCR_FRCRSTOUT  (0x40)
 377
 378 /* Chip Configuration Module CCM */
 379
 380 #define MCFCCM_CCR              (*(vu_short *)(CONFIG_SYS_MBAR+0x00110004))
 381 #define MCFCCM_RCON             (*(vu_short *)(CONFIG_SYS_MBAR+0x00110008))
 382 #define MCFCCM_CIR              (*(vu_short *)(CONFIG_SYS_MBAR+0x0011000A))
 383
 384 /* Bit level definitions and macros */
 385 #define MCFCCM_CCR_LOAD         (0x8000)
 386 #define MCFCCM_CCR_MODE(x)      (((x)&0x0007)<<8)
 387 #define MCFCCM_CCR_SZEN         (0x0040)
 388 #define MCFCCM_CCR_PSTEN        (0x0020)
 389 #define MCFCCM_CCR_BME          (0x0008)
 390 #define MCFCCM_CCR_BMT(x)       (((x)&0x0007))
 391
 392 #define MCFCCM_CIR_PIN_MASK     (0xFF00)
 393 #define MCFCCM_CIR_PRN_MASK     (0x00FF)
 394
 395 /* Clock Module */
 396
 397 #define MCFCLOCK_SYNCR          (*(vu_short *)(CONFIG_SYS_MBAR+0x120000))
 398 #define MCFCLOCK_SYNSR          (*(vu_char *) (CONFIG_SYS_MBAR+0x120002))
 399
 400 #define MCFCLOCK_SYNCR_MFD(x)   (((x)&0x0007)<<12)
 401 #define MCFCLOCK_SYNCR_RFD(x)   (((x)&0x0007)<<8)
 402 #define MCFCLOCK_SYNSR_LOCK     0x08
 403
 404 #define MCFSDRAMC_DCR           (*(vu_short *)(CONFIG_SYS_MBAR+0x00000040))
 405 #define MCFSDRAMC_DACR0         (*(vu_long *) (CONFIG_SYS_MBAR+0x00000048))
 406 #define MCFSDRAMC_DMR0          (*(vu_long *) (CONFIG_SYS_MBAR+0x0000004c))
 407 #define MCFSDRAMC_DACR1         (*(vu_long *) (CONFIG_SYS_MBAR+0x00000050))
 408 #define MCFSDRAMC_DMR1          (*(vu_long *) (CONFIG_SYS_MBAR+0x00000054))
 409
 410 #define MCFSDRAMC_DCR_NAM       (0x2000)
 411 #define MCFSDRAMC_DCR_COC       (0x1000)
 412 #define MCFSDRAMC_DCR_IS        (0x0800)
 413 #define MCFSDRAMC_DCR_RTIM_3    (0x0000)
 414 #define MCFSDRAMC_DCR_RTIM_6    (0x0200)
 415 #define MCFSDRAMC_DCR_RTIM_9    (0x0400)
 416 #define MCFSDRAMC_DCR_RC(x)     ((x)&0x01FF)
 417
 418 #define MCFSDRAMC_DACR_BASE(x)  ((x)&0xFFFC0000)
 419 #define MCFSDRAMC_DACR_RE       (0x00008000)
 420 #define MCFSDRAMC_DACR_CASL(x)  (((x)&0x03)<<12)
 421 #define MCFSDRAMC_DACR_CBM(x)   (((x)&0x07)<<8)
 422 #define MCFSDRAMC_DACR_PS_32    (0x00000000)
 423 #define MCFSDRAMC_DACR_PS_16    (0x00000020)
 424 #define MCFSDRAMC_DACR_PS_8     (0x00000010)
 425 #define MCFSDRAMC_DACR_IP       (0x00000008)
 426 #define MCFSDRAMC_DACR_IMRS     (0x00000040)
 427
 428 #define MCFSDRAMC_DMR_BAM_16M   (0x00FC0000)
 429 #define MCFSDRAMC_DMR_WP        (0x00000100)
 430 #define MCFSDRAMC_DMR_CI        (0x00000040)
 431 #define MCFSDRAMC_DMR_AM        (0x00000020)
 432 #define MCFSDRAMC_DMR_SC        (0x00000010)
 433 #define MCFSDRAMC_DMR_SD        (0x00000008)
 434 #define MCFSDRAMC_DMR_UC        (0x00000004)
 435 #define MCFSDRAMC_DMR_UD        (0x00000002)
 436 #define MCFSDRAMC_DMR_V         (0x00000001)
 437
 438 #define MCFWTM_WCR              (*(vu_short *)(CONFIG_SYS_MBAR+0x00140000))
 439 #define MCFWTM_WMR              (*(vu_short *)(CONFIG_SYS_MBAR+0x00140002))
 440 #define MCFWTM_WCNTR            (*(vu_short *)(CONFIG_SYS_MBAR+0x00140004))
 441 #define MCFWTM_WSR              (*(vu_short *)(CONFIG_SYS_MBAR+0x00140006))
 442
 443 /*********************************************************************
 444 * General Purpose Timer (GPT) Module
 445 *********************************************************************/
 446
 447 #define MCFGPTA_GPTIOS          (*(vu_char *)(CONFIG_SYS_MBAR+0x1A0000))
 448 #define MCFGPTA_GPTCFORC        (*(vu_char *)(CONFIG_SYS_MBAR+0x1A0001))
 449 #define MCFGPTA_GPTOC3M         (*(vu_char *)(CONFIG_SYS_MBAR+0x1A0002))
 450 #define MCFGPTA_GPTOC3D         (*(vu_char *)(CONFIG_SYS_MBAR+0x1A0003))
 451 #define MCFGPTA_GPTCNT          (*(vu_short *)(CONFIG_SYS_MBAR+0x1A0004))
 452 #define MCFGPTA_GPTSCR1         (*(vu_char *)(CONFIG_SYS_MBAR+0x1A0006))
 453 #define MCFGPTA_GPTTOV          (*(vu_char *)(CONFIG_SYS_MBAR+0x1A0008))
 454 #define MCFGPTA_GPTCTL1         (*(vu_char *)(CONFIG_SYS_MBAR+0x1A0009))
 455 #define MCFGPTA_GPTCTL2         (*(vu_char *)(CONFIG_SYS_MBAR+0x1A000B))
 456 #define MCFGPTA_GPTIE           (*(vu_char *)(CONFIG_SYS_MBAR+0x1A000C))
 457 #define MCFGPTA_GPTSCR2         (*(vu_char *)(CONFIG_SYS_MBAR+0x1A000D))
 458 #define MCFGPTA_GPTFLG1         (*(vu_char *)(CONFIG_SYS_MBAR+0x1A000E))
 459 #define MCFGPTA_GPTFLG2         (*(vu_char *)(CONFIG_SYS_MBAR+0x1A000F))
 460 #define MCFGPTA_GPTC0           (*(vu_short *)(CONFIG_SYS_MBAR+0x1A0010))
 461 #define MCFGPTA_GPTC1           (*(vu_short *)(CONFIG_SYS_MBAR+0x1A0012))
 462 #define MCFGPTA_GPTC2           (*(vu_short *)(CONFIG_SYS_MBAR+0x1A0014))
 463 #define MCFGPTA_GPTC3           (*(vu_short *)(CONFIG_SYS_MBAR+0x1A0016))
 464 #define MCFGPTA_GPTPACTL        (*(vu_char *)(CONFIG_SYS_MBAR+0x1A0018))
 465 #define MCFGPTA_GPTPAFLG        (*(vu_char *)(CONFIG_SYS_MBAR+0x1A0019))
 466 #define MCFGPTA_GPTPACNT        (*(vu_short *)(CONFIG_SYS_MBAR+0x1A001A))
 467 #define MCFGPTA_GPTPORT         (*(vu_char *)(CONFIG_SYS_MBAR+0x1A001D))
 468 #define MCFGPTA_GPTDDR          (*(vu_char *)(CONFIG_SYS_MBAR+0x1A001E))
 469
 470 #define MCFGPTB_GPTIOS          (*(vu_char *)(CONFIG_SYS_MBAR+0x1B0000))
 471 #define MCFGPTB_GPTCFORC        (*(vu_char *)(CONFIG_SYS_MBAR+0x1B0001))
 472 #define MCFGPTB_GPTOC3M         (*(vu_char *)(CONFIG_SYS_MBAR+0x1B0002))
 473 #define MCFGPTB_GPTOC3D         (*(vu_char *)(CONFIG_SYS_MBAR+0x1B0003))
 474 #define MCFGPTB_GPTCNT          (*(vu_short *)(CONFIG_SYS_MBAR+0x1B0004))
 475 #define MCFGPTB_GPTSCR1         (*(vu_char *)(CONFIG_SYS_MBAR+0x1B0006))
 476 #define MCFGPTB_GPTTOV          (*(vu_char *)(CONFIG_SYS_MBAR+0x1B0008))
 477 #define MCFGPTB_GPTCTL1         (*(vu_char *)(CONFIG_SYS_MBAR+0x1B0009))
 478 #define MCFGPTB_GPTCTL2         (*(vu_char *)(CONFIG_SYS_MBAR+0x1B000B))
 479 #define MCFGPTB_GPTIE           (*(vu_char *)(CONFIG_SYS_MBAR+0x1B000C))
 480 #define MCFGPTB_GPTSCR2         (*(vu_char *)(CONFIG_SYS_MBAR+0x1B000D))
 481 #define MCFGPTB_GPTFLG1         (*(vu_char *)(CONFIG_SYS_MBAR+0x1B000E))
 482 #define MCFGPTB_GPTFLG2         (*(vu_char *)(CONFIG_SYS_MBAR+0x1B000F))
 483 #define MCFGPTB_GPTC0           (*(vu_short *)(CONFIG_SYS_MBAR+0x1B0010))
 484 #define MCFGPTB_GPTC1           (*(vu_short *)(CONFIG_SYS_MBAR+0x1B0012))
 485 #define MCFGPTB_GPTC2           (*(vu_short *)(CONFIG_SYS_MBAR+0x1B0014))
 486 #define MCFGPTB_GPTC3           (*(vu_short *)(CONFIG_SYS_MBAR+0x1B0016))
 487 #define MCFGPTB_GPTPACTL        (*(vu_char *)(CONFIG_SYS_MBAR+0x1B0018))
 488 #define MCFGPTB_GPTPAFLG        (*(vu_char *)(CONFIG_SYS_MBAR+0x1B0019))
 489 #define MCFGPTB_GPTPACNT        (*(vu_short *)(CONFIG_SYS_MBAR+0x1B001A))
 490 #define MCFGPTB_GPTPORT         (*(vu_char *)(CONFIG_SYS_MBAR+0x1B001D))
 491 #define MCFGPTB_GPTDDR          (*(vu_char *)(CONFIG_SYS_MBAR+0x1B001E))
 492
 493 /* Bit level definitions and macros */
 494 #define MCFGPT_GPTIOS_IOS3              (0x08)
 495 #define MCFGPT_GPTIOS_IOS2              (0x04)
 496 #define MCFGPT_GPTIOS_IOS1              (0x02)
 497 #define MCFGPT_GPTIOS_IOS0              (0x01)
 498
 499 #define MCFGPT_GPTCFORC_FOC3            (0x08)
 500 #define MCFGPT_GPTCFORC_FOC2            (0x04)
 501 #define MCFGPT_GPTCFORC_FOC1            (0x02)
 502 #define MCFGPT_GPTCFORC_FOC0            (0x01)
 503
 504 #define MCFGPT_GPTOC3M_OC3M3            (0x08)
 505 #define MCFGPT_GPTOC3M_OC3M2            (0x04)
 506 #define MCFGPT_GPTOC3M_OC3M1            (0x02)
 507 #define MCFGPT_GPTOC3M_OC3M0            (0x01)
 508
 509 #define MCFGPT_GPTOC3M_OC3D(x)          (((x)&0x04))
 510
 511 #define MCFGPT_GPTSCR1_GPTEN            (0x80)
 512 #define MCFGPT_GPTSCR1_TFFCA            (0x10)
 513
 514 #define MCFGPT_GPTTOV3                  (0x08)
 515 #define MCFGPT_GPTTOV2                  (0x04)
 516 #define MCFGPT_GPTTOV1                  (0x02)
 517 #define MCFGPT_GPTTOV0                  (0x01)
 518
 519 #define MCFGPT_GPTCTL_OMOL3(x)          (((x)&0x03)<<6)
 520 #define MCFGPT_GPTCTL_OMOL2(x)          (((x)&0x03)<<4)
 521 #define MCFGPT_GPTCTL_OMOL1(x)          (((x)&0x03)<<2)
 522 #define MCFGPT_GPTCTL_OMOL0(x)          (((x)&0x03))
 523
 524 #define MCFGPT_GPTCTL2_EDG3(x)          (((x)&0x03)<<6)
 525 #define MCFGPT_GPTCTL2_EDG2(x)          (((x)&0x03)<<4)
 526 #define MCFGPT_GPTCTL2_EDG1(x)          (((x)&0x03)<<2)
 527 #define MCFGPT_GPTCTL2_EDG0(x)          (((x)&0x03))
 528
 529 #define MCFGPT_GPTIE_C3I                (0x08)
 530 #define MCFGPT_GPTIE_C2I                (0x04)
 531 #define MCFGPT_GPTIE_C1I                (0x02)
 532 #define MCFGPT_GPTIE_C0I                (0x01)
 533
 534 #define MCFGPT_GPTSCR2_TOI              (0x80)
 535 #define MCFGPT_GPTSCR2_PUPT             (0x20)
 536 #define MCFGPT_GPTSCR2_RDPT             (0x10)
 537 #define MCFGPT_GPTSCR2_TCRE             (0x08)
 538 #define MCFGPT_GPTSCR2_PR(x)            (((x)&0x07))
 539
 540 #define MCFGPT_GPTFLG1_C3F              (0x08)
 541 #define MCFGPT_GPTFLG1_C2F              (0x04)
 542 #define MCFGPT_GPTFLG1_C1F              (0x02)
 543 #define MCFGPT_GPTFLG1_C0F              (0x01)
 544
 545 #define MCFGPT_GPTFLG2_TOF              (0x80)
 546 #define MCFGPT_GPTFLG2_C3F              (0x08)
 547 #define MCFGPT_GPTFLG2_C2F              (0x04)
 548 #define MCFGPT_GPTFLG2_C1F              (0x02)
 549 #define MCFGPT_GPTFLG2_C0F              (0x01)
 550
 551 #define MCFGPT_GPTPACTL_PAE             (0x40)
 552 #define MCFGPT_GPTPACTL_PAMOD           (0x20)
 553 #define MCFGPT_GPTPACTL_PEDGE           (0x10)
 554 #define MCFGPT_GPTPACTL_CLK_PACLK       (0x04)
 555 #define MCFGPT_GPTPACTL_CLK_PACLK256    (0x08)
 556 #define MCFGPT_GPTPACTL_CLK_PACLK65536  (0x0C)
 557 #define MCFGPT_GPTPACTL_CLK(x)          (((x)&0x03)<<2)
 558 #define MCFGPT_GPTPACTL_PAOVI           (0x02)
 559 #define MCFGPT_GPTPACTL_PAI             (0x01)
 560
 561 #define MCFGPT_GPTPAFLG_PAOVF           (0x02)
 562 #define MCFGPT_GPTPAFLG_PAIF            (0x01)
 563
 564 #define MCFGPT_GPTPORT_PORTT3           (0x08)
 565 #define MCFGPT_GPTPORT_PORTT2           (0x04)
 566 #define MCFGPT_GPTPORT_PORTT1           (0x02)
 567 #define MCFGPT_GPTPORT_PORTT0           (0x01)
 568
 569 #define MCFGPT_GPTDDR_DDRT3             (0x08)
 570 #define MCFGPT_GPTDDR_DDRT2             (0x04)
 571 #define MCFGPT_GPTDDR_DDRT1             (0x02)
 572 #define MCFGPT_GPTDDR_DDRT0             (0x01)
 573
 574 /* Coldfire Flash Module CFM */
 575
 576 #define MCFCFM_MCR                      (*(vu_short *)(CONFIG_SYS_MBAR+0x1D0000))
 577 #define MCFCFM_MCR_LOCK                 (0x0400)
 578 #define MCFCFM_MCR_PVIE                 (0x0200)
 579 #define MCFCFM_MCR_AEIE                 (0x0100)
 580 #define MCFCFM_MCR_CBEIE                (0x0080)
 581 #define MCFCFM_MCR_CCIE                 (0x0040)
 582 #define MCFCFM_MCR_KEYACC               (0x0020)
 583
 584 #define MCFCFM_CLKD                     (*(vu_char *)(CONFIG_SYS_MBAR+0x1D0002))
 585
 586 #define MCFCFM_SEC                      (*(vu_long*) (CONFIG_SYS_MBAR+0x1D0008))
 587 #define MCFCFM_SEC_KEYEN                (0x80000000)
 588 #define MCFCFM_SEC_SECSTAT              (0x40000000)
 589
 590 #define MCFCFM_PROT                     (*(vu_long*) (CONFIG_SYS_MBAR+0x1D0010))
 591 #define MCFCFM_SACC                     (*(vu_long*) (CONFIG_SYS_MBAR+0x1D0014))
 592 #define MCFCFM_DACC                     (*(vu_long*) (CONFIG_SYS_MBAR+0x1D0018))
 593 #define MCFCFM_USTAT                    (*(vu_char*) (CONFIG_SYS_MBAR+0x1D0020))
 594 #define MCFCFM_USTAT_CBEIF              0x80
 595 #define MCFCFM_USTAT_CCIF               0x40
 596 #define MCFCFM_USTAT_PVIOL              0x20
 597 #define MCFCFM_USTAT_ACCERR             0x10
 598 #define MCFCFM_USTAT_BLANK              0x04
 599
 600 #define MCFCFM_CMD                      (*(vu_char*) (CONFIG_SYS_MBAR+0x1D0024))
 601 #define MCFCFM_CMD_ERSVER               0x05
 602 #define MCFCFM_CMD_PGERSVER             0x06
 603 #define MCFCFM_CMD_PGM                  0x20
 604 #define MCFCFM_CMD_PGERS                0x40
 605 #define MCFCFM_CMD_MASERS               0x41
 606
 607 /****************************************************************************/
 608 #endif                          /* m5282_h */