]>
git.ipfire.org Git - people/ms/u-boot.git/blob - arch/m68k/include/asm/m547x_8x.h
2 * mcf547x_8x.h -- Definitions for Freescale Coldfire 547x_8x
4 * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
5 * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
7 * See file CREDITS for list of people who contributed to this
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
29 /*********************************************************************
31 *********************************************************************/
32 /* Bit definitions and macros for XARB_CFG */
33 #define XARB_CFG_AT (0x00000002)
34 #define XARB_CFG_DT (0x00000004)
35 #define XARB_CFG_BA (0x00000008)
36 #define XARB_CFG_PM(x) (((x)&0x00000003)<<5)
37 #define XARB_CFG_SP(x) (((x)&0x00000007)<<8)
38 #define XARB_CFG_PLDIS (0x80000000)
40 /* Bit definitions and macros for XARB_SR */
41 #define XARB_SR_AT (0x00000001)
42 #define XARB_SR_DT (0x00000002)
43 #define XARB_SR_BA (0x00000004)
44 #define XARB_SR_TTM (0x00000008)
45 #define XARB_SR_ECW (0x00000010)
46 #define XARB_SR_TTR (0x00000020)
47 #define XARB_SR_TTA (0x00000040)
48 #define XARB_SR_MM (0x00000080)
49 #define XARB_SR_SEA (0x00000100)
51 /* Bit definitions and macros for XARB_IMR */
52 #define XARB_IMR_ATE (0x00000001)
53 #define XARB_IMR_DTE (0x00000002)
54 #define XARB_IMR_BAE (0x00000004)
55 #define XARB_IMR_TTME (0x00000008)
56 #define XARB_IMR_ECWE (0x00000010)
57 #define XARB_IMR_TTRE (0x00000020)
58 #define XARB_IMR_TTAE (0x00000040)
59 #define XARB_IMR_MME (0x00000080)
60 #define XARB_IMR_SEAE (0x00000100)
62 /* Bit definitions and macros for XARB_SIGCAP */
63 #define XARB_SIGCAP_TT(x) ((x)&0x0000001F)
64 #define XARB_SIGCAP_TBST (0x00000020)
65 #define XARB_SIGCAP_TSIZ(x) (((x)&0x00000007)<<7)
67 /* Bit definitions and macros for XARB_PRIEN */
68 #define XARB_PRIEN_M0 (0x00000001)
69 #define XARB_PRIEN_M2 (0x00000004)
70 #define XARB_PRIEN_M3 (0x00000008)
72 /* Bit definitions and macros for XARB_PRI */
73 #define XARB_PRI_M0P(x) (((x)&0x00000007)<<0)
74 #define XARB_PRI_M2P(x) (((x)&0x00000007)<<8)
75 #define XARB_PRI_M3P(x) (((x)&0x00000007)<<12)
77 /*********************************************************************
78 * General Purpose I/O (GPIO)
79 *********************************************************************/
80 /* Bit definitions and macros for GPIO_PAR_FBCTL */
81 #define GPIO_PAR_FBCTL_TS(x) (((x)&0x0003)<<0)
82 #define GPIO_PAR_FBCTL_TA (0x0004)
83 #define GPIO_PAR_FBCTL_RWB(x) (((x)&0x0003)<<4)
84 #define GPIO_PAR_FBCTL_OE (0x0040)
85 #define GPIO_PAR_FBCTL_BWE0 (0x0100)
86 #define GPIO_PAR_FBCTL_BWE1 (0x0400)
87 #define GPIO_PAR_FBCTL_BWE2 (0x1000)
88 #define GPIO_PAR_FBCTL_BWE3 (0x4000)
89 #define GPIO_PAR_FBCTL_TS_GPIO (0)
90 #define GPIO_PAR_FBCTL_TS_TBST (2)
91 #define GPIO_PAR_FBCTL_TS_TS (3)
92 #define GPIO_PAR_FBCTL_RWB_GPIO (0x0000)
93 #define GPIO_PAR_FBCTL_RWB_TBST (0x0020)
94 #define GPIO_PAR_FBCTL_RWB_RWB (0x0030)
96 /* Bit definitions and macros for GPIO_PAR_FBCS */
97 #define GPIO_PAR_FBCS_CS1 (0x02)
98 #define GPIO_PAR_FBCS_CS2 (0x04)
99 #define GPIO_PAR_FBCS_CS3 (0x08)
100 #define GPIO_PAR_FBCS_CS4 (0x10)
101 #define GPIO_PAR_FBCS_CS5 (0x20)
103 /* Bit definitions and macros for GPIO_PAR_DMA */
104 #define GPIO_PAR_DMA_DREQ0(x) (((x)&0x03)<<0)
105 #define GPIO_PAR_DMA_DREQ1(x) (((x)&0x03)<<2)
106 #define GPIO_PAR_DMA_DACK0(x) (((x)&0x03)<<4)
107 #define GPIO_PAR_DMA_DACK1(x) (((x)&0x03)<<6)
108 #define GPIO_PAR_DMA_DACKx_GPIO (0)
109 #define GPIO_PAR_DMA_DACKx_TOUT (2)
110 #define GPIO_PAR_DMA_DACKx_DACK (3)
111 #define GPIO_PAR_DMA_DREQx_GPIO (0)
112 #define GPIO_PAR_DMA_DREQx_TIN (2)
113 #define GPIO_PAR_DMA_DREQx_DREQ (3)
115 /* Bit definitions and macros for GPIO_PAR_FECI2CIRQ */
116 #define GPIO_PAR_FECI2CIRQ_IRQ5 (0x0001)
117 #define GPIO_PAR_FECI2CIRQ_IRQ6 (0x0002)
118 #define GPIO_PAR_FECI2CIRQ_SCL (0x0004)
119 #define GPIO_PAR_FECI2CIRQ_SDA (0x0008)
120 #define GPIO_PAR_FECI2CIRQ_E1MDC(x) (((x)&0x0003)<<6)
121 #define GPIO_PAR_FECI2CIRQ_E1MDIO(x) (((x)&0x0003)<<8)
122 #define GPIO_PAR_FECI2CIRQ_E1MII (0x0400)
123 #define GPIO_PAR_FECI2CIRQ_E17 (0x0800)
124 #define GPIO_PAR_FECI2CIRQ_E0MDC (0x1000)
125 #define GPIO_PAR_FECI2CIRQ_E0MDIO (0x2000)
126 #define GPIO_PAR_FECI2CIRQ_E0MII (0x4000)
127 #define GPIO_PAR_FECI2CIRQ_E07 (0x8000)
128 #define GPIO_PAR_FECI2CIRQ_E1MDIO_CANRX (0x0000)
129 #define GPIO_PAR_FECI2CIRQ_E1MDIO_SDA (0x0200)
130 #define GPIO_PAR_FECI2CIRQ_E1MDIO_EMDIO (0x0300)
131 #define GPIO_PAR_FECI2CIRQ_E1MDC_CANTX (0x0000)
132 #define GPIO_PAR_FECI2CIRQ_E1MDC_SCL (0x0080)
133 #define GPIO_PAR_FECI2CIRQ_E1MDC_EMDC (0x00C0)
135 /* Bit definitions and macros for GPIO_PAR_PCIBG */
136 #define GPIO_PAR_PCIBG_PCIBG0(x) (((x)&0x0003)<<0)
137 #define GPIO_PAR_PCIBG_PCIBG1(x) (((x)&0x0003)<<2)
138 #define GPIO_PAR_PCIBG_PCIBG2(x) (((x)&0x0003)<<4)
139 #define GPIO_PAR_PCIBG_PCIBG3(x) (((x)&0x0003)<<6)
140 #define GPIO_PAR_PCIBG_PCIBG4(x) (((x)&0x0003)<<8)
142 /* Bit definitions and macros for GPIO_PAR_PCIBR */
143 #define GPIO_PAR_PCIBR_PCIBR0(x) (((x)&0x0003)<<0)
144 #define GPIO_PAR_PCIBR_PCIBR1(x) (((x)&0x0003)<<2)
145 #define GPIO_PAR_PCIBR_PCIBR2(x) (((x)&0x0003)<<4)
146 #define GPIO_PAR_PCIBR_PCIBR3(x) (((x)&0x0003)<<6)
147 #define GPIO_PAR_PCIBR_PCIBR4(x) (((x)&0x0003)<<8)
149 /* Bit definitions and macros for GPIO_PAR_PSC3 */
150 #define GPIO_PAR_PSC3_TXD3 (0x04)
151 #define GPIO_PAR_PSC3_RXD3 (0x08)
152 #define GPIO_PAR_PSC3_RTS3(x) (((x)&0x03)<<4)
153 #define GPIO_PAR_PSC3_CTS3(x) (((x)&0x03)<<6)
154 #define GPIO_PAR_PSC3_CTS3_GPIO (0x00)
155 #define GPIO_PAR_PSC3_CTS3_BCLK (0x80)
156 #define GPIO_PAR_PSC3_CTS3_CTS (0xC0)
157 #define GPIO_PAR_PSC3_RTS3_GPIO (0x00)
158 #define GPIO_PAR_PSC3_RTS3_FSYNC (0x20)
159 #define GPIO_PAR_PSC3_RTS3_RTS (0x30)
160 #define GPIO_PAR_PSC3_CTS2_CANRX (0x40)
162 /* Bit definitions and macros for GPIO_PAR_PSC2 */
163 #define GPIO_PAR_PSC2_TXD2 (0x04)
164 #define GPIO_PAR_PSC2_RXD2 (0x08)
165 #define GPIO_PAR_PSC2_RTS2(x) (((x)&0x03)<<4)
166 #define GPIO_PAR_PSC2_CTS2(x) (((x)&0x03)<<6)
167 #define GPIO_PAR_PSC2_CTS2_GPIO (0x00)
168 #define GPIO_PAR_PSC2_CTS2_BCLK (0x80)
169 #define GPIO_PAR_PSC2_CTS2_CTS (0xC0)
170 #define GPIO_PAR_PSC2_RTS2_GPIO (0x00)
171 #define GPIO_PAR_PSC2_RTS2_CANTX (0x10)
172 #define GPIO_PAR_PSC2_RTS2_FSYNC (0x20)
173 #define GPIO_PAR_PSC2_RTS2_RTS (0x30)
175 /* Bit definitions and macros for GPIO_PAR_PSC1 */
176 #define GPIO_PAR_PSC1_TXD1 (0x04)
177 #define GPIO_PAR_PSC1_RXD1 (0x08)
178 #define GPIO_PAR_PSC1_RTS1(x) (((x)&0x03)<<4)
179 #define GPIO_PAR_PSC1_CTS1(x) (((x)&0x03)<<6)
180 #define GPIO_PAR_PSC1_CTS1_GPIO (0x00)
181 #define GPIO_PAR_PSC1_CTS1_BCLK (0x80)
182 #define GPIO_PAR_PSC1_CTS1_CTS (0xC0)
183 #define GPIO_PAR_PSC1_RTS1_GPIO (0x00)
184 #define GPIO_PAR_PSC1_RTS1_FSYNC (0x20)
185 #define GPIO_PAR_PSC1_RTS1_RTS (0x30)
187 /* Bit definitions and macros for GPIO_PAR_PSC0 */
188 #define GPIO_PAR_PSC0_TXD0 (0x04)
189 #define GPIO_PAR_PSC0_RXD0 (0x08)
190 #define GPIO_PAR_PSC0_RTS0(x) (((x)&0x03)<<4)
191 #define GPIO_PAR_PSC0_CTS0(x) (((x)&0x03)<<6)
192 #define GPIO_PAR_PSC0_CTS0_GPIO (0x00)
193 #define GPIO_PAR_PSC0_CTS0_BCLK (0x80)
194 #define GPIO_PAR_PSC0_CTS0_CTS (0xC0)
195 #define GPIO_PAR_PSC0_RTS0_GPIO (0x00)
196 #define GPIO_PAR_PSC0_RTS0_FSYNC (0x20)
197 #define GPIO_PAR_PSC0_RTS0_RTS (0x30)
199 /* Bit definitions and macros for GPIO_PAR_DSPI */
200 #define GPIO_PAR_DSPI_SOUT(x) (((x)&0x0003)<<0)
201 #define GPIO_PAR_DSPI_SIN(x) (((x)&0x0003)<<2)
202 #define GPIO_PAR_DSPI_SCK(x) (((x)&0x0003)<<4)
203 #define GPIO_PAR_DSPI_CS0(x) (((x)&0x0003)<<6)
204 #define GPIO_PAR_DSPI_CS2(x) (((x)&0x0003)<<8)
205 #define GPIO_PAR_DSPI_CS3(x) (((x)&0x0003)<<10)
206 #define GPIO_PAR_DSPI_CS5 (0x1000)
207 #define GPIO_PAR_DSPI_CS3_GPIO (0x0000)
208 #define GPIO_PAR_DSPI_CS3_CANTX (0x0400)
209 #define GPIO_PAR_DSPI_CS3_TOUT (0x0800)
210 #define GPIO_PAR_DSPI_CS3_DSPICS (0x0C00)
211 #define GPIO_PAR_DSPI_CS2_GPIO (0x0000)
212 #define GPIO_PAR_DSPI_CS2_CANTX (0x0100)
213 #define GPIO_PAR_DSPI_CS2_TOUT (0x0200)
214 #define GPIO_PAR_DSPI_CS2_DSPICS (0x0300)
215 #define GPIO_PAR_DSPI_CS0_GPIO (0x0000)
216 #define GPIO_PAR_DSPI_CS0_FSYNC (0x0040)
217 #define GPIO_PAR_DSPI_CS0_RTS (0x0080)
218 #define GPIO_PAR_DSPI_CS0_DSPICS (0x00C0)
219 #define GPIO_PAR_DSPI_SCK_GPIO (0x0000)
220 #define GPIO_PAR_DSPI_SCK_BCLK (0x0010)
221 #define GPIO_PAR_DSPI_SCK_CTS (0x0020)
222 #define GPIO_PAR_DSPI_SCK_SCK (0x0030)
223 #define GPIO_PAR_DSPI_SIN_GPIO (0x0000)
224 #define GPIO_PAR_DSPI_SIN_RXD (0x0008)
225 #define GPIO_PAR_DSPI_SIN_SIN (0x000C)
226 #define GPIO_PAR_DSPI_SOUT_GPIO (0x0000)
227 #define GPIO_PAR_DSPI_SOUT_TXD (0x0002)
228 #define GPIO_PAR_DSPI_SOUT_SOUT (0x0003)
230 /* Bit definitions and macros for GPIO_PAR_TIMER */
231 #define GPIO_PAR_TIMER_TOUT2 (0x01)
232 #define GPIO_PAR_TIMER_TIN2(x) (((x)&0x03)<<1)
233 #define GPIO_PAR_TIMER_TOUT3 (0x08)
234 #define GPIO_PAR_TIMER_TIN3(x) (((x)&0x03)<<4)
235 #define GPIO_PAR_TIMER_TIN3_CANRX (0x00)
236 #define GPIO_PAR_TIMER_TIN3_IRQ (0x20)
237 #define GPIO_PAR_TIMER_TIN3_TIN (0x30)
238 #define GPIO_PAR_TIMER_TIN2_CANRX (0x00)
239 #define GPIO_PAR_TIMER_TIN2_IRQ (0x04)
240 #define GPIO_PAR_TIMER_TIN2_TIN (0x06)
242 /*********************************************************************
244 *********************************************************************/
245 #define SLT_CR_RUN (0x04000000)
246 #define SLT_CR_IEN (0x02000000)
247 #define SLT_CR_TEN (0x01000000)
249 #define SLT_SR_BE (0x02000000)
250 #define SLT_SR_ST (0x01000000)
252 /*********************************************************************
253 * Interrupt Controller (INTC)
254 *********************************************************************/
255 #define INT0_LO_RSVD0 (0)
256 #define INT0_LO_EPORT1 (1)
257 #define INT0_LO_EPORT2 (2)
258 #define INT0_LO_EPORT3 (3)
259 #define INT0_LO_EPORT4 (4)
260 #define INT0_LO_EPORT5 (5)
261 #define INT0_LO_EPORT6 (6)
262 #define INT0_LO_EPORT7 (7)
263 #define INT0_LO_EP0ISR (15)
264 #define INT0_LO_EP1ISR (16)
265 #define INT0_LO_EP2ISR (17)
266 #define INT0_LO_EP3ISR (18)
267 #define INT0_LO_EP4ISR (19)
268 #define INT0_LO_EP5ISR (20)
269 #define INT0_LO_EP6ISR (21)
270 #define INT0_LO_USBISR (22)
271 #define INT0_LO_USBAISR (23)
272 #define INT0_LO_USB (24)
273 #define INT1_LO_DSPI_RFOF_TFUF (25)
274 #define INT1_LO_DSPI_RFOF (26)
275 #define INT1_LO_DSPI_RFDF (27)
276 #define INT1_LO_DSPI_TFUF (28)
277 #define INT1_LO_DSPI_TCF (29)
278 #define INT1_LO_DSPI_TFFF (30)
279 #define INT1_LO_DSPI_EOQF (31)
281 #define INT0_HI_UART3 (32)
282 #define INT0_HI_UART2 (33)
283 #define INT0_HI_UART1 (34)
284 #define INT0_HI_UART0 (35)
285 #define INT0_HI_COMMTIM_TC (36)
286 #define INT0_HI_SEC (37)
287 #define INT0_HI_FEC1 (38)
288 #define INT0_HI_FEC0 (39)
289 #define INT0_HI_I2C (40)
290 #define INT0_HI_PCIARB (41)
291 #define INT0_HI_CBPCI (42)
292 #define INT0_HI_XLBPCI (43)
293 #define INT0_HI_XLBARB (47)
294 #define INT0_HI_DMA (48)
295 #define INT0_HI_CAN0_ERROR (49)
296 #define INT0_HI_CAN0_BUSOFF (50)
297 #define INT0_HI_CAN0_MBOR (51)
298 #define INT0_HI_SLT1 (53)
299 #define INT0_HI_SLT0 (54)
300 #define INT0_HI_CAN1_ERROR (55)
301 #define INT0_HI_CAN1_BUSOFF (56)
302 #define INT0_HI_CAN1_MBOR (57)
303 #define INT0_HI_GPT3 (59)
304 #define INT0_HI_GPT2 (60)
305 #define INT0_HI_GPT1 (61)
306 #define INT0_HI_GPT0 (62)
308 /*********************************************************************
309 * General Purpose Timers (GPTMR)
310 *********************************************************************/
311 /* Enable and Mode Select */
312 #define GPT_OCT(x) (x & 0x3)<<4 /* Output Compare Type */
313 #define GPT_ICT(x) (x & 0x3) /* Input Capture Type */
314 #define GPT_CTRL_WDEN 0x80 /* Watchdog Enable */
315 #define GPT_CTRL_CE 0x10 /* Counter Enable */
316 #define GPT_CTRL_STPCNT 0x04 /* Stop continous */
317 #define GPT_CTRL_ODRAIN 0x02 /* Open Drain */
318 #define GPT_CTRL_INTEN 0x01 /* Interrupt Enable */
319 #define GPT_MODE_GPIO(x) (x & 0x3)<<4 /* Gpio Mode Type */
320 #define GPT_TMS_ICT 0x01 /* Input Capture Enable */
321 #define GPT_TMS_OCT 0x02 /* Output Capture Enable */
322 #define GPT_TMS_PWM 0x03 /* PWM Capture Enable */
323 #define GPT_TMS_SGPIO 0x04 /* PWM Capture Enable */
325 #define GPT_PWM_WIDTH(x) (x & 0xffff)
328 #define GPT_STA_CAPTURE(x) (x & 0xffff)
330 #define GPT_OVFPIN_OVF(x) (x & 0x70)
331 #define GPT_OVFPIN_PIN 0x01
333 #define GPT_INT_TEXP 0x08
334 #define GPT_INT_PWMP 0x04
335 #define GPT_INT_COMP 0x02
336 #define GPT_INT_CAPT 0x01
338 /*********************************************************************
340 *********************************************************************/
342 /* Bit definitions and macros for SCR */
343 #define PCI_SCR_PE (0x80000000) /* Parity Error detected */
344 #define PCI_SCR_SE (0x40000000) /* System error signalled */
345 #define PCI_SCR_MA (0x20000000) /* Master aboart received */
346 #define PCI_SCR_TR (0x10000000) /* Target abort received */
347 #define PCI_SCR_TS (0x08000000) /* Target abort signalled */
348 #define PCI_SCR_DT (0x06000000) /* PCI_DEVSEL timing */
349 #define PCI_SCR_DP (0x01000000) /* Master data parity err */
350 #define PCI_SCR_FC (0x00800000) /* Fast back-to-back */
351 #define PCI_SCR_R (0x00400000) /* Reserved */
352 #define PCI_SCR_66M (0x00200000) /* 66Mhz */
353 #define PCI_SCR_C (0x00100000) /* Capabilities list */
354 #define PCI_SCR_F (0x00000200) /* Fast back-to-back enable */
355 #define PCI_SCR_S (0x00000100) /* SERR enable */
356 #define PCI_SCR_ST (0x00000080) /* Addr and Data stepping */
357 #define PCI_SCR_PER (0x00000040) /* Parity error response */
358 #define PCI_SCR_V (0x00000020) /* VGA palette snoop enable */
359 #define PCI_SCR_MW (0x00000010) /* Memory write and invalidate enable */
360 #define PCI_SCR_SP (0x00000008) /* Special cycle monitor or ignore */
361 #define PCI_SCR_B (0x00000004) /* Bus master enable */
362 #define PCI_SCR_M (0x00000002) /* Memory access control */
363 #define PCI_SCR_IO (0x00000001) /* I/O access control */
365 #define PCI_CR1_BIST(x) ((x & 0xFF) << 24) /* Built in self test */
366 #define PCI_CR1_HDR(x) ((x & 0xFF) << 16) /* Header type */
367 #define PCI_CR1_LTMR(x) ((x & 0xF8) << 8) /* Latency timer */
368 #define PCI_CR1_CLS(x) (x & 0x0F) /* Cache line size */
370 #define PCI_BAR_BAR0(x) (x & 0xFFFC0000)
371 #define PCI_BAR_BAR1(x) (x & 0xC0000000)
372 #define PCI_BAR_PREF (0x00000004) /* Prefetchable access */
373 #define PCI_BAR_RANGE (0x00000002) /* Fixed to 00 */
374 #define PCI_BAR_IO_M (0x00000001) /* IO / memory space */
376 #define PCI_CR2_MAXLAT(x) ((x & 0xFF) << 24) /* Maximum latency */
377 #define PCI_CR2_MINGNT(x) ((x & 0xFF) << 16) /* Minimum grant */
378 #define PCI_CR2_INTPIN(x) ((x & 0xFF) << 8) /* Interrupt Pin */
379 #define PCI_CR2_INTLIN(x) (x & 0xFF) /* Interrupt Line */
381 #define PCI_GSCR_DRD (0x80000000) /* Delayed read discarded */
382 #define PCI_GSCR_PE (0x20000000) /* PCI_PERR detected */
383 #define PCI_GSCR_SE (0x10000000) /* SERR detected */
384 #define PCI_GSCR_ER (0x08000000) /* Error response detected */
385 #define PCI_GSCR_DRDE (0x00008000) /* Delayed read discarded enable */
386 #define PCI_GSCR_PEE (0x00002000) /* PERR detected interrupt enable */
387 #define PCI_GSCR_SEE (0x00001000) /* SERR detected interrupt enable */
388 #define PCI_GSCR_PR (0x00000001) /* PCI reset */
390 #define PCI_TCR1_LD (0x01000000) /* Latency rule disable */
391 #define PCI_TCR1_PID (0x00020000) /* Prefetch invalidate and disable */
392 #define PCI_TCR1_P (0x00010000) /* Prefetch reads */
393 #define PCI_TCR1_WCD (0x00000100) /* Write combine disable */
395 #define PCI_TCR1_B5E (0x00002000) /* */
396 #define PCI_TCR1_B4E (0x00001000) /* */
397 #define PCI_TCR1_B3E (0x00000800) /* */
398 #define PCI_TCR1_B2E (0x00000400) /* */
399 #define PCI_TCR1_B1E (0x00000200) /* */
400 #define PCI_TCR1_B0E (0x00000100) /* */
401 #define PCI_TCR1_CR (0x00000001) /* */
403 #define PCI_TBATR_BAT0(x) (x & 0xFFFC0000)
404 #define PCI_TBATR_BAT1(x) (x & 0xC0000000)
405 #define PCI_TBATR_EN (0x00000001) /* Enable */
407 #define PCI_IWCR_W0C_IO (0x08000000) /* Windows Maps to PCI I/O */
408 #define PCI_IWCR_W0C_PRC_RDMUL (0x04000000) /* PCI Memory Read multiple */
409 #define PCI_IWCR_W0C_PRC_RDLN (0x02000000) /* PCI Memory Read line */
410 #define PCI_IWCR_W0C_PRC_RD (0x00000000) /* PCI Memory Read */
411 #define PCI_IWCR_W0C_EN (0x01000000) /* Enable - Register initialize */
412 #define PCI_IWCR_W1C_IO (0x00080000) /* Windows Maps to PCI I/O */
413 #define PCI_IWCR_W1C_PRC_RDMUL (0x00040000) /* PCI Memory Read multiple */
414 #define PCI_IWCR_W1C_PRC_RDLN (0x00020000) /* PCI Memory Read line */
415 #define PCI_IWCR_W1C_PRC_RD (0x00000000) /* PCI Memory Read */
416 #define PCI_IWCR_W1C_EN (0x00010000) /* Enable - Register initialize */
417 #define PCI_IWCR_W2C_IO (0x00000800) /* Windows Maps to PCI I/O */
418 #define PCI_IWCR_W2C_PRC_RDMUL (0x00000400) /* PCI Memory Read multiple */
419 #define PCI_IWCR_W2C_PRC_RDLN (0x00000200) /* PCI Memory Read line */
420 #define PCI_IWCR_W2C_PRC_RD (0x00000000) /* PCI Memory Read */
421 #define PCI_IWCR_W2C_EN (0x00000100) /* Enable - Register initialize */
423 #define PCI_ICR_REE (0x04000000) /* Retry error enable */
424 #define PCI_ICR_IAE (0x02000000) /* Initiator abort enable */
425 #define PCI_ICR_TAE (0x01000000) /* Target abort enable */
426 #define PCI_ICR_MAXRETRY(x) ((x) & 0x000000FF)
428 #define PCIARB_ACR_DS (0x80000000)
429 #define PCIARB_ARC_EXTMINTEN(x) (((x)&0x1F) << 17)
430 #define PCIARB_ARC_INTMINTEN (0x00010000)
431 #define PCIARB_ARC_EXTMPRI(x) (((x)&0x1F) << 1)
432 #define PCIARB_ARC_INTMPRI (0x00000001)
434 #endif /* mcf547x_8x_h */
projects / people / ms / u-boot.git / blob