arch/mips/cpu/start.S

   1 /*
   2  *  Startup Code for MIPS32 CPU-core
   3  *
   4  *  Copyright (c) 2003  Wolfgang Denk <wd@denx.de>
   5  *
   6  * SPDX-License-Identifier:     GPL-2.0+
   7  */
   8
   9 #include <asm-offsets.h>
  10 #include <config.h>
  11 #include <asm/asm.h>
  12 #include <asm/regdef.h>
  13 #include <asm/mipsregs.h>
  14
  15 #ifndef CONFIG_SYS_MIPS_CACHE_MODE
  16 #define CONFIG_SYS_MIPS_CACHE_MODE CONF_CM_CACHABLE_NONCOHERENT
  17 #endif
  18
  19 #ifndef CONFIG_SYS_INIT_SP_ADDR
  20 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + \
  21                                 CONFIG_SYS_INIT_SP_OFFSET)
  22 #endif
  23
  24 #ifdef CONFIG_32BIT
  25 # define MIPS_RELOC     3
  26 # define STATUS_SET     0
  27 #endif
  28
  29 #ifdef CONFIG_64BIT
  30 # ifdef CONFIG_SYS_LITTLE_ENDIAN
  31 #  define MIPS64_R_INFO(ssym, r_type3, r_type2, r_type) \
  32         (((r_type) << 24) | ((r_type2) << 16) | ((r_type3) << 8) | (ssym))
  33 # else
  34 #  define MIPS64_R_INFO(ssym, r_type3, r_type2, r_type) \
  35         ((r_type) | ((r_type2) << 8) | ((r_type3) << 16) | (ssym) << 24)
  36 # endif
  37 # define MIPS_RELOC     MIPS64_R_INFO(0x00, 0x00, 0x12, 0x03)
  38 # define STATUS_SET     ST0_KX
  39 #endif
  40
  41         /*
  42          * For the moment disable interrupts, mark the kernel mode and
  43          * set ST0_KX so that the CPU does not spit fire when using
  44          * 64-bit addresses.
  45          */
  46         .macro  setup_c0_status set clr
  47         .set    push
  48         mfc0    t0, CP0_STATUS
  49         or      t0, ST0_CU0 | \set | 0x1f | \clr
  50         xor     t0, 0x1f | \clr
  51         mtc0    t0, CP0_STATUS
  52         .set    noreorder
  53         sll     zero, 3                         # ehb
  54         .set    pop
  55         .endm
  56
  57         .set noreorder
  58
  59 ENTRY(_start)
  60         /* U-Boot entry point */
  61         b       reset
  62          nop
  63
  64         .org 0x10
  65 #if defined(CONFIG_SYS_XWAY_EBU_BOOTCFG)
  66         /*
  67          * Almost all Lantiq XWAY SoC devices have an external bus unit (EBU) to
  68          * access external NOR flashes. If the board boots from NOR flash the
  69          * internal BootROM does a blind read at address 0xB0000010 to read the
  70          * initial configuration for that EBU in order to access the flash
  71          * device with correct parameters. This config option is board-specific.
  72          */
  73         .word CONFIG_SYS_XWAY_EBU_BOOTCFG
  74         .word 0x0
  75 #elif defined(CONFIG_MALTA)
  76         /*
  77          * Linux expects the Board ID here.
  78          */
  79         .word 0x00000420        # 0x420 (Malta Board with CoreLV)
  80         .word 0x00000000
  81 #endif
  82
  83         .org 0x200
  84         /* TLB refill, 32 bit task */
  85 1:      b       1b
  86          nop
  87
  88         .org 0x280
  89         /* XTLB refill, 64 bit task */
  90 1:      b       1b
  91          nop
  92
  93         .org 0x300
  94         /* Cache error exception */
  95 1:      b       1b
  96          nop
  97
  98         .org 0x380
  99         /* General exception */
 100 1:      b       1b
 101          nop
 102
 103         .org 0x400
 104         /* Catch interrupt exceptions */
 105 1:      b       1b
 106          nop
 107
 108         .org 0x480
 109         /* EJTAG debug exception */
 110 1:      b       1b
 111          nop
 112
 113         .align 4
 114 reset:
 115
 116         /* Clear watch registers */
 117         MTC0    zero, CP0_WATCHLO
 118         mtc0    zero, CP0_WATCHHI
 119
 120         /* WP(Watch Pending), SW0/1 should be cleared */
 121         mtc0    zero, CP0_CAUSE
 122
 123         setup_c0_status STATUS_SET 0
 124
 125         /* Init Timer */
 126         mtc0    zero, CP0_COUNT
 127         mtc0    zero, CP0_COMPARE
 128
 129 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
 130         /* CONFIG0 register */
 131         li      t0, CONF_CM_UNCACHED
 132         mtc0    t0, CP0_CONFIG
 133 #endif
 134
 135         /*
 136          * Initialize $gp, force pointer sized alignment of bal instruction to
 137          * forbid the compiler to put nop's between bal and _gp. This is
 138          * required to keep _gp and ra aligned to 8 byte.
 139          */
 140         .align  PTRLOG
 141         bal     1f
 142          nop
 143         PTR     _gp
 144 1:
 145         PTR_L   gp, 0(ra)
 146
 147 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
 148         /* Initialize any external memory */
 149         PTR_LA  t9, lowlevel_init
 150         jalr    t9
 151          nop
 152
 153         /* Initialize caches... */
 154         PTR_LA  t9, mips_cache_reset
 155         jalr    t9
 156          nop
 157
 158         /* ... and enable them */
 159         li      t0, CONFIG_SYS_MIPS_CACHE_MODE
 160         mtc0    t0, CP0_CONFIG
 161 #endif
 162
 163         /* Set up temporary stack */
 164         li      t0, -16
 165         PTR_LI  t1, CONFIG_SYS_INIT_SP_ADDR
 166         and     sp, t1, t0              # force 16 byte alignment
 167         PTR_SUB sp, sp, GD_SIZE         # reserve space for gd
 168         and     sp, sp, t0              # force 16 byte alignment
 169         move    k0, sp                  # save gd pointer
 170 #ifdef CONFIG_SYS_MALLOC_F_LEN
 171         li      t2, CONFIG_SYS_MALLOC_F_LEN
 172         PTR_SUB sp, sp, t2              # reserve space for early malloc
 173         and     sp, sp, t0              # force 16 byte alignment
 174 #endif
 175         move    fp, sp
 176
 177         /* Clear gd */
 178         move    t0, k0
 179 1:
 180         PTR_S   zero, 0(t0)
 181         blt     t0, t1, 1b
 182          PTR_ADDI t0, PTRSIZE
 183
 184 #ifdef CONFIG_SYS_MALLOC_F_LEN
 185         PTR_S   sp, GD_MALLOC_BASE(k0)  # gd->malloc_base offset
 186 #endif
 187
 188         move    a0, zero                # a0 <-- boot_flags = 0
 189         PTR_LA  t9, board_init_f
 190         jr      t9
 191          move   ra, zero
 192
 193         END(_start)
 194
 195 /*
 196  * void relocate_code (addr_sp, gd, addr_moni)
 197  *
 198  * This "function" does not return, instead it continues in RAM
 199  * after relocating the monitor code.
 200  *
 201  * a0 = addr_sp
 202  * a1 = gd
 203  * a2 = destination address
 204  */
 205 ENTRY(relocate_code)
 206         move    sp, a0                  # set new stack pointer
 207         move    fp, sp
 208
 209         move    s0, a1                  # save gd in s0
 210         move    s2, a2                  # save destination address in s2
 211
 212         PTR_LI  t0, CONFIG_SYS_MONITOR_BASE
 213         PTR_SUB s1, s2, t0              # s1 <-- relocation offset
 214
 215         PTR_LA  t3, in_ram
 216         PTR_L   t2, -(3 * PTRSIZE)(t3)  # t2 <-- __image_copy_end
 217         move    t1, a2
 218
 219         PTR_ADD gp, s1                  # adjust gp
 220
 221         /*
 222          * t0 = source address
 223          * t1 = target address
 224          * t2 = source end address
 225          */
 226 1:
 227         PTR_L   t3, 0(t0)
 228         PTR_S   t3, 0(t1)
 229         PTR_ADDU t0, PTRSIZE
 230         blt     t0, t2, 1b
 231          PTR_ADDU t1, PTRSIZE
 232
 233         /* If caches were enabled, we would have to flush them here. */
 234         PTR_SUB a1, t1, s2              # a1 <-- size
 235         PTR_LA  t9, flush_cache
 236         jalr    t9
 237          move   a0, s2                  # a0 <-- destination address
 238
 239         /* Jump to where we've relocated ourselves */
 240         PTR_ADDI t0, s2, in_ram - _start
 241         jr      t0
 242          nop
 243
 244         PTR     __rel_dyn_end
 245         PTR     __rel_dyn_start
 246         PTR     __image_copy_end
 247         PTR     _GLOBAL_OFFSET_TABLE_
 248         PTR     num_got_entries
 249
 250 in_ram:
 251         /*
 252          * Now we want to update GOT.
 253          *
 254          * GOT[0] is reserved. GOT[1] is also reserved for the dynamic object
 255          * generated by GNU ld. Skip these reserved entries from relocation.
 256          */
 257         PTR_L   t3, -(1 * PTRSIZE)(t0)  # t3 <-- num_got_entries
 258         PTR_L   t8, -(2 * PTRSIZE)(t0)  # t8 <-- _GLOBAL_OFFSET_TABLE_
 259         PTR_ADD t8, s1                  # t8 now holds relocated _G_O_T_
 260         PTR_ADDI t8, t8, 2 * PTRSIZE    # skipping first two entries
 261         PTR_LI  t2, 2
 262 1:
 263         PTR_L   t1, 0(t8)
 264         beqz    t1, 2f
 265          PTR_ADD t1, s1
 266         PTR_S   t1, 0(t8)
 267 2:
 268         PTR_ADDI t2, 1
 269         blt     t2, t3, 1b
 270          PTR_ADDI t8, PTRSIZE
 271
 272         /* Update dynamic relocations */
 273         PTR_L   t1, -(4 * PTRSIZE)(t0)  # t1 <-- __rel_dyn_start
 274         PTR_L   t2, -(5 * PTRSIZE)(t0)  # t2 <-- __rel_dyn_end
 275
 276         b       2f                      # skip first reserved entry
 277          PTR_ADDI t1, 2 * PTRSIZE
 278
 279 1:
 280         lw      t8, -4(t1)              # t8 <-- relocation info
 281
 282         PTR_LI  t3, MIPS_RELOC
 283         bne     t8, t3, 2f              # skip non-MIPS_RELOC entries
 284          nop
 285
 286         PTR_L   t3, -(2 * PTRSIZE)(t1)  # t3 <-- location to fix up in FLASH
 287
 288         PTR_L   t8, 0(t3)               # t8 <-- original pointer
 289         PTR_ADD t8, s1                  # t8 <-- adjusted pointer
 290
 291         PTR_ADD t3, s1                  # t3 <-- location to fix up in RAM
 292         PTR_S   t8, 0(t3)
 293
 294 2:
 295         blt     t1, t2, 1b
 296          PTR_ADDI t1, 2 * PTRSIZE       # each rel.dyn entry is 2*PTRSIZE bytes
 297
 298         /*
 299          * Clear BSS
 300          *
 301          * GOT is now relocated. Thus __bss_start and __bss_end can be
 302          * accessed directly via $gp.
 303          */
 304         PTR_LA  t1, __bss_start         # t1 <-- __bss_start
 305         PTR_LA  t2, __bss_end           # t2 <-- __bss_end
 306
 307 1:
 308         PTR_S   zero, 0(t1)
 309         blt     t1, t2, 1b
 310          PTR_ADDI t1, PTRSIZE
 311
 312         move    a0, s0                  # a0 <-- gd
 313         move    a1, s2
 314         PTR_LA  t9, board_init_r
 315         jr      t9
 316          move   ra, zero
 317
 318         END(relocate_code)