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git.ipfire.org Git - people/ms/u-boot.git/blob - arch/nios2/cpu/interrupts.c
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2 * (C) Copyright 2000-2002
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * (C) Copyright 2004, Psyent Corporation <www.psyent.com>
6 * Scott McNutt <smcnutt@psyent.com>
8 * See file CREDITS for list of people who contributed to this
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of
14 * the License, or (at your option) any later version.
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
30 #include <asm/types.h>
32 #include <asm/ptrace.h>
36 #ifdef CONFIG_STATUS_LED
37 #include <status_led.h>
40 #if defined(CONFIG_SYS_NIOS_TMRBASE) && !defined(CONFIG_SYS_NIOS_TMRIRQ)
41 #error CONFIG_SYS_NIOS_TMRIRQ not defined (see documentation)
44 /****************************************************************************/
47 interrupt_handler_t
*handler
;
52 static struct irq_action vecs
[32];
54 /*************************************************************************/
55 volatile ulong timestamp
= 0;
57 void reset_timer (void)
59 nios_timer_t
*tmr
=(nios_timer_t
*)CONFIG_SYS_NIOS_TMRBASE
;
61 /* From Embedded Peripherals Handbook:
63 * "When the hardware is configured with Writeable period
64 * disabled, writing to one of the period_n registers causes
65 * the counter to reset to the fixed Timeout Period specified
66 * at system generation time."
68 * Here we force a reload to prevent early timeouts from
69 * get_timer() when the interrupt period is greater than
72 * Simply write to periodl with its own value to force an
73 * internal counter reload, THEN reset the timestamp.
75 writel (readl (&tmr
->periodl
), &tmr
->periodl
);
78 /* From Embedded Peripherals Handbook:
80 * "Writing to one of the period_n registers stops the internal
81 * counter, except when the hardware is configured with Start/Stop
82 * control bits off. If Start/Stop control bits is off, writing
83 * either register does not stop the counter."
85 * In order to accomodate either configuration, the control
86 * register is re-written. If the counter is stopped, it will
87 * be restarted. If it is running, the write is essentially
90 writel (NIOS_TIMER_ITO
| NIOS_TIMER_CONT
| NIOS_TIMER_START
,
95 ulong
get_timer (ulong base
)
98 return (timestamp
- base
);
101 void set_timer (ulong t
)
107 /* The board must handle this interrupt if a timer is not
110 #if defined(CONFIG_SYS_NIOS_TMRBASE)
111 void tmr_isr (void *arg
)
113 nios_timer_t
*tmr
= (nios_timer_t
*)arg
;
114 /* Interrupt is cleared by writing anything to the
117 writel (0, &tmr
->status
);
118 timestamp
+= CONFIG_SYS_NIOS_TMRMS
;
119 #ifdef CONFIG_STATUS_LED
120 status_led_tick(timestamp
);
124 static void tmr_init (void)
126 nios_timer_t
*tmr
=(nios_timer_t
*)CONFIG_SYS_NIOS_TMRBASE
;
128 writel (0, &tmr
->status
);
129 writel (0, &tmr
->control
);
130 writel (NIOS_TIMER_STOP
, &tmr
->control
);
132 #if defined(CONFIG_SYS_NIOS_TMRCNT)
133 writel (CONFIG_SYS_NIOS_TMRCNT
& 0xffff, &tmr
->periodl
);
134 writel ((CONFIG_SYS_NIOS_TMRCNT
>> 16) & 0xffff, &tmr
->periodh
);
136 writel (NIOS_TIMER_ITO
| NIOS_TIMER_CONT
| NIOS_TIMER_START
,
138 irq_install_handler (CONFIG_SYS_NIOS_TMRIRQ
, tmr_isr
, (void *)tmr
);
141 #endif /* CONFIG_SYS_NIOS_TMRBASE */
143 /*************************************************************************/
144 int disable_interrupts (void)
146 int val
= rdctl (CTL_STATUS
);
147 wrctl (CTL_STATUS
, val
& ~STATUS_IE
);
148 return (val
& STATUS_IE
);
151 void enable_interrupts( void )
153 int val
= rdctl (CTL_STATUS
);
154 wrctl (CTL_STATUS
, val
| STATUS_IE
);
157 void external_interrupt (struct pt_regs
*regs
)
160 struct irq_action
*act
;
162 /* Evaluate only irqs that are both enabled AND pending */
163 irqs
= rdctl (CTL_IENABLE
) & rdctl (CTL_IPENDING
);
166 /* Assume (as does the Nios2 HAL) that bit 0 is highest
167 * priority. NOTE: There is ALWAYS a handler assigned
168 * (the default if no other).
172 act
->handler (act
->arg
);
180 static void def_hdlr (void *arg
)
182 unsigned irqs
= rdctl (CTL_IENABLE
);
184 /* Disable the individual interrupt -- with gratuitous
187 irqs
&= ~(1 << (int)arg
);
188 wrctl (CTL_IENABLE
, irqs
);
189 printf ("WARNING: Disabling unhandled interrupt: %d\n",
193 /*************************************************************************/
194 void irq_install_handler (int irq
, interrupt_handler_t
*hdlr
, void *arg
)
198 struct irq_action
*act
;
199 unsigned ena
= rdctl (CTL_IENABLE
);
201 if ((irq
< 0) || (irq
> 31))
205 flag
= disable_interrupts ();
209 ena
|= (1 << irq
); /* enable */
211 act
->handler
= def_hdlr
;
212 act
->arg
= (void *)irq
;
213 ena
&= ~(1 << irq
); /* disable */
215 wrctl (CTL_IENABLE
, ena
);
216 if (flag
) enable_interrupts ();
220 int interrupt_init (void)
224 /* Assign the default handler to all */
225 for (i
= 0; i
< 32; i
++) {
226 vecs
[i
].handler
= def_hdlr
;
227 vecs
[i
].arg
= (void *)i
;
231 #if defined(CONFIG_SYS_NIOS_TMRBASE)
235 enable_interrupts ();
240 /*************************************************************************/
241 #if defined(CONFIG_CMD_IRQ)
242 int do_irqinfo (cmd_tbl_t
*cmdtp
, int flag
, int argc
, char *argv
[])
245 struct irq_action
*act
= vecs
;
247 printf ("\nInterrupt-Information:\n\n");
248 printf ("Nr Routine Arg Count\n");
249 printf ("-----------------------------\n");
251 for (i
=0; i
<32; i
++) {
252 if (act
->handler
!= def_hdlr
) {
253 printf ("%02d %08lx %08lx %d\n",