arch/powerpc/cpu/mpc512x/fixed_sdram.c

   1 /*
   2  * (C) Copyright 2007-2009 DENX Software Engineering
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 #include <common.h>
   8 #include <asm/io.h>
   9 #include <asm/mpc512x.h>
  10
  11 /*
  12  * MDDRC Config Runtime Settings
  13  */
  14 ddr512x_config_t default_mddrc_config = {
  15         .ddr_sys_config   = CONFIG_SYS_MDDRC_SYS_CFG,
  16         .ddr_time_config0 = CONFIG_SYS_MDDRC_TIME_CFG0,
  17         .ddr_time_config1 = CONFIG_SYS_MDDRC_TIME_CFG1,
  18         .ddr_time_config2 = CONFIG_SYS_MDDRC_TIME_CFG2,
  19 };
  20
  21 u32 default_init_seq[] = {
  22         CONFIG_SYS_DDRCMD_NOP,
  23         CONFIG_SYS_DDRCMD_NOP,
  24         CONFIG_SYS_DDRCMD_NOP,
  25         CONFIG_SYS_DDRCMD_NOP,
  26         CONFIG_SYS_DDRCMD_NOP,
  27         CONFIG_SYS_DDRCMD_NOP,
  28         CONFIG_SYS_DDRCMD_NOP,
  29         CONFIG_SYS_DDRCMD_NOP,
  30         CONFIG_SYS_DDRCMD_NOP,
  31         CONFIG_SYS_DDRCMD_NOP,
  32         CONFIG_SYS_DDRCMD_PCHG_ALL,
  33         CONFIG_SYS_DDRCMD_NOP,
  34         CONFIG_SYS_DDRCMD_RFSH,
  35         CONFIG_SYS_DDRCMD_NOP,
  36         CONFIG_SYS_DDRCMD_RFSH,
  37         CONFIG_SYS_DDRCMD_NOP,
  38         CONFIG_SYS_MICRON_INIT_DEV_OP,
  39         CONFIG_SYS_DDRCMD_NOP,
  40         CONFIG_SYS_DDRCMD_EM2,
  41         CONFIG_SYS_DDRCMD_NOP,
  42         CONFIG_SYS_DDRCMD_PCHG_ALL,
  43         CONFIG_SYS_DDRCMD_EM2,
  44         CONFIG_SYS_DDRCMD_EM3,
  45         CONFIG_SYS_DDRCMD_EN_DLL,
  46         CONFIG_SYS_MICRON_INIT_DEV_OP,
  47         CONFIG_SYS_DDRCMD_PCHG_ALL,
  48         CONFIG_SYS_DDRCMD_RFSH,
  49         CONFIG_SYS_MICRON_INIT_DEV_OP,
  50         CONFIG_SYS_DDRCMD_OCD_DEFAULT,
  51         CONFIG_SYS_DDRCMD_PCHG_ALL,
  52         CONFIG_SYS_DDRCMD_NOP
  53 };
  54
  55 /*
  56  * fixed sdram init:
  57  * The board doesn't use memory modules that have serial presence
  58  * detect or similar mechanism for discovery of the DRAM settings
  59  */
  60 long int fixed_sdram(ddr512x_config_t *mddrc_config,
  61                         u32 *dram_init_seq, int seq_sz)
  62 {
  63         volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
  64         u32 msize = CONFIG_SYS_MAX_RAM_SIZE;
  65         u32 msize_log2 = __ilog2(msize);
  66         u32 i;
  67
  68         /* take default settings and init sequence if necessary */
  69         if (mddrc_config == NULL)
  70                 mddrc_config = &default_mddrc_config;
  71         if (dram_init_seq == NULL) {
  72                 dram_init_seq = default_init_seq;
  73                 seq_sz = sizeof(default_init_seq)/sizeof(u32);
  74         }
  75
  76         /* Initialize IO Control */
  77         out_be32(&im->io_ctrl.io_control_mem, CONFIG_SYS_IOCTRL_MUX_DDR);
  78
  79         /* Initialize DDR Local Window */
  80         out_be32(&im->sysconf.ddrlaw.bar, CONFIG_SYS_DDR_BASE & 0xFFFFF000);
  81         out_be32(&im->sysconf.ddrlaw.ar, msize_log2 - 1);
  82         sync_law(&im->sysconf.ddrlaw.ar);
  83
  84         /* DDR Enable */
  85         /*
  86          * the "enable" combination: DRAM controller out of reset,
  87          * clock enabled, command mode -- BUT leave CKE low for now
  88          */
  89         i = MDDRC_SYS_CFG_EN & ~MDDRC_SYS_CFG_CKE_MASK;
  90         out_be32(&im->mddrc.ddr_sys_config, i);
  91         /* maintain 200 microseconds of stable power and clock */
  92         udelay(200);
  93         /* apply a NOP, it shouldn't harm */
  94         out_be32(&im->mddrc.ddr_command, CONFIG_SYS_DDRCMD_NOP);
  95         /* now assert CKE (high) */
  96         i |= MDDRC_SYS_CFG_CKE_MASK;
  97         out_be32(&im->mddrc.ddr_sys_config, i);
  98
  99         /* Initialize DDR Priority Manager */
 100         out_be32(&im->mddrc.prioman_config1, CONFIG_SYS_MDDRCGRP_PM_CFG1);
 101         out_be32(&im->mddrc.prioman_config2, CONFIG_SYS_MDDRCGRP_PM_CFG2);
 102         out_be32(&im->mddrc.hiprio_config, CONFIG_SYS_MDDRCGRP_HIPRIO_CFG);
 103         out_be32(&im->mddrc.lut_table0_main_upper, CONFIG_SYS_MDDRCGRP_LUT0_MU);
 104         out_be32(&im->mddrc.lut_table0_main_lower, CONFIG_SYS_MDDRCGRP_LUT0_ML);
 105         out_be32(&im->mddrc.lut_table1_main_upper, CONFIG_SYS_MDDRCGRP_LUT1_MU);
 106         out_be32(&im->mddrc.lut_table1_main_lower, CONFIG_SYS_MDDRCGRP_LUT1_ML);
 107         out_be32(&im->mddrc.lut_table2_main_upper, CONFIG_SYS_MDDRCGRP_LUT2_MU);
 108         out_be32(&im->mddrc.lut_table2_main_lower, CONFIG_SYS_MDDRCGRP_LUT2_ML);
 109         out_be32(&im->mddrc.lut_table3_main_upper, CONFIG_SYS_MDDRCGRP_LUT3_MU);
 110         out_be32(&im->mddrc.lut_table3_main_lower, CONFIG_SYS_MDDRCGRP_LUT3_ML);
 111         out_be32(&im->mddrc.lut_table4_main_upper, CONFIG_SYS_MDDRCGRP_LUT4_MU);
 112         out_be32(&im->mddrc.lut_table4_main_lower, CONFIG_SYS_MDDRCGRP_LUT4_ML);
 113         out_be32(&im->mddrc.lut_table0_alternate_upper, CONFIG_SYS_MDDRCGRP_LUT0_AU);
 114         out_be32(&im->mddrc.lut_table0_alternate_lower, CONFIG_SYS_MDDRCGRP_LUT0_AL);
 115         out_be32(&im->mddrc.lut_table1_alternate_upper, CONFIG_SYS_MDDRCGRP_LUT1_AU);
 116         out_be32(&im->mddrc.lut_table1_alternate_lower, CONFIG_SYS_MDDRCGRP_LUT1_AL);
 117         out_be32(&im->mddrc.lut_table2_alternate_upper, CONFIG_SYS_MDDRCGRP_LUT2_AU);
 118         out_be32(&im->mddrc.lut_table2_alternate_lower, CONFIG_SYS_MDDRCGRP_LUT2_AL);
 119         out_be32(&im->mddrc.lut_table3_alternate_upper, CONFIG_SYS_MDDRCGRP_LUT3_AU);
 120         out_be32(&im->mddrc.lut_table3_alternate_lower, CONFIG_SYS_MDDRCGRP_LUT3_AL);
 121         out_be32(&im->mddrc.lut_table4_alternate_upper, CONFIG_SYS_MDDRCGRP_LUT4_AU);
 122         out_be32(&im->mddrc.lut_table4_alternate_lower, CONFIG_SYS_MDDRCGRP_LUT4_AL);
 123
 124         /*
 125          * Initialize MDDRC
 126          *  put MDDRC in CMD mode and
 127          *  set the max time between refreshes to 0 during init process
 128          */
 129         out_be32(&im->mddrc.ddr_sys_config,
 130                 mddrc_config->ddr_sys_config | MDDRC_SYS_CFG_CMD_MASK);
 131         out_be32(&im->mddrc.ddr_time_config0,
 132                 mddrc_config->ddr_time_config0 & MDDRC_REFRESH_ZERO_MASK);
 133         out_be32(&im->mddrc.ddr_time_config1,
 134                 mddrc_config->ddr_time_config1);
 135         out_be32(&im->mddrc.ddr_time_config2,
 136                 mddrc_config->ddr_time_config2);
 137
 138         /* Initialize DDR with either default or supplied init sequence */
 139         for (i = 0; i < seq_sz; i++)
 140                 out_be32(&im->mddrc.ddr_command, dram_init_seq[i]);
 141
 142         /* Start MDDRC */
 143         out_be32(&im->mddrc.ddr_time_config0, mddrc_config->ddr_time_config0);
 144         out_be32(&im->mddrc.ddr_sys_config, mddrc_config->ddr_sys_config);
 145
 146         /* Allow for the DLL to startup before accessing data */
 147         udelay(10);
 148
 149         msize = get_ram_size(CONFIG_SYS_DDR_BASE, CONFIG_SYS_MAX_RAM_SIZE);
 150         /* Fix DDR Local Window for new size */
 151         out_be32(&im->sysconf.ddrlaw.ar, __ilog2(msize) - 1);
 152         sync_law(&im->sysconf.ddrlaw.ar);
 153
 154         return msize;
 155 }