arch/powerpc/cpu/mpc5xxx/firmware_sc_task_bestcomm.impl.S

   1 /*
   2  * Copyright (C) 2001, Software Center, Motorola China.
   3  *
   4  * This file contains microcode for the FEC controller of the MPC5200 CPU.
   5  */
   6
   7 #include <config.h>
   8
   9 /* sas/sccg, gas target */
  10 .section        smartdmaInitData,"aw",@progbits /* Initialized data for task variables */
  11 .section        smartdmaTaskTable,"aw",@progbits        /* Task tables */
  12 .align  9
  13 .globl taskTable
  14 taskTable:
  15 .globl scEthernetRecv_Entry
  16 scEthernetRecv_Entry:           /* Task 0 */
  17 .long   scEthernetRecv_TDT - taskTable  /* Task 0 Descriptor Table */
  18 .long   scEthernetRecv_TDT - taskTable + 0x000000a4
  19 .long   scEthernetRecv_VarTab - taskTable       /* Task 0 Variable Table */
  20 .long   scEthernetRecv_FDT - taskTable + 0x03   /* Task 0 Function Descriptor Table & Flags */
  21 .long   0x00000000
  22 .long   0x00000000
  23 .long   scEthernetRecv_CSave - taskTable        /* Task 0 context save space */
  24 .long   CONFIG_SYS_MBAR
  25 .globl scEthernetXmit_Entry
  26 scEthernetXmit_Entry:           /* Task 1 */
  27 .long   scEthernetXmit_TDT - taskTable  /* Task 1 Descriptor Table */
  28 .long   scEthernetXmit_TDT - taskTable + 0x000000d0
  29 .long   scEthernetXmit_VarTab - taskTable       /* Task 1 Variable Table */
  30 .long   scEthernetXmit_FDT - taskTable + 0x03   /* Task 1 Function Descriptor Table & Flags */
  31 .long   0x00000000
  32 .long   0x00000000
  33 .long   scEthernetXmit_CSave - taskTable        /* Task 1 context save space */
  34 .long   CONFIG_SYS_MBAR
  35
  36
  37 .globl scEthernetRecv_TDT
  38 scEthernetRecv_TDT:     /* Task 0 Descriptor Table */
  39 .long   0xc4c50000      /* 0000:  LCDEXT: idx0 = var9 + var10; idx0 once var0; idx0 += inc0 */
  40 .long   0x84c5e000      /* 0004:  LCD: idx1 = var9 + var11; ; idx1 += inc0 */
  41 .long   0x10001f08      /* 0008:    DRD1A: var7 = idx1; FN=0 MORE init=0 WS=0 RS=0 */
  42 .long   0x10000380      /* 000C:    DRD1A: var0 = *idx0; FN=0 MORE init=0 WS=0 RS=0 */
  43 .long   0x00000f88      /* 0010:    DRD1A: var3 = *idx1; FN=0 init=0 WS=0 RS=0 */
  44 .long   0x81980000      /* 0014:  LCD: idx0 = var3; idx0 once var0; idx0 += inc0 */
  45 .long   0x10000780      /* 0018:    DRD1A: var1 = *idx0; FN=0 MORE init=0 WS=0 RS=0 */
  46 .long   0x60000000      /* 001C:    DRD2A: EU0=0 EU1=0 EU2=0 EU3=0 EXT init=0 WS=0 RS=0 */
  47 .long   0x010cf04c      /* 0020:    DRD2B1: var4 = EU3(); EU3(var1,var12)  */
  48 .long   0x82180349      /* 0024:  LCD: idx0 = var4; idx0 != var13; idx0 += inc1 */
  49 .long   0x81c68004      /* 0028:    LCD: idx1 = var3 + var13 + 4; idx1 once var0; idx1 += inc0 */
  50 .long   0x70000000      /* 002C:      DRD2A: EU0=0 EU1=0 EU2=0 EU3=0 EXT MORE init=0 WS=0 RS=0 */
  51 .long   0x018cf04e      /* 0030:      DRD2B1: var6 = EU3(); EU3(var1,var14)  */
  52 .long   0x70000000      /* 0034:      DRD2A: EU0=0 EU1=0 EU2=0 EU3=0 EXT MORE init=0 WS=0 RS=0 */
  53 .long   0x020cf04f      /* 0038:      DRD2B1: var8 = EU3(); EU3(var1,var15)  */
  54 .long   0x00000b88      /* 003C:      DRD1A: var2 = *idx1; FN=0 init=0 WS=0 RS=0 */
  55 .long   0x8000d184      /* 0040:    LCDEXT: idx1 = 0xf0003184; ; */
  56 .long   0xc6990452      /* 0044:    LCDEXT: idx2 = var13; idx2 < var17; idx2 += inc2 */
  57 .long   0x81486010      /* 0048:    LCD: idx3 = var2 + var16; ; idx3 += inc2 */
  58 .long   0x006acf88      /* 004C:      DRD1A: *idx3 = *idx1; FN=0 init=3 WS=1 RS=1 */
  59 .long   0x8000d184      /* 0050:    LCDEXT: idx1 = 0xf0003184; ; */
  60 .long   0x86810492      /* 0054:    LCD: idx2 = var13, idx3 = var2; idx2 < var18; idx2 += inc2, idx3 += inc2 */
  61 .long   0x006acf88      /* 0058:      DRD1A: *idx3 = *idx1; FN=0 init=3 WS=1 RS=1 */
  62 .long   0x8000d184      /* 005C:    LCDEXT: idx1 = 0xf0003184; ; */
  63 .long   0x868184d2      /* 0060:    LCD: idx2 = var13, idx3 = var3; idx2 < var19; idx2 += inc2, idx3 += inc2 */
  64 .long   0x000acf88      /* 0064:      DRD1A: *idx3 = *idx1; FN=0 init=0 WS=1 RS=1 */
  65 .long   0xc318839b      /* 0068:    LCDEXT: idx1 = var6; idx1 == var14; idx1 += inc3 */
  66 .long   0x80190000      /* 006C:    LCD: idx2 = var0; idx2 once var0; idx2 += inc0 */
  67 .long   0x04008468      /* 0070:      DRD1A: idx1 = var13; FN=0 INT init=0 WS=0 RS=0 */
  68 .long   0xc4038358      /* 0074:    LCDEXT: idx1 = var8, idx2 = var7; idx1 == var13; idx1 += inc3, idx2 += inc0 */
  69 .long   0x81c50000      /* 0078:    LCD: idx3 = var3 + var10; idx3 once var0; idx3 += inc0 */
  70 .long   0x1000cb18      /* 007C:      DRD1A: *idx2 = idx3; FN=0 MORE init=0 WS=0 RS=0 */
  71 .long   0x00000f18      /* 0080:      DRD1A: var3 = idx3; FN=0 init=0 WS=0 RS=0 */
  72 .long   0xc4188364      /* 0084:    LCDEXT: idx1 = var8; idx1 > var13; idx1 += inc4 */
  73 .long   0x83990000      /* 0088:    LCD: idx2 = var7; idx2 once var0; idx2 += inc0 */
  74 .long   0x10000c00      /* 008C:      DRD1A: var3 = var0; FN=0 MORE init=0 WS=0 RS=0 */
  75 .long   0x0000c800      /* 0090:      DRD1A: *idx2 = var0; FN=0 init=0 WS=0 RS=0 */
  76 .long   0x81988000      /* 0094:    LCD: idx1 = var3; idx1 once var0; idx1 += inc0 */
  77 .long   0x10000788      /* 0098:      DRD1A: var1 = *idx1; FN=0 MORE init=0 WS=0 RS=0 */
  78 .long   0x60000000      /* 009C:      DRD2A: EU0=0 EU1=0 EU2=0 EU3=0 EXT init=0 WS=0 RS=0 */
  79 .long   0x080cf04c      /* 00A0:      DRD2B1: idx0 = EU3(); EU3(var1,var12)  */
  80 .long   0x000001f8      /* 00A4(:0):    NOP */
  81
  82
  83 .globl scEthernetXmit_TDT
  84 scEthernetXmit_TDT:     /* Task 1 Descriptor Table */
  85 .long   0x80024800      /* 0000:  LCDEXT: idx0 = 0xf0008800; ; */
  86 .long   0x85c60004      /* 0004:  LCD: idx1 = var11 + var12 + 4; idx1 once var0; idx1 += inc0 */
  87 .long   0x10002308      /* 0008:    DRD1A: var8 = idx1; FN=0 MORE init=0 WS=0 RS=0 */
  88 .long   0x10000f88      /* 000C:    DRD1A: var3 = *idx1; FN=0 MORE init=0 WS=0 RS=0 */
  89 .long   0x00000380      /* 0010:    DRD1A: var0 = *idx0; FN=0 init=0 WS=0 RS=0 */
  90 .long   0x81980000      /* 0014:  LCD: idx0 = var3; idx0 once var0; idx0 += inc0 */
  91 .long   0x10000780      /* 0018:    DRD1A: var1 = *idx0; FN=0 MORE init=0 WS=0 RS=0 */
  92 .long   0x60000000      /* 001C:    DRD2A: EU0=0 EU1=0 EU2=0 EU3=0 EXT init=0 WS=0 RS=0 */
  93 .long   0x024cf04d      /* 0020:    DRD2B1: var9 = EU3(); EU3(var1,var13)  */
  94 .long   0x84980309      /* 0024:  LCD: idx0 = var9; idx0 != var12; idx0 += inc1 */
  95 .long   0xc0004003      /* 0028:    LCDEXT: idx1 = 0x00000003; ; */
  96 .long   0x81c60004      /* 002C:    LCD: idx2 = var3 + var12 + 4; idx2 once var0; idx2 += inc0 */
  97 .long   0x70000000      /* 0030:      DRD2A: EU0=0 EU1=0 EU2=0 EU3=0 EXT MORE init=0 WS=0 RS=0 */
  98 .long   0x010cf04e      /* 0034:      DRD2B1: var4 = EU3(); EU3(var1,var14)  */
  99 .long   0x70000000      /* 0038:      DRD2A: EU0=0 EU1=0 EU2=0 EU3=0 EXT MORE init=0 WS=0 RS=0 */
 100 .long   0x014cf04f      /* 003C:      DRD2B1: var5 = EU3(); EU3(var1,var15)  */
 101 .long   0x70000000      /* 0040:      DRD2A: EU0=0 EU1=0 EU2=0 EU3=0 EXT MORE init=0 WS=0 RS=0 */
 102 .long   0x028cf050      /* 0044:      DRD2B1: var10 = EU3(); EU3(var1,var16)  */
 103 .long   0x70000000      /* 0048:      DRD2A: EU0=0 EU1=0 EU2=0 EU3=0 EXT MORE init=0 WS=0 RS=0 */
 104 .long   0x018cf051      /* 004C:      DRD2B1: var6 = EU3(); EU3(var1,var17)  */
 105 .long   0x10000b90      /* 0050:      DRD1A: var2 = *idx2; FN=0 MORE init=0 WS=0 RS=0 */
 106 .long   0x60000000      /* 0054:      DRD2A: EU0=0 EU1=0 EU2=0 EU3=0 EXT init=0 WS=0 RS=0 */
 107 .long   0x01ccf0a1      /* 0058:      DRD2B1: var7 = EU3(); EU3(var2,idx1)  */
 108 .long   0xc2988312      /* 005C:    LCDEXT: idx1 = var5; idx1 > var12; idx1 += inc2 */
 109 .long   0x83490000      /* 0060:    LCD: idx2 = var6 + var18; idx2 once var0; idx2 += inc0 */
 110 .long   0x00001b10      /* 0064:      DRD1A: var6 = idx2; FN=0 init=0 WS=0 RS=0 */
 111 .long   0x8000d1a4      /* 0068:    LCDEXT: idx1 = 0xf00031a4; ; */
 112 .long   0x8301031c      /* 006C:    LCD: idx2 = var6, idx3 = var2; idx2 > var12; idx2 += inc3, idx3 += inc4 */
 113 .long   0x008ac798      /* 0070:      DRD1A: *idx1 = *idx3; FN=0 init=4 WS=1 RS=1 */
 114 .long   0x8000d1a4      /* 0074:    LCDEXT: idx1 = 0xf00031a4; ; */
 115 .long   0xc1430000      /* 0078:    LCDEXT: idx2 = var2 + var6; idx2 once var0; idx2 += inc0 */
 116 .long   0x82998312      /* 007C:    LCD: idx3 = var5; idx3 > var12; idx3 += inc2 */
 117 .long   0x088ac790      /* 0080:      DRD1A: *idx1 = *idx2; FN=0 TFD init=4 WS=1 RS=1 */
 118 .long   0x81988000      /* 0084:    LCD: idx1 = var3; idx1 once var0; idx1 += inc0 */
 119 .long   0x60000001      /* 0088:      DRD2A: EU0=0 EU1=0 EU2=0 EU3=1 EXT init=0 WS=0 RS=0 */
 120 .long   0x0c4cfc4d      /* 008C:      DRD2B1: *idx1 = EU3(); EU3(*idx1,var13)  */
 121 .long   0xc21883ad      /* 0090:    LCDEXT: idx1 = var4; idx1 == var14; idx1 += inc5 */
 122 .long   0x80190000      /* 0094:    LCD: idx2 = var0; idx2 once var0; idx2 += inc0 */
 123 .long   0x04008460      /* 0098:      DRD1A: idx1 = var12; FN=0 INT init=0 WS=0 RS=0 */
 124 .long   0xc4052305      /* 009C:    LCDEXT: idx1 = var8, idx2 = var10; idx2 == var12; idx1 += inc0, idx2 += inc5 */
 125 .long   0x81c98000      /* 00A0:    LCD: idx3 = var3 + var19; idx3 once var0; idx3 += inc0 */
 126 .long   0x1000c718      /* 00A4:      DRD1A: *idx1 = idx3; FN=0 MORE init=0 WS=0 RS=0 */
 127 .long   0x00000f18      /* 00A8:      DRD1A: var3 = idx3; FN=0 init=0 WS=0 RS=0 */
 128 .long   0xc4188000      /* 00AC:    LCDEXT: idx1 = var8; idx1 once var0; idx1 += inc0 */
 129 .long   0x85190312      /* 00B0:    LCD: idx2 = var10; idx2 > var12; idx2 += inc2 */
 130 .long   0x10000c00      /* 00B4:      DRD1A: var3 = var0; FN=0 MORE init=0 WS=0 RS=0 */
 131 .long   0x1000c400      /* 00B8:      DRD1A: *idx1 = var0; FN=0 MORE init=0 WS=0 RS=0 */
 132 .long   0x00008860      /* 00BC:      DRD1A: idx2 = var12; FN=0 init=0 WS=0 RS=0 */
 133 .long   0x81988000      /* 00C0:    LCD: idx1 = var3; idx1 once var0; idx1 += inc0 */
 134 .long   0x10000788      /* 00C4:      DRD1A: var1 = *idx1; FN=0 MORE init=0 WS=0 RS=0 */
 135 .long   0x60000000      /* 00C8:      DRD2A: EU0=0 EU1=0 EU2=0 EU3=0 EXT init=0 WS=0 RS=0 */
 136 .long   0x080cf04d      /* 00CC:      DRD2B1: idx0 = EU3(); EU3(var1,var13)  */
 137 .long   0x000001f8      /* 00D0(:0):    NOP */
 138
 139 .align  8
 140
 141 .globl scEthernetRecv_VarTab
 142 scEthernetRecv_VarTab:  /* Task 0 Variable Table */
 143 .long   0x00000000      /* var[0] */
 144 .long   0x00000000      /* var[1] */
 145 .long   0x00000000      /* var[2] */
 146 .long   0x00000000      /* var[3] */
 147 .long   0x00000000      /* var[4] */
 148 .long   0x00000000      /* var[5] */
 149 .long   0x00000000      /* var[6] */
 150 .long   0x00000000      /* var[7] */
 151 .long   0x00000000      /* var[8] */
 152 .long   (CONFIG_SYS_MBAR + 0x8800)      /* var[9] */
 153 .long   0x00000008      /* var[10] */
 154 .long   0x0000000c      /* var[11] */
 155 .long   0x80000000      /* var[12] */
 156 .long   0x00000000      /* var[13] */
 157 .long   0x10000000      /* var[14] */
 158 .long   0x20000000      /* var[15] */
 159 .long   0x000005e4      /* var[16] */
 160 .long   0x0000000e      /* var[17] */
 161 .long   0x000005e0      /* var[18] */
 162 .long   0x00000004      /* var[19] */
 163 .long   0x00000000      /* var[20] */
 164 .long   0x00000000      /* var[21] */
 165 .long   0x00000000      /* var[22] */
 166 .long   0x00000000      /* var[23] */
 167 .long   0x00000000      /* inc[0] */
 168 .long   0x60000000      /* inc[1] */
 169 .long   0x20000001      /* inc[2] */
 170 .long   0x80000000      /* inc[3] */
 171 .long   0x40000000      /* inc[4] */
 172 .long   0x00000000      /* inc[5] */
 173 .long   0x00000000      /* inc[6] */
 174 .long   0x00000000      /* inc[7] */
 175
 176 .align  8
 177
 178 .globl scEthernetXmit_VarTab
 179 scEthernetXmit_VarTab:  /* Task 1 Variable Table */
 180 .long   0x00000000      /* var[0] */
 181 .long   0x00000000      /* var[1] */
 182 .long   0x00000000      /* var[2] */
 183 .long   0x00000000      /* var[3] */
 184 .long   0x00000000      /* var[4] */
 185 .long   0x00000000      /* var[5] */
 186 .long   0x00000000      /* var[6] */
 187 .long   0x00000000      /* var[7] */
 188 .long   0x00000000      /* var[8] */
 189 .long   0x00000000      /* var[9] */
 190 .long   0x00000000      /* var[10] */
 191 .long   (CONFIG_SYS_MBAR + 0x8800)      /* var[11] */
 192 .long   0x00000000      /* var[12] */
 193 .long   0x80000000      /* var[13] */
 194 .long   0x10000000      /* var[14] */
 195 .long   0x08000000      /* var[15] */
 196 .long   0x20000000      /* var[16] */
 197 .long   0x0000ffff      /* var[17] */
 198 .long   0xffffffff      /* var[18] */
 199 .long   0x00000008      /* var[19] */
 200 .long   0x00000000      /* var[20] */
 201 .long   0x00000000      /* var[21] */
 202 .long   0x00000000      /* var[22] */
 203 .long   0x00000000      /* var[23] */
 204 .long   0x00000000      /* inc[0] */
 205 .long   0x60000000      /* inc[1] */
 206 .long   0x40000000      /* inc[2] */
 207 .long   0x4000ffff      /* inc[3] */
 208 .long   0xe0000001      /* inc[4] */
 209 .long   0x80000000      /* inc[5] */
 210 .long   0x00000000      /* inc[6] */
 211 .long   0x00000000      /* inc[7] */
 212
 213 .align  8
 214
 215 .globl scEthernetRecv_FDT
 216 scEthernetRecv_FDT:     /* Task 0 Function Descriptor Table */
 217 .long   0x00000000
 218 .long   0x00000000
 219 .long   0x00000000
 220 .long   0x00000000
 221 .long   0x00000000
 222 .long   0x00000000
 223 .long   0x00000000
 224 .long   0x00000000
 225 .long   0x00000000
 226 .long   0x00000000
 227 .long   0x00000000
 228 .long   0x00000000
 229 .long   0x00000000
 230 .long   0x00000000
 231 .long   0x00000000
 232 .long   0x00000000
 233 .long   0x00000000
 234 .long   0x00000000
 235 .long   0x00000000
 236 .long   0x00000000
 237 .long   0x00000000
 238 .long   0x00000000
 239 .long   0x00000000
 240 .long   0x00000000
 241 .long   0x00000000
 242 .long   0x00000000
 243 .long   0x00000000
 244 .long   0x00000000
 245 .long   0x00000000
 246 .long   0x00000000
 247 .long   0x00000000
 248 .long   0x00000000
 249 .long   0x00000000
 250 .long   0x00000000
 251 .long   0x00000000
 252 .long   0x00000000
 253 .long   0x00000000
 254 .long   0x00000000
 255 .long   0x00000000
 256 .long   0x00000000
 257 .long   0x00000000
 258 .long   0x00000000
 259 .long   0x00000000
 260 .long   0x00000000
 261 .long   0x00000000
 262 .long   0x00000000
 263 .long   0x00000000
 264 .long   0x00000000
 265 .long   0x21800000      /* and(), EU# 3 */
 266 .long   0x21400000      /* andn(), EU# 3 */
 267 .long   0x00000000
 268 .long   0x00000000
 269 .long   0x00000000
 270 .long   0x00000000
 271 .long   0x00000000
 272 .long   0x00000000
 273 .long   0x00000000
 274 .long   0x00000000
 275 .long   0x00000000
 276 .long   0x00000000
 277 .long   0x00000000
 278 .long   0x00000000
 279 .long   0x00000000
 280 .long   0x00000000
 281
 282 .align  8
 283
 284 .globl scEthernetXmit_FDT
 285 scEthernetXmit_FDT:     /* Task 1 Function Descriptor Table */
 286 .long   0x00000000
 287 .long   0x00000000
 288 .long   0x00000000
 289 .long   0x00000000
 290 .long   0x00000000
 291 .long   0x00000000
 292 .long   0x00000000
 293 .long   0x00000000
 294 .long   0x00000000
 295 .long   0x00000000
 296 .long   0x00000000
 297 .long   0x00000000
 298 .long   0x00000000
 299 .long   0x00000000
 300 .long   0x00000000
 301 .long   0x00000000
 302 .long   0x00000000
 303 .long   0x00000000
 304 .long   0x00000000
 305 .long   0x00000000
 306 .long   0x00000000
 307 .long   0x00000000
 308 .long   0x00000000
 309 .long   0x00000000
 310 .long   0x00000000
 311 .long   0x00000000
 312 .long   0x00000000
 313 .long   0x00000000
 314 .long   0x00000000
 315 .long   0x00000000
 316 .long   0x00000000
 317 .long   0x00000000
 318 .long   0x00000000
 319 .long   0x00000000
 320 .long   0x00000000
 321 .long   0x00000000
 322 .long   0x00000000
 323 .long   0x00000000
 324 .long   0x00000000
 325 .long   0x00000000
 326 .long   0x00000000
 327 .long   0x00000000
 328 .long   0x00000000
 329 .long   0x00000000
 330 .long   0x00000000
 331 .long   0x00000000
 332 .long   0x00000000
 333 .long   0x00000000
 334 .long   0x21800000      /* and(), EU# 3 */
 335 .long   0x21400000      /* andn(), EU# 3 */
 336 .long   0x00000000
 337 .long   0x00000000
 338 .long   0x00000000
 339 .long   0x00000000
 340 .long   0x00000000
 341 .long   0x00000000
 342 .long   0x00000000
 343 .long   0x00000000
 344 .long   0x00000000
 345 .long   0x00000000
 346 .long   0x00000000
 347 .long   0x00000000
 348 .long   0x00000000
 349 .long   0x00000000
 350
 351
 352 .globl scEthernetRecv_CSave
 353 scEthernetRecv_CSave:   /* Task 0 context save space */
 354 .space  128, 0x0
 355
 356
 357 .globl scEthernetXmit_CSave
 358 scEthernetXmit_CSave:   /* Task 1 context save space */
 359 .space  128, 0x0