arch/powerpc/cpu/mpc5xxx/pci_mpc5200.c

   1 /*
   2  * (C) Copyright 2000-2003
   3  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0+
   6  */
   7
   8 #include <common.h>
   9
  10 #if defined(CONFIG_PCI)
  11
  12 #include <asm/processor.h>
  13 #include <asm/io.h>
  14 #include <pci.h>
  15 #include <mpc5xxx.h>
  16
  17 /* System RAM mapped over PCI */
  18 #define CONFIG_PCI_MEMORY_BUS   CONFIG_SYS_SDRAM_BASE
  19 #define CONFIG_PCI_MEMORY_PHYS  CONFIG_SYS_SDRAM_BASE
  20 #define CONFIG_PCI_MEMORY_SIZE  (1024 * 1024 * 1024)
  21
  22 /* PCIIWCR bit fields */
  23 #define IWCR_MEM        (0 << 3)
  24 #define IWCR_IO         (1 << 3)
  25 #define IWCR_READ       (0 << 1)
  26 #define IWCR_READLINE   (1 << 1)
  27 #define IWCR_READMULT   (2 << 1)
  28 #define IWCR_EN         (1 << 0)
  29
  30 static int mpc5200_read_config_dword(struct pci_controller *hose,
  31                               pci_dev_t dev, int offset, u32* value)
  32 {
  33         *(volatile u32 *)MPC5XXX_PCI_CAR = (1 << 31) | dev | offset;
  34         eieio();
  35         udelay(10);
  36         *value = in_le32((volatile u32 *)CONFIG_PCI_IO_PHYS);
  37         eieio();
  38         *(volatile u32 *)MPC5XXX_PCI_CAR = 0;
  39         udelay(10);
  40         return 0;
  41 }
  42
  43 static int mpc5200_write_config_dword(struct pci_controller *hose,
  44                               pci_dev_t dev, int offset, u32 value)
  45 {
  46         *(volatile u32 *)MPC5XXX_PCI_CAR = (1 << 31) | dev | offset;
  47         eieio();
  48         udelay(10);
  49         out_le32((volatile u32 *)CONFIG_PCI_IO_PHYS, value);
  50         eieio();
  51         *(volatile u32 *)MPC5XXX_PCI_CAR = 0;
  52         udelay(10);
  53         return 0;
  54 }
  55
  56 void pci_mpc5xxx_init (struct pci_controller *hose)
  57 {
  58         hose->first_busno = 0;
  59         hose->last_busno = 0xff;
  60
  61         /* System space */
  62         pci_set_region(hose->regions + 0,
  63                        CONFIG_PCI_MEMORY_BUS,
  64                        CONFIG_PCI_MEMORY_PHYS,
  65                        CONFIG_PCI_MEMORY_SIZE,
  66                        PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
  67
  68         /* PCI memory space */
  69         pci_set_region(hose->regions + 1,
  70                        CONFIG_PCI_MEM_BUS,
  71                        CONFIG_PCI_MEM_PHYS,
  72                        CONFIG_PCI_MEM_SIZE,
  73                        PCI_REGION_MEM);
  74
  75         /* PCI IO space */
  76         pci_set_region(hose->regions + 2,
  77                        CONFIG_PCI_IO_BUS,
  78                        CONFIG_PCI_IO_PHYS,
  79                        CONFIG_PCI_IO_SIZE,
  80                        PCI_REGION_IO);
  81
  82         hose->region_count = 3;
  83
  84         pci_register_hose(hose);
  85
  86         /* GPIO Multiplexing - enable PCI */
  87         *(vu_long *)MPC5XXX_GPS_PORT_CONFIG &= ~(1 << 15);
  88
  89         /* Set host bridge as pci master and enable memory decoding */
  90         *(vu_long *)MPC5XXX_PCI_CMD |=
  91                 PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
  92
  93         /* Set maximum latency timer */
  94         *(vu_long *)MPC5XXX_PCI_CFG |= (0xf800);
  95
  96         /* Set cache line size */
  97         *(vu_long *)MPC5XXX_PCI_CFG = (*(vu_long *)MPC5XXX_PCI_CFG & ~0xff) |
  98                 (CONFIG_SYS_CACHELINE_SIZE / 4);
  99
 100         /* Map MBAR to PCI space */
 101         *(vu_long *)MPC5XXX_PCI_BAR0 = CONFIG_SYS_MBAR;
 102         *(vu_long *)MPC5XXX_PCI_TBATR0 = CONFIG_SYS_MBAR | 1;
 103
 104         /* Map RAM to PCI space */
 105         *(vu_long *)MPC5XXX_PCI_BAR1 = CONFIG_PCI_MEMORY_BUS | (1 << 3);
 106         *(vu_long *)MPC5XXX_PCI_TBATR1 = CONFIG_PCI_MEMORY_PHYS | 1;
 107
 108         /* Park XLB on PCI */
 109         *(vu_long *)(MPC5XXX_XLBARB + 0x40) &= ~((7 << 8) | (3 << 5));
 110         *(vu_long *)(MPC5XXX_XLBARB + 0x40) |= (3 << 8) | (3 << 5);
 111
 112         /* Disable interrupts from PCI controller */
 113         *(vu_long *)MPC5XXX_PCI_GSCR &= ~(7 << 12);
 114         *(vu_long *)MPC5XXX_PCI_ICR  &= ~(7 << 24);
 115
 116         /* Set PCI retry counter to 0 = infinite retry. */
 117         /* The default of 255 is too short for slow devices. */
 118         *(vu_long *)MPC5XXX_PCI_ICR &= 0xFFFFFF00;
 119
 120         /* Disable initiator windows */
 121         *(vu_long *)MPC5XXX_PCI_IWCR = 0;
 122
 123         /* Map PCI memory to physical space */
 124         *(vu_long *)MPC5XXX_PCI_IW0BTAR = CONFIG_PCI_MEM_PHYS |
 125                 (((CONFIG_PCI_MEM_SIZE - 1) >> 8) & 0x00ff0000) |
 126                 (CONFIG_PCI_MEM_BUS >> 16);
 127         *(vu_long *)MPC5XXX_PCI_IWCR |= (IWCR_MEM | IWCR_READ | IWCR_EN) << 24;
 128
 129         /* Map PCI I/O to physical space */
 130         *(vu_long *)MPC5XXX_PCI_IW1BTAR = CONFIG_PCI_IO_PHYS |
 131                 (((CONFIG_PCI_IO_SIZE - 1) >> 8) & 0x00ff0000) |
 132                 (CONFIG_PCI_IO_BUS >> 16);
 133         *(vu_long *)MPC5XXX_PCI_IWCR |= (IWCR_IO | IWCR_READ | IWCR_EN) << 16;
 134
 135         /* Reset the PCI bus */
 136         *(vu_long *)MPC5XXX_PCI_GSCR |= 1;
 137         udelay(1000);
 138         *(vu_long *)MPC5XXX_PCI_GSCR &= ~1;
 139         udelay(1000);
 140
 141         pci_set_ops(hose,
 142                 pci_hose_read_config_byte_via_dword,
 143                 pci_hose_read_config_word_via_dword,
 144                 mpc5200_read_config_dword,
 145                 pci_hose_write_config_byte_via_dword,
 146                 pci_hose_write_config_word_via_dword,
 147                 mpc5200_write_config_dword);
 148
 149         udelay(1000);
 150
 151 #ifdef CONFIG_PCI_SCAN_SHOW
 152         printf("PCI:   Bus Dev VenId DevId Class Int\n");
 153 #endif
 154
 155         hose->last_busno = pci_hose_scan(hose);
 156 }
 157 #endif /* CONFIG_PCI */