arch/powerpc/cpu/mpc824x/cpu_init.c

   1 /*
   2  * (C) Copyright 2000
   3  * Rob Taylor. Flying Pig Systems. robt@flyingpig.com.
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0+
   6  */
   7
   8 #include <common.h>
   9 #include <asm/processor.h>
  10 #include <mpc824x.h>
  11
  12 #ifndef CONFIG_SYS_BANK0_ROW
  13 #define CONFIG_SYS_BANK0_ROW 0
  14 #endif
  15 #ifndef CONFIG_SYS_BANK1_ROW
  16 #define CONFIG_SYS_BANK1_ROW 0
  17 #endif
  18 #ifndef CONFIG_SYS_BANK2_ROW
  19 #define CONFIG_SYS_BANK2_ROW 0
  20 #endif
  21 #ifndef CONFIG_SYS_BANK3_ROW
  22 #define CONFIG_SYS_BANK3_ROW 0
  23 #endif
  24 #ifndef CONFIG_SYS_BANK4_ROW
  25 #define CONFIG_SYS_BANK4_ROW 0
  26 #endif
  27 #ifndef CONFIG_SYS_BANK5_ROW
  28 #define CONFIG_SYS_BANK5_ROW 0
  29 #endif
  30 #ifndef CONFIG_SYS_BANK6_ROW
  31 #define CONFIG_SYS_BANK6_ROW 0
  32 #endif
  33 #ifndef CONFIG_SYS_BANK7_ROW
  34 #define CONFIG_SYS_BANK7_ROW 0
  35 #endif
  36 #ifndef CONFIG_SYS_DBUS_SIZE2
  37 #define CONFIG_SYS_DBUS_SIZE2 0
  38 #endif
  39
  40 /*
  41  * Breath some life into the CPU...
  42  *
  43  * Set up the memory map,
  44  * initialize a bunch of registers,
  45  */
  46 void
  47 cpu_init_f (void)
  48 {
  49     register unsigned long val;
  50     CONFIG_WRITE_HALFWORD(PCICR, 0x06); /* Bus Master, respond to PCI memory space acesses*/
  51 /*    CONFIG_WRITE_HALFWORD(PCISR, 0xffff); */ /*reset PCISR*/
  52
  53 #if defined(CONFIG_MUSENKI)
  54 /* Why is this here, you ask?  Try, just try setting 0x8000
  55  * in PCIACR with CONFIG_WRITE_HALFWORD()
  56  * this one was a stumper, and we are annoyed
  57  */
  58
  59 #define M_CONFIG_WRITE_HALFWORD( addr, data ) \
  60         __asm__ __volatile__("          \
  61                 stw  %2,0(%0)\n         \
  62                 sync\n                  \
  63                 sth  %3,2(%1)\n         \
  64                 sync\n                  \
  65                 "                       \
  66                 : /* no output */       \
  67                 : "r" (CONFIG_ADDR), "r" (CONFIG_DATA),                 \
  68                 "r" (PCISWAP(addr & ~3)), "r" (PCISWAP(data << 16))     \
  69         );
  70
  71         M_CONFIG_WRITE_HALFWORD(PCIACR, 0x8000);
  72 #endif
  73
  74         CONFIG_WRITE_BYTE(PCLSR, 0x8);  /* set PCI cache line size */
  75         CONFIG_WRITE_BYTE (PLTR, 0x40); /* set PCI latency timer */
  76         /*
  77         * Note that although this bit is cleared after a hard reset, it
  78         * must be explicitly set and then cleared by software during
  79         * initialization in order to guarantee correct operation of the
  80         * DLL and the SDRAM_CLK[0:3] signals (if they are used).
  81         */
  82         CONFIG_READ_BYTE (AMBOR, val);
  83         CONFIG_WRITE_BYTE(AMBOR, val & 0xDF);
  84         CONFIG_WRITE_BYTE(AMBOR, val | 0x20);
  85         CONFIG_WRITE_BYTE(AMBOR, val & 0xDF);
  86 #ifdef CONFIG_MPC8245
  87         /* silicon bug 28 MPC8245 */
  88         CONFIG_READ_BYTE(AMBOR,val);
  89         CONFIG_WRITE_BYTE(AMBOR,val|0x1);
  90
  91 #if 0
  92         /*
  93          * The following bug only affects older (XPC8245) processors.
  94          * DMA transfers initiated by external devices get corrupted due
  95          * to a hardware scheduling problem.
  96          *
  97          * The effect is:
  98          * when transferring X words, the first 32 words are transferred
  99          * OK, the next 3 x 32 words are 'old' data (from previous DMA)
 100          * while the rest of the X words is xferred fine.
 101          *
 102          * Disabling 3 of the 4 32 word hardware buffers solves the problem
 103          * with no significant performance loss.
 104          */
 105
 106         CONFIG_READ_BYTE(PCMBCR,val);
 107         /* in order not to corrupt data which is being read over the PCI bus
 108         * with the PPC as slave, we need to reduce the number of PCMRBs to 1,
 109         * 4.11 in the  processor user manual
 110         * */
 111
 112 #if 1
 113         CONFIG_WRITE_BYTE(PCMBCR,(val|0xC0)); /* 1 PCMRB */
 114 #else
 115         CONFIG_WRITE_BYTE(PCMBCR,(val|0x80)); /* 2 PCMRBs */
 116         CONFIG_WRITE_BYTE(PCMBCR,(val|0x40)); /* 3 PCMRBs */
 117         /* default, 4 PCMRBs are used */
 118 #endif
 119 #endif
 120 #endif
 121
 122         CONFIG_READ_WORD(PICR1, val);
 123 #if defined(CONFIG_MPC8240)
 124         CONFIG_WRITE_WORD( PICR1,
 125                 (val & (PICR1_ADDRESS_MAP | PICR1_RCS0)) |
 126                        PIRC1_MSK | PICR1_PROC_TYPE_603E |
 127                        PICR1_FLASH_WR_EN | PICR1_MCP_EN |
 128                        PICR1_CF_DPARK | PICR1_EN_PCS |
 129                        PICR1_CF_APARK );
 130 #elif defined(CONFIG_MPC8245)
 131         CONFIG_WRITE_WORD( PICR1,
 132                 (val & (PICR1_RCS0)) |
 133                        PICR1_PROC_TYPE_603E |
 134                        PICR1_FLASH_WR_EN | PICR1_MCP_EN |
 135                        PICR1_CF_DPARK | PICR1_NO_BUSW_CK |
 136                        PICR1_DEC| PICR1_CF_APARK | 0x10); /* 8245 UM says bit 4 must be set */
 137 #else
 138 #error Specific type of MPC824x must be defined (i.e. CONFIG_MPC8240)
 139 #endif
 140
 141         CONFIG_READ_WORD(PICR2, val);
 142         val= val & ~ (PICR2_CF_SNOOP_WS_MASK | PICR2_CF_APHASE_WS_MASK); /*mask off waitstate bits*/
 143         val |= PICR2_CF_SNOOP_WS_1WS | PICR2_CF_APHASE_WS_1WS; /*1 wait state*/
 144         CONFIG_WRITE_WORD(PICR2, val);
 145
 146         CONFIG_WRITE_WORD(EUMBBAR, CONFIG_SYS_EUMB_ADDR);
 147 #ifndef CONFIG_SYS_RAMBOOT
 148         CONFIG_WRITE_WORD(MCCR1, (CONFIG_SYS_ROMNAL << MCCR1_ROMNAL_SHIFT) |
 149                                  (CONFIG_SYS_BANK0_ROW) |
 150                                  (CONFIG_SYS_BANK1_ROW << MCCR1_BANK1ROW_SHIFT) |
 151                                  (CONFIG_SYS_BANK2_ROW << MCCR1_BANK2ROW_SHIFT) |
 152                                  (CONFIG_SYS_BANK3_ROW << MCCR1_BANK3ROW_SHIFT) |
 153                                  (CONFIG_SYS_BANK4_ROW << MCCR1_BANK4ROW_SHIFT) |
 154                                  (CONFIG_SYS_BANK5_ROW << MCCR1_BANK5ROW_SHIFT) |
 155                                  (CONFIG_SYS_BANK6_ROW << MCCR1_BANK6ROW_SHIFT) |
 156                                  (CONFIG_SYS_BANK7_ROW << MCCR1_BANK7ROW_SHIFT) |
 157                                  (CONFIG_SYS_ROMFAL << MCCR1_ROMFAL_SHIFT));
 158 #endif
 159
 160 #if defined(CONFIG_SYS_ASRISE) && defined(CONFIG_SYS_ASFALL)
 161         CONFIG_WRITE_WORD(MCCR2, CONFIG_SYS_REFINT << MCCR2_REFINT_SHIFT |
 162                                  CONFIG_SYS_ASRISE << MCCR2_ASRISE_SHIFT |
 163                                  CONFIG_SYS_ASFALL << MCCR2_ASFALL_SHIFT);
 164 #else
 165         CONFIG_WRITE_WORD(MCCR2, CONFIG_SYS_REFINT << MCCR2_REFINT_SHIFT);
 166 #endif
 167
 168 #if defined(CONFIG_MPC8240)
 169         CONFIG_WRITE_WORD(MCCR3,
 170                 (((CONFIG_SYS_BSTOPRE & 0x003c) >> 2) << MCCR3_BSTOPRE2TO5_SHIFT) |
 171                 (CONFIG_SYS_REFREC << MCCR3_REFREC_SHIFT) |
 172                 (CONFIG_SYS_RDLAT  << MCCR3_RDLAT_SHIFT));
 173 #elif defined(CONFIG_MPC8245)
 174         CONFIG_WRITE_WORD(MCCR3,
 175                 (((CONFIG_SYS_BSTOPRE & 0x003c) >> 2) << MCCR3_BSTOPRE2TO5_SHIFT) |
 176                 (CONFIG_SYS_REFREC << MCCR3_REFREC_SHIFT));
 177 #else
 178 #error Specific type of MPC824x must be defined (i.e. CONFIG_MPC8240)
 179 #endif
 180
 181 /* this is gross.  We think these should all be the same, and various boards
 182  *  should define CONFIG_SYS_ACTORW to 0 if they don't want to set it, or even, if
 183  *  its not set, we define it to zero in this file
 184  */
 185 #if defined(CONFIG_CU824)
 186         CONFIG_WRITE_WORD(MCCR4,
 187         (CONFIG_SYS_PRETOACT << MCCR4_PRETOACT_SHIFT) |
 188         (CONFIG_SYS_ACTTOPRE << MCCR4_ACTTOPRE_SHIFT) |
 189         MCCR4_BIT21 |
 190         (CONFIG_SYS_REGISTERD_TYPE_BUFFER ? MCCR4_REGISTERED: 0) |
 191         ((CONFIG_SYS_BSTOPRE & 0x0003) <<MCCR4_BSTOPRE0TO1_SHIFT ) |
 192         (((CONFIG_SYS_SDMODE_CAS_LAT <<4) | (CONFIG_SYS_SDMODE_WRAP <<3) |
 193                   CONFIG_SYS_SDMODE_BURSTLEN) << MCCR4_SDMODE_SHIFT) |
 194         (CONFIG_SYS_ACTORW << MCCR4_ACTTORW_SHIFT) |
 195         (((CONFIG_SYS_BSTOPRE & 0x03c0) >> 6) << MCCR4_BSTOPRE6TO9_SHIFT));
 196 #elif defined(CONFIG_MPC8240)
 197         CONFIG_WRITE_WORD(MCCR4,
 198         (CONFIG_SYS_PRETOACT << MCCR4_PRETOACT_SHIFT) |
 199         (CONFIG_SYS_ACTTOPRE << MCCR4_ACTTOPRE_SHIFT) |
 200         MCCR4_BIT21 |
 201         (CONFIG_SYS_REGISTERD_TYPE_BUFFER ? MCCR4_REGISTERED: 0) |
 202         ((CONFIG_SYS_BSTOPRE & 0x0003) <<MCCR4_BSTOPRE0TO1_SHIFT ) |
 203         (((CONFIG_SYS_SDMODE_CAS_LAT <<4) | (CONFIG_SYS_SDMODE_WRAP <<3) |
 204                   (CONFIG_SYS_SDMODE_BURSTLEN)) <<MCCR4_SDMODE_SHIFT) |
 205         (((CONFIG_SYS_BSTOPRE & 0x03c0) >> 6) <<MCCR4_BSTOPRE6TO9_SHIFT ));
 206 #elif defined(CONFIG_MPC8245)
 207         CONFIG_READ_WORD(MCCR1, val);
 208         val &= MCCR1_DBUS_SIZE0;    /* test for 64-bit mem bus */
 209
 210         CONFIG_WRITE_WORD(MCCR4,
 211                 (CONFIG_SYS_PRETOACT << MCCR4_PRETOACT_SHIFT) |
 212                 (CONFIG_SYS_ACTTOPRE << MCCR4_ACTTOPRE_SHIFT) |
 213                 (CONFIG_SYS_EXTROM ? MCCR4_EXTROM : 0) |
 214                 (CONFIG_SYS_REGDIMM ? MCCR4_REGDIMM : 0) |
 215                 (CONFIG_SYS_REGISTERD_TYPE_BUFFER ? MCCR4_REGISTERED: 0) |
 216                 ((CONFIG_SYS_BSTOPRE & 0x0003) <<MCCR4_BSTOPRE0TO1_SHIFT ) |
 217                 (CONFIG_SYS_DBUS_SIZE2 << MCCR4_DBUS_SIZE2_SHIFT) |
 218                 (((CONFIG_SYS_SDMODE_CAS_LAT <<4) | (CONFIG_SYS_SDMODE_WRAP <<3) |
 219                       (val ? 2 : 3)) << MCCR4_SDMODE_SHIFT)  |
 220                 (CONFIG_SYS_ACTORW << MCCR4_ACTTORW_SHIFT) |
 221                 (((CONFIG_SYS_BSTOPRE & 0x03c0) >> 6) <<MCCR4_BSTOPRE6TO9_SHIFT ));
 222 #else
 223 #error Specific type of MPC824x must be defined (i.e. CONFIG_MPC8240)
 224 #endif
 225
 226         CONFIG_WRITE_WORD(MSAR1,
 227                 ( (CONFIG_SYS_BANK0_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) |
 228                 (((CONFIG_SYS_BANK1_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 8) |
 229                 (((CONFIG_SYS_BANK2_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 16) |
 230                 (((CONFIG_SYS_BANK3_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 24));
 231         CONFIG_WRITE_WORD(EMSAR1,
 232                 ( (CONFIG_SYS_BANK0_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) |
 233                 (((CONFIG_SYS_BANK1_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 8) |
 234                 (((CONFIG_SYS_BANK2_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 16) |
 235                 (((CONFIG_SYS_BANK3_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 24));
 236         CONFIG_WRITE_WORD(MSAR2,
 237                 ( (CONFIG_SYS_BANK4_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) |
 238                 (((CONFIG_SYS_BANK5_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 8) |
 239                 (((CONFIG_SYS_BANK6_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 16) |
 240                 (((CONFIG_SYS_BANK7_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 24));
 241         CONFIG_WRITE_WORD(EMSAR2,
 242                 ( (CONFIG_SYS_BANK4_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) |
 243                 (((CONFIG_SYS_BANK5_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 8) |
 244                 (((CONFIG_SYS_BANK6_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 16) |
 245                 (((CONFIG_SYS_BANK7_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 24));
 246         CONFIG_WRITE_WORD(MEAR1,
 247                 ( (CONFIG_SYS_BANK0_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) |
 248                 (((CONFIG_SYS_BANK1_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 8) |
 249                 (((CONFIG_SYS_BANK2_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 16) |
 250                 (((CONFIG_SYS_BANK3_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 24));
 251         CONFIG_WRITE_WORD(EMEAR1,
 252                 ( (CONFIG_SYS_BANK0_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) |
 253                 (((CONFIG_SYS_BANK1_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 8) |
 254                 (((CONFIG_SYS_BANK2_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 16) |
 255                 (((CONFIG_SYS_BANK3_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 24));
 256         CONFIG_WRITE_WORD(MEAR2,
 257                 ( (CONFIG_SYS_BANK4_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) |
 258                 (((CONFIG_SYS_BANK5_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 8) |
 259                 (((CONFIG_SYS_BANK6_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 16) |
 260                 (((CONFIG_SYS_BANK7_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 24));
 261         CONFIG_WRITE_WORD(EMEAR2,
 262                 ( (CONFIG_SYS_BANK4_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) |
 263                 (((CONFIG_SYS_BANK5_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 8) |
 264                 (((CONFIG_SYS_BANK6_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 16) |
 265                 (((CONFIG_SYS_BANK7_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 24));
 266
 267         CONFIG_WRITE_BYTE(ODCR, CONFIG_SYS_ODCR);
 268 #ifdef CONFIG_SYS_DLL_MAX_DELAY
 269         CONFIG_WRITE_BYTE(MIOCR1, CONFIG_SYS_DLL_MAX_DELAY);    /* needed to make DLL lock */
 270 #endif
 271 #if defined(CONFIG_SYS_DLL_EXTEND) && defined(CONFIG_SYS_PCI_HOLD_DEL)
 272         CONFIG_WRITE_BYTE(PMCR2, CONFIG_SYS_DLL_EXTEND | CONFIG_SYS_PCI_HOLD_DEL);
 273 #endif
 274 #if defined(MIOCR2) && defined(CONFIG_SYS_SDRAM_DSCD)
 275         CONFIG_WRITE_BYTE(MIOCR2, CONFIG_SYS_SDRAM_DSCD);       /* change memory input */
 276 #endif /* setup & hold time */
 277
 278         CONFIG_WRITE_BYTE(MBER,
 279                  CONFIG_SYS_BANK0_ENABLE |
 280                 (CONFIG_SYS_BANK1_ENABLE << 1) |
 281                 (CONFIG_SYS_BANK2_ENABLE << 2) |
 282                 (CONFIG_SYS_BANK3_ENABLE << 3) |
 283                 (CONFIG_SYS_BANK4_ENABLE << 4) |
 284                 (CONFIG_SYS_BANK5_ENABLE << 5) |
 285                 (CONFIG_SYS_BANK6_ENABLE << 6) |
 286                 (CONFIG_SYS_BANK7_ENABLE << 7));
 287
 288 #ifdef CONFIG_SYS_PGMAX
 289         CONFIG_WRITE_BYTE(MPMR, CONFIG_SYS_PGMAX);
 290 #endif
 291
 292         /* ! Wait 200us before initialize other registers */
 293         /*FIXME: write a decent udelay wait */
 294         __asm__ __volatile__(
 295                 " mtctr %0 \n \
 296                 0: bdnz  0b\n"
 297                 :
 298                 : "r" (0x10000));
 299
 300         CONFIG_READ_WORD(MCCR1, val);
 301         CONFIG_WRITE_WORD(MCCR1, val | MCCR1_MEMGO); /* set memory access going */
 302         __asm__ __volatile__("eieio");
 303 }
 304
 305 /*
 306  * initialize higher level parts of CPU like time base and timers
 307  */
 308 int cpu_init_r (void)
 309 {
 310         return (0);
 311 }