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[people/ms/u-boot.git] / arch / powerpc / cpu / mpc8260 / ether_fcc.c
1 /*
2 * MPC8260 FCC Fast Ethernet
3 *
4 * Copyright (c) 2000 MontaVista Software, Inc. Dan Malek (dmalek@jlc.net)
5 *
6 * (C) Copyright 2000 Sysgo Real-Time Solutions, GmbH <www.elinos.com>
7 * Marius Groeger <mgroeger@sysgo.de>
8 *
9 * SPDX-License-Identifier: GPL-2.0+
10 */
11
12 /*
13 * MPC8260 FCC Fast Ethernet
14 * Basic ET HW initialization and packet RX/TX routines
15 *
16 * This code will not perform the IO port configuration. This should be
17 * done in the iop_conf_t structure specific for the board.
18 *
19 * TODO:
20 * add a PHY driver to do the negotiation
21 * reflect negotiation results in FPSMR
22 * look for ways to configure the board specific stuff elsewhere, eg.
23 * config_xxx.h or the board directory
24 */
25
26 #include <common.h>
27 #include <malloc.h>
28 #include <asm/cpm_8260.h>
29 #include <mpc8260.h>
30 #include <command.h>
31 #include <config.h>
32 #include <net.h>
33
34 #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
35 #include <miiphy.h>
36 #endif
37
38 DECLARE_GLOBAL_DATA_PTR;
39
40 #if defined(CONFIG_ETHER_ON_FCC) && defined(CONFIG_CMD_NET)
41
42 static struct ether_fcc_info_s
43 {
44 int ether_index;
45 int proff_enet;
46 ulong cpm_cr_enet_sblock;
47 ulong cpm_cr_enet_page;
48 ulong cmxfcr_mask;
49 ulong cmxfcr_value;
50 }
51 ether_fcc_info[] =
52 {
53 #ifdef CONFIG_ETHER_ON_FCC1
54 {
55 0,
56 PROFF_FCC1,
57 CPM_CR_FCC1_SBLOCK,
58 CPM_CR_FCC1_PAGE,
59 CONFIG_SYS_CMXFCR_MASK1,
60 CONFIG_SYS_CMXFCR_VALUE1
61 },
62 #endif
63
64 #ifdef CONFIG_ETHER_ON_FCC2
65 {
66 1,
67 PROFF_FCC2,
68 CPM_CR_FCC2_SBLOCK,
69 CPM_CR_FCC2_PAGE,
70 CONFIG_SYS_CMXFCR_MASK2,
71 CONFIG_SYS_CMXFCR_VALUE2
72 },
73 #endif
74
75 #ifdef CONFIG_ETHER_ON_FCC3
76 {
77 2,
78 PROFF_FCC3,
79 CPM_CR_FCC3_SBLOCK,
80 CPM_CR_FCC3_PAGE,
81 CONFIG_SYS_CMXFCR_MASK3,
82 CONFIG_SYS_CMXFCR_VALUE3
83 },
84 #endif
85 };
86
87 /*---------------------------------------------------------------------*/
88
89 /* Maximum input DMA size. Must be a should(?) be a multiple of 4. */
90 #define PKT_MAXDMA_SIZE 1520
91
92 /* The FCC stores dest/src/type, data, and checksum for receive packets. */
93 #define PKT_MAXBUF_SIZE 1518
94 #define PKT_MINBUF_SIZE 64
95
96 /* Maximum input buffer size. Must be a multiple of 32. */
97 #define PKT_MAXBLR_SIZE 1536
98
99 #define TOUT_LOOP 1000000
100
101 #define TX_BUF_CNT 2
102 #ifdef __GNUC__
103 static char txbuf[TX_BUF_CNT][PKT_MAXBLR_SIZE] __attribute__ ((aligned(8)));
104 #else
105 #error "txbuf must be 64-bit aligned"
106 #endif
107
108 static uint rxIdx; /* index of the current RX buffer */
109 static uint txIdx; /* index of the current TX buffer */
110
111 /*
112 * FCC Ethernet Tx and Rx buffer descriptors.
113 * Provide for Double Buffering
114 * Note: PKTBUFSRX is defined in net.h
115 */
116
117 typedef volatile struct rtxbd {
118 cbd_t rxbd[PKTBUFSRX];
119 cbd_t txbd[TX_BUF_CNT];
120 } RTXBD;
121
122 /* Good news: the FCC supports external BDs! */
123 #ifdef __GNUC__
124 static RTXBD rtx __attribute__ ((aligned(8)));
125 #else
126 #error "rtx must be 64-bit aligned"
127 #endif
128
129 static int fec_send(struct eth_device *dev, void *packet, int length)
130 {
131 int i;
132 int result = 0;
133
134 if (length <= 0) {
135 printf("fec: bad packet size: %d\n", length);
136 goto out;
137 }
138
139 for(i=0; rtx.txbd[txIdx].cbd_sc & BD_ENET_TX_READY; i++) {
140 if (i >= TOUT_LOOP) {
141 puts ("fec: tx buffer not ready\n");
142 goto out;
143 }
144 }
145
146 rtx.txbd[txIdx].cbd_bufaddr = (uint)packet;
147 rtx.txbd[txIdx].cbd_datlen = length;
148 rtx.txbd[txIdx].cbd_sc |= (BD_ENET_TX_READY | BD_ENET_TX_LAST |
149 BD_ENET_TX_WRAP);
150
151 for(i=0; rtx.txbd[txIdx].cbd_sc & BD_ENET_TX_READY; i++) {
152 if (i >= TOUT_LOOP) {
153 puts ("fec: tx error\n");
154 goto out;
155 }
156 }
157
158 #ifdef ET_DEBUG
159 printf("cycles: %d status: %04x\n", i, rtx.txbd[txIdx].cbd_sc);
160 #endif
161
162 /* return only status bits */
163 result = rtx.txbd[txIdx].cbd_sc & BD_ENET_TX_STATS;
164
165 out:
166 return result;
167 }
168
169 static int fec_recv(struct eth_device* dev)
170 {
171 int length;
172
173 for (;;)
174 {
175 if (rtx.rxbd[rxIdx].cbd_sc & BD_ENET_RX_EMPTY) {
176 length = -1;
177 break; /* nothing received - leave for() loop */
178 }
179 length = rtx.rxbd[rxIdx].cbd_datlen;
180
181 if (rtx.rxbd[rxIdx].cbd_sc & 0x003f) {
182 printf("fec: rx error %04x\n", rtx.rxbd[rxIdx].cbd_sc);
183 }
184 else {
185 /* Pass the packet up to the protocol layers. */
186 NetReceive(NetRxPackets[rxIdx], length - 4);
187 }
188
189
190 /* Give the buffer back to the FCC. */
191 rtx.rxbd[rxIdx].cbd_datlen = 0;
192
193 /* wrap around buffer index when necessary */
194 if ((rxIdx + 1) >= PKTBUFSRX) {
195 rtx.rxbd[PKTBUFSRX - 1].cbd_sc = (BD_ENET_RX_WRAP | BD_ENET_RX_EMPTY);
196 rxIdx = 0;
197 }
198 else {
199 rtx.rxbd[rxIdx].cbd_sc = BD_ENET_RX_EMPTY;
200 rxIdx++;
201 }
202 }
203 return length;
204 }
205
206
207 static int fec_init(struct eth_device* dev, bd_t *bis)
208 {
209 struct ether_fcc_info_s * info = dev->priv;
210 int i;
211 volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
212 volatile cpm8260_t *cp = &(immr->im_cpm);
213 fcc_enet_t *pram_ptr;
214 unsigned long mem_addr;
215
216 #if 0
217 mii_discover_phy();
218 #endif
219
220 /* 28.9 - (1-2): ioports have been set up already */
221
222 /* 28.9 - (3): connect FCC's tx and rx clocks */
223 immr->im_cpmux.cmx_uar = 0;
224 immr->im_cpmux.cmx_fcr = (immr->im_cpmux.cmx_fcr & ~info->cmxfcr_mask) |
225 info->cmxfcr_value;
226
227 /* 28.9 - (4): GFMR: disable tx/rx, CCITT CRC, Mode Ethernet */
228 immr->im_fcc[info->ether_index].fcc_gfmr =
229 FCC_GFMR_MODE_ENET | FCC_GFMR_TCRC_32;
230
231 /* 28.9 - (5): FPSMR: enable full duplex, select CCITT CRC for Ethernet */
232 immr->im_fcc[info->ether_index].fcc_fpsmr = CONFIG_SYS_FCC_PSMR | FCC_PSMR_ENCRC;
233
234 /* 28.9 - (6): FDSR: Ethernet Syn */
235 immr->im_fcc[info->ether_index].fcc_fdsr = 0xD555;
236
237 /* reset indeces to current rx/tx bd (see eth_send()/eth_rx()) */
238 rxIdx = 0;
239 txIdx = 0;
240
241 /* Setup Receiver Buffer Descriptors */
242 for (i = 0; i < PKTBUFSRX; i++)
243 {
244 rtx.rxbd[i].cbd_sc = BD_ENET_RX_EMPTY;
245 rtx.rxbd[i].cbd_datlen = 0;
246 rtx.rxbd[i].cbd_bufaddr = (uint)NetRxPackets[i];
247 }
248 rtx.rxbd[PKTBUFSRX - 1].cbd_sc |= BD_ENET_RX_WRAP;
249
250 /* Setup Ethernet Transmitter Buffer Descriptors */
251 for (i = 0; i < TX_BUF_CNT; i++)
252 {
253 rtx.txbd[i].cbd_sc = (BD_ENET_TX_PAD | BD_ENET_TX_LAST | BD_ENET_TX_TC);
254 rtx.txbd[i].cbd_datlen = 0;
255 rtx.txbd[i].cbd_bufaddr = (uint)&txbuf[i][0];
256 }
257 rtx.txbd[TX_BUF_CNT - 1].cbd_sc |= BD_ENET_TX_WRAP;
258
259 /* 28.9 - (7): initialise parameter ram */
260 pram_ptr = (fcc_enet_t *)&(immr->im_dprambase[info->proff_enet]);
261
262 /* clear whole structure to make sure all reserved fields are zero */
263 memset((void*)pram_ptr, 0, sizeof(fcc_enet_t));
264
265 /*
266 * common Parameter RAM area
267 *
268 * Allocate space in the reserved FCC area of DPRAM for the
269 * internal buffers. No one uses this space (yet), so we
270 * can do this. Later, we will add resource management for
271 * this area.
272 */
273 mem_addr = CPM_FCC_SPECIAL_BASE + ((info->ether_index) * 64);
274 pram_ptr->fen_genfcc.fcc_riptr = mem_addr;
275 pram_ptr->fen_genfcc.fcc_tiptr = mem_addr+32;
276 /*
277 * Set maximum bytes per receive buffer.
278 * It must be a multiple of 32.
279 */
280 pram_ptr->fen_genfcc.fcc_mrblr = PKT_MAXBLR_SIZE;
281 pram_ptr->fen_genfcc.fcc_rstate = (CPMFCR_GBL | CPMFCR_EB |
282 CONFIG_SYS_CPMFCR_RAMTYPE) << 24;
283 pram_ptr->fen_genfcc.fcc_rbase = (unsigned int)(&rtx.rxbd[rxIdx]);
284 pram_ptr->fen_genfcc.fcc_tstate = (CPMFCR_GBL | CPMFCR_EB |
285 CONFIG_SYS_CPMFCR_RAMTYPE) << 24;
286 pram_ptr->fen_genfcc.fcc_tbase = (unsigned int)(&rtx.txbd[txIdx]);
287
288 /* protocol-specific area */
289 pram_ptr->fen_cmask = 0xdebb20e3; /* CRC mask */
290 pram_ptr->fen_cpres = 0xffffffff; /* CRC preset */
291 pram_ptr->fen_retlim = 15; /* Retry limit threshold */
292 pram_ptr->fen_mflr = PKT_MAXBUF_SIZE; /* maximum frame length register */
293 /*
294 * Set Ethernet station address.
295 *
296 * This is supplied in the board information structure, so we
297 * copy that into the controller.
298 * So, far we have only been given one Ethernet address. We make
299 * it unique by setting a few bits in the upper byte of the
300 * non-static part of the address.
301 */
302 #define ea eth_get_ethaddr()
303 pram_ptr->fen_paddrh = (ea[5] << 8) + ea[4];
304 pram_ptr->fen_paddrm = (ea[3] << 8) + ea[2];
305 pram_ptr->fen_paddrl = (ea[1] << 8) + ea[0];
306 #undef ea
307 pram_ptr->fen_minflr = PKT_MINBUF_SIZE; /* minimum frame length register */
308 /* pad pointer. use tiptr since we don't need a specific padding char */
309 pram_ptr->fen_padptr = pram_ptr->fen_genfcc.fcc_tiptr;
310 pram_ptr->fen_maxd1 = PKT_MAXDMA_SIZE; /* maximum DMA1 length */
311 pram_ptr->fen_maxd2 = PKT_MAXDMA_SIZE; /* maximum DMA2 length */
312 pram_ptr->fen_rfthr = 1;
313 pram_ptr->fen_rfcnt = 1;
314 #if 0
315 printf("pram_ptr->fen_genfcc.fcc_rbase %08lx\n",
316 pram_ptr->fen_genfcc.fcc_rbase);
317 printf("pram_ptr->fen_genfcc.fcc_tbase %08lx\n",
318 pram_ptr->fen_genfcc.fcc_tbase);
319 #endif
320
321 /* 28.9 - (8): clear out events in FCCE */
322 immr->im_fcc[info->ether_index].fcc_fcce = ~0x0;
323
324 /* 28.9 - (9): FCCM: mask all events */
325 immr->im_fcc[info->ether_index].fcc_fccm = 0;
326
327 /* 28.9 - (10-12): we don't use ethernet interrupts */
328
329 /* 28.9 - (13)
330 *
331 * Let's re-initialize the channel now. We have to do it later
332 * than the manual describes because we have just now finished
333 * the BD initialization.
334 */
335 cp->cp_cpcr = mk_cr_cmd(info->cpm_cr_enet_page,
336 info->cpm_cr_enet_sblock,
337 0x0c,
338 CPM_CR_INIT_TRX) | CPM_CR_FLG;
339 do {
340 __asm__ __volatile__ ("eieio");
341 } while (cp->cp_cpcr & CPM_CR_FLG);
342
343 /* 28.9 - (14): enable tx/rx in gfmr */
344 immr->im_fcc[info->ether_index].fcc_gfmr |= FCC_GFMR_ENT | FCC_GFMR_ENR;
345
346 return 1;
347 }
348
349 static void fec_halt(struct eth_device* dev)
350 {
351 struct ether_fcc_info_s * info = dev->priv;
352 volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
353
354 /* write GFMR: disable tx/rx */
355 immr->im_fcc[info->ether_index].fcc_gfmr &=
356 ~(FCC_GFMR_ENT | FCC_GFMR_ENR);
357 }
358
359 int fec_initialize(bd_t *bis)
360 {
361 struct eth_device* dev;
362 int i;
363
364 for (i = 0; i < sizeof(ether_fcc_info) / sizeof(ether_fcc_info[0]); i++)
365 {
366 dev = (struct eth_device*) malloc(sizeof *dev);
367 memset(dev, 0, sizeof *dev);
368
369 sprintf(dev->name, "FCC%d",
370 ether_fcc_info[i].ether_index + 1);
371 dev->priv = &ether_fcc_info[i];
372 dev->init = fec_init;
373 dev->halt = fec_halt;
374 dev->send = fec_send;
375 dev->recv = fec_recv;
376
377 eth_register(dev);
378
379 #if (defined(CONFIG_MII) || defined(CONFIG_CMD_MII)) \
380 && defined(CONFIG_BITBANGMII)
381 miiphy_register(dev->name,
382 bb_miiphy_read, bb_miiphy_write);
383 #endif
384 }
385
386 return 1;
387 }
388
389 #ifdef CONFIG_ETHER_LOOPBACK_TEST
390
391 #define ELBT_BUFSZ 1024 /* must be multiple of 32 */
392
393 #define ELBT_CRCSZ 4
394
395 #define ELBT_NRXBD 4 /* must be at least 2 */
396 #define ELBT_NTXBD 4
397
398 #define ELBT_MAXRXERR 32
399 #define ELBT_MAXTXERR 32
400
401 #define ELBT_CLSWAIT 1000 /* msec to wait for further input frames */
402
403 typedef
404 struct {
405 uint off;
406 char *lab;
407 }
408 elbt_prdesc;
409
410 typedef
411 struct {
412 uint _l, _f, m, bc, mc, lg, no, sh, cr, ov, cl;
413 uint badsrc, badtyp, badlen, badbit;
414 }
415 elbt_rxeacc;
416
417 static elbt_prdesc rxeacc_descs[] = {
418 { offsetof(elbt_rxeacc, _l), "Not Last in Frame" },
419 { offsetof(elbt_rxeacc, _f), "Not First in Frame" },
420 { offsetof(elbt_rxeacc, m), "Address Miss" },
421 { offsetof(elbt_rxeacc, bc), "Broadcast Address" },
422 { offsetof(elbt_rxeacc, mc), "Multicast Address" },
423 { offsetof(elbt_rxeacc, lg), "Frame Length Violation"},
424 { offsetof(elbt_rxeacc, no), "Non-Octet Alignment" },
425 { offsetof(elbt_rxeacc, sh), "Short Frame" },
426 { offsetof(elbt_rxeacc, cr), "CRC Error" },
427 { offsetof(elbt_rxeacc, ov), "Overrun" },
428 { offsetof(elbt_rxeacc, cl), "Collision" },
429 { offsetof(elbt_rxeacc, badsrc), "Bad Src Address" },
430 { offsetof(elbt_rxeacc, badtyp), "Bad Frame Type" },
431 { offsetof(elbt_rxeacc, badlen), "Bad Frame Length" },
432 { offsetof(elbt_rxeacc, badbit), "Data Compare Errors" },
433 };
434 static int rxeacc_ndesc = sizeof (rxeacc_descs) / sizeof (rxeacc_descs[0]);
435
436 typedef
437 struct {
438 uint def, hb, lc, rl, rc, un, csl;
439 }
440 elbt_txeacc;
441
442 static elbt_prdesc txeacc_descs[] = {
443 { offsetof(elbt_txeacc, def), "Defer Indication" },
444 { offsetof(elbt_txeacc, hb), "Heartbeat" },
445 { offsetof(elbt_txeacc, lc), "Late Collision" },
446 { offsetof(elbt_txeacc, rl), "Retransmission Limit" },
447 { offsetof(elbt_txeacc, rc), "Retry Count" },
448 { offsetof(elbt_txeacc, un), "Underrun" },
449 { offsetof(elbt_txeacc, csl), "Carrier Sense Lost" },
450 };
451 static int txeacc_ndesc = sizeof (txeacc_descs) / sizeof (txeacc_descs[0]);
452
453 typedef
454 struct {
455 uchar rxbufs[ELBT_NRXBD][ELBT_BUFSZ];
456 uchar txbufs[ELBT_NTXBD][ELBT_BUFSZ];
457 cbd_t rxbd[ELBT_NRXBD];
458 cbd_t txbd[ELBT_NTXBD];
459 enum { Idle, Running, Closing, Closed } state;
460 int proff, page, sblock;
461 uint clstime, nsent, ntxerr, nrcvd, nrxerr;
462 ushort rxerrs[ELBT_MAXRXERR], txerrs[ELBT_MAXTXERR];
463 elbt_rxeacc rxeacc;
464 elbt_txeacc txeacc;
465 } __attribute__ ((aligned(8)))
466 elbt_chan;
467
468 static uchar patbytes[ELBT_NTXBD] = {
469 0xff, 0xaa, 0x55, 0x00
470 };
471 static uint patwords[ELBT_NTXBD] = {
472 0xffffffff, 0xaaaaaaaa, 0x55555555, 0x00000000
473 };
474
475 #ifdef __GNUC__
476 static elbt_chan elbt_chans[3] __attribute__ ((aligned(8)));
477 #else
478 #error "elbt_chans must be 64-bit aligned"
479 #endif
480
481 #define CPM_CR_GRACEFUL_STOP_TX ((ushort)0x0005)
482
483 static elbt_prdesc epram_descs[] = {
484 { offsetof(fcc_enet_t, fen_crcec), "CRC Errors" },
485 { offsetof(fcc_enet_t, fen_alec), "Alignment Errors" },
486 { offsetof(fcc_enet_t, fen_disfc), "Discarded Frames" },
487 { offsetof(fcc_enet_t, fen_octc), "Octets" },
488 { offsetof(fcc_enet_t, fen_colc), "Collisions" },
489 { offsetof(fcc_enet_t, fen_broc), "Broadcast Frames" },
490 { offsetof(fcc_enet_t, fen_mulc), "Multicast Frames" },
491 { offsetof(fcc_enet_t, fen_uspc), "Undersize Frames" },
492 { offsetof(fcc_enet_t, fen_frgc), "Fragments" },
493 { offsetof(fcc_enet_t, fen_ospc), "Oversize Frames" },
494 { offsetof(fcc_enet_t, fen_jbrc), "Jabbers" },
495 { offsetof(fcc_enet_t, fen_p64c), "64 Octet Frames" },
496 { offsetof(fcc_enet_t, fen_p65c), "65-127 Octet Frames" },
497 { offsetof(fcc_enet_t, fen_p128c), "128-255 Octet Frames" },
498 { offsetof(fcc_enet_t, fen_p256c), "256-511 Octet Frames" },
499 { offsetof(fcc_enet_t, fen_p512c), "512-1023 Octet Frames" },
500 { offsetof(fcc_enet_t, fen_p1024c), "1024-1518 Octet Frames"},
501 };
502 static int epram_ndesc = sizeof (epram_descs) / sizeof (epram_descs[0]);
503
504 /*
505 * given an elbt_prdesc array and an array of base addresses, print
506 * each prdesc down the screen with the values fetched from each
507 * base address across the screen
508 */
509 static void
510 print_desc (elbt_prdesc descs[], int ndesc, uchar *bases[], int nbase)
511 {
512 elbt_prdesc *dp = descs, *edp = dp + ndesc;
513 int i;
514
515 printf ("%32s", "");
516
517 for (i = 0; i < nbase; i++)
518 printf (" Channel %d", i);
519
520 putc ('\n');
521
522 while (dp < edp) {
523
524 printf ("%-32s", dp->lab);
525
526 for (i = 0; i < nbase; i++) {
527 uint val = *(uint *)(bases[i] + dp->off);
528
529 printf (" %10u", val);
530 }
531
532 putc ('\n');
533
534 dp++;
535 }
536 }
537
538 /*
539 * return number of bits that are set in a value; value contains
540 * nbits (right-justified) bits.
541 */
542 static uint __inline__
543 nbs (uint value, uint nbits)
544 {
545 uint cnt = 0;
546 #if 1
547 uint pos = sizeof (uint) * 8;
548
549 __asm__ __volatile__ ("\
550 mtctr %2\n\
551 1: rlwnm. %2,%1,%4,31,31\n\
552 beq 2f\n\
553 addi %0,%0,1\n\
554 2: subi %4,%4,1\n\
555 bdnz 1b"
556 : "=r"(cnt)
557 : "r"(value), "r"(nbits), "r"(cnt), "r"(pos)
558 : "ctr", "cc" );
559 #else
560 uint mask = 1;
561
562 do {
563 if (value & mask)
564 cnt++;
565 mask <<= 1;
566 } while (--nbits);
567 #endif
568
569 return (cnt);
570 }
571
572 static ulong
573 badbits (uchar *bp, int n, ulong pat)
574 {
575 ulong *lp, cnt = 0;
576 int nl;
577
578 while (n > 0 && ((ulong)bp & (sizeof (ulong) - 1)) != 0) {
579 uchar diff;
580
581 diff = *bp++ ^ (uchar)pat;
582
583 if (diff)
584 cnt += nbs ((ulong)diff, 8);
585
586 n--;
587 }
588
589 lp = (ulong *)bp;
590 nl = n / sizeof (ulong);
591 n -= nl * sizeof (ulong);
592
593 while (nl > 0) {
594 ulong diff;
595
596 diff = *lp++ ^ pat;
597
598 if (diff)
599 cnt += nbs (diff, 32);
600
601 nl--;
602 }
603
604 bp = (uchar *)lp;
605
606 while (n > 0) {
607 uchar diff;
608
609 diff = *bp++ ^ (uchar)pat;
610
611 if (diff)
612 cnt += nbs ((ulong)diff, 8);
613
614 n--;
615 }
616
617 return (cnt);
618 }
619
620 static inline unsigned short
621 swap16 (unsigned short x)
622 {
623 return (((x & 0xff) << 8) | ((x & 0xff00) >> 8));
624 }
625
626 /* broadcast is not an error - we send them like that */
627 #define BD_ENET_RX_ERRS (BD_ENET_RX_STATS & ~BD_ENET_RX_BC)
628
629 void
630 eth_loopback_test (void)
631 {
632 volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
633 volatile cpm8260_t *cp = &(immr->im_cpm);
634 int c, nclosed;
635 ulong runtime, nmsec;
636 uchar *bases[3];
637
638 puts ("FCC Ethernet External loopback test\n");
639
640 eth_getenv_enetaddr("ethaddr", net_ethaddr);
641
642 /*
643 * global initialisations for all FCC channels
644 */
645
646 /* 28.9 - (1-2): ioports have been set up already */
647
648 #if defined(CONFIG_SACSng)
649 /*
650 * Attention: this is board-specific
651 * 1, FCC2
652 */
653 # define FCC_START_LOOP 1
654 # define FCC_END_LOOP 1
655
656 /*
657 * Attention: this is board-specific
658 * - FCC2 Rx-CLK is CLK13
659 * - FCC2 Tx-CLK is CLK14
660 */
661
662 /* 28.9 - (3): connect FCC's tx and rx clocks */
663 immr->im_cpmux.cmx_uar = 0;
664 immr->im_cpmux.cmx_fcr = CMXFCR_RF2CS_CLK13|CMXFCR_TF2CS_CLK14;
665 #else
666 #error "eth_loopback_test not supported on your board"
667 #endif
668
669 puts ("Initialise FCC channels:");
670
671 for (c = FCC_START_LOOP; c <= FCC_END_LOOP; c++) {
672 elbt_chan *ecp = &elbt_chans[c];
673 volatile fcc_t *fcp = &immr->im_fcc[c];
674 volatile fcc_enet_t *fpp;
675 int i;
676 ulong addr;
677
678 /*
679 * initialise channel data
680 */
681
682 printf (" %d", c);
683
684 memset ((void *)ecp, 0, sizeof (*ecp));
685
686 ecp->state = Idle;
687
688 switch (c) {
689
690 case 0: /* FCC1 */
691 ecp->proff = PROFF_FCC1;
692 ecp->page = CPM_CR_FCC1_PAGE;
693 ecp->sblock = CPM_CR_FCC1_SBLOCK;
694 break;
695
696 case 1: /* FCC2 */
697 ecp->proff = PROFF_FCC2;
698 ecp->page = CPM_CR_FCC2_PAGE;
699 ecp->sblock = CPM_CR_FCC2_SBLOCK;
700 break;
701
702 case 2: /* FCC3 */
703 ecp->proff = PROFF_FCC3;
704 ecp->page = CPM_CR_FCC3_PAGE;
705 ecp->sblock = CPM_CR_FCC3_SBLOCK;
706 break;
707 }
708
709 /*
710 * set up tx buffers and bds
711 */
712
713 for (i = 0; i < ELBT_NTXBD; i++) {
714 cbd_t *bdp = &ecp->txbd[i];
715 uchar *bp = &ecp->txbufs[i][0];
716
717 bdp->cbd_bufaddr = (uint)bp;
718 /* room for crc */
719 bdp->cbd_datlen = ELBT_BUFSZ - ELBT_CRCSZ;
720 bdp->cbd_sc = BD_ENET_TX_READY | BD_ENET_TX_PAD | \
721 BD_ENET_TX_LAST | BD_ENET_TX_TC;
722
723 memset ((void *)bp, patbytes[i], ELBT_BUFSZ);
724 NetSetEther(bp, net_bcast_ethaddr, 0x8000);
725 }
726 ecp->txbd[ELBT_NTXBD - 1].cbd_sc |= BD_ENET_TX_WRAP;
727
728 /*
729 * set up rx buffers and bds
730 */
731
732 for (i = 0; i < ELBT_NRXBD; i++) {
733 cbd_t *bdp = &ecp->rxbd[i];
734 uchar *bp = &ecp->rxbufs[i][0];
735
736 bdp->cbd_bufaddr = (uint)bp;
737 bdp->cbd_datlen = 0;
738 bdp->cbd_sc = BD_ENET_RX_EMPTY;
739
740 memset ((void *)bp, 0, ELBT_BUFSZ);
741 }
742 ecp->rxbd[ELBT_NRXBD - 1].cbd_sc |= BD_ENET_RX_WRAP;
743
744 /*
745 * set up the FCC channel hardware
746 */
747
748 /* 28.9 - (4): GFMR: disable tx/rx, CCITT CRC, Mode Ethernet */
749 fcp->fcc_gfmr = FCC_GFMR_MODE_ENET | FCC_GFMR_TCRC_32;
750
751 /* 28.9 - (5): FPSMR: fd, enet CRC, Promis, RMON, Rx SHort */
752 fcp->fcc_fpsmr = FCC_PSMR_FDE | FCC_PSMR_LPB | \
753 FCC_PSMR_ENCRC | FCC_PSMR_PRO | \
754 FCC_PSMR_MON | FCC_PSMR_RSH;
755
756 /* 28.9 - (6): FDSR: Ethernet Syn */
757 fcp->fcc_fdsr = 0xD555;
758
759 /* 29.9 - (7): initialise parameter ram */
760 fpp = (fcc_enet_t *)&(immr->im_dprambase[ecp->proff]);
761
762 /* clear whole struct to make sure all resv fields are zero */
763 memset ((void *)fpp, 0, sizeof (fcc_enet_t));
764
765 /*
766 * common Parameter RAM area
767 *
768 * Allocate space in the reserved FCC area of DPRAM for the
769 * internal buffers. No one uses this space (yet), so we
770 * can do this. Later, we will add resource management for
771 * this area.
772 */
773 addr = CPM_FCC_SPECIAL_BASE + (c * 64);
774 fpp->fen_genfcc.fcc_riptr = addr;
775 fpp->fen_genfcc.fcc_tiptr = addr + 32;
776
777 /*
778 * Set maximum bytes per receive buffer.
779 * It must be a multiple of 32.
780 * buffers are in 60x bus memory.
781 */
782 fpp->fen_genfcc.fcc_mrblr = PKT_MAXBLR_SIZE;
783 fpp->fen_genfcc.fcc_rstate = (CPMFCR_GBL | CPMFCR_EB) << 24;
784 fpp->fen_genfcc.fcc_rbase = (unsigned int)(&ecp->rxbd[0]);
785 fpp->fen_genfcc.fcc_tstate = (CPMFCR_GBL | CPMFCR_EB) << 24;
786 fpp->fen_genfcc.fcc_tbase = (unsigned int)(&ecp->txbd[0]);
787
788 /* protocol-specific area */
789 fpp->fen_cmask = 0xdebb20e3; /* CRC mask */
790 fpp->fen_cpres = 0xffffffff; /* CRC preset */
791 fpp->fen_retlim = 15; /* Retry limit threshold */
792 fpp->fen_mflr = PKT_MAXBUF_SIZE;/* max frame length register */
793
794 /*
795 * Set Ethernet station address.
796 *
797 * This is supplied in the board information structure, so we
798 * copy that into the controller.
799 * So, far we have only been given one Ethernet address. We use
800 * the same address for all channels
801 */
802 fpp->fen_paddrh = (net_ethaddr[5] << 8) + net_ethaddr[4];
803 fpp->fen_paddrm = (net_ethaddr[3] << 8) + net_ethaddr[2];
804 fpp->fen_paddrl = (net_ethaddr[1] << 8) + net_ethaddr[0];
805
806 fpp->fen_minflr = PKT_MINBUF_SIZE; /* min frame len register */
807 /*
808 * pad pointer. use tiptr since we don't need
809 * a specific padding char
810 */
811 fpp->fen_padptr = fpp->fen_genfcc.fcc_tiptr;
812 fpp->fen_maxd1 = PKT_MAXDMA_SIZE; /* max DMA1 length */
813 fpp->fen_maxd2 = PKT_MAXDMA_SIZE; /* max DMA2 length */
814 fpp->fen_rfthr = 1;
815 fpp->fen_rfcnt = 1;
816
817 /* 28.9 - (8): clear out events in FCCE */
818 fcp->fcc_fcce = ~0x0;
819
820 /* 28.9 - (9): FCCM: mask all events */
821 fcp->fcc_fccm = 0;
822
823 /* 28.9 - (10-12): we don't use ethernet interrupts */
824
825 /* 28.9 - (13)
826 *
827 * Let's re-initialize the channel now. We have to do it later
828 * than the manual describes because we have just now finished
829 * the BD initialization.
830 */
831 cp->cp_cpcr = mk_cr_cmd (ecp->page, ecp->sblock, \
832 0x0c, CPM_CR_INIT_TRX) | CPM_CR_FLG;
833 do {
834 __asm__ __volatile__ ("eieio");
835 } while (cp->cp_cpcr & CPM_CR_FLG);
836 }
837
838 puts (" done\nStarting test... (Ctrl-C to Finish)\n");
839
840 /*
841 * Note: don't want serial output from here until the end of the
842 * test - the delays would probably stuff things up.
843 */
844
845 clear_ctrlc ();
846 runtime = get_timer (0);
847
848 do {
849 nclosed = 0;
850
851 for (c = FCC_START_LOOP; c <= FCC_END_LOOP; c++) {
852 volatile fcc_t *fcp = &immr->im_fcc[c];
853 elbt_chan *ecp = &elbt_chans[c];
854 int i;
855
856 switch (ecp->state) {
857
858 case Idle:
859 /*
860 * set the channel Running ...
861 */
862
863 /* 28.9 - (14): enable tx/rx in gfmr */
864 fcp->fcc_gfmr |= FCC_GFMR_ENT | FCC_GFMR_ENR;
865
866 ecp->state = Running;
867 break;
868
869 case Running:
870 /*
871 * (while Running only) check for
872 * termination of the test
873 */
874
875 (void)ctrlc ();
876
877 if (had_ctrlc ()) {
878 /*
879 * initiate a "graceful stop transmit"
880 * on the channel
881 */
882 cp->cp_cpcr = mk_cr_cmd (ecp->page, \
883 ecp->sblock, 0x0c, \
884 CPM_CR_GRACEFUL_STOP_TX) | \
885 CPM_CR_FLG;
886 do {
887 __asm__ __volatile__ ("eieio");
888 } while (cp->cp_cpcr & CPM_CR_FLG);
889
890 ecp->clstime = get_timer (0);
891 ecp->state = Closing;
892 }
893 /* fall through ... */
894
895 case Closing:
896 /*
897 * (while Running or Closing) poll the channel:
898 * - check for any non-READY tx buffers and
899 * make them ready
900 * - check for any non-EMPTY rx buffers and
901 * check that they were received correctly,
902 * adjust counters etc, then make empty
903 */
904
905 for (i = 0; i < ELBT_NTXBD; i++) {
906 cbd_t *bdp = &ecp->txbd[i];
907 ushort sc = bdp->cbd_sc;
908
909 if ((sc & BD_ENET_TX_READY) != 0)
910 continue;
911
912 /*
913 * this frame has finished
914 * transmitting
915 */
916 ecp->nsent++;
917
918 if (sc & BD_ENET_TX_STATS) {
919 ulong n;
920
921 /*
922 * we had an error on
923 * the transmission
924 */
925 n = ecp->ntxerr++;
926 if (n < ELBT_MAXTXERR)
927 ecp->txerrs[n] = sc;
928
929 if (sc & BD_ENET_TX_DEF)
930 ecp->txeacc.def++;
931 if (sc & BD_ENET_TX_HB)
932 ecp->txeacc.hb++;
933 if (sc & BD_ENET_TX_LC)
934 ecp->txeacc.lc++;
935 if (sc & BD_ENET_TX_RL)
936 ecp->txeacc.rl++;
937 if (sc & BD_ENET_TX_RCMASK)
938 ecp->txeacc.rc++;
939 if (sc & BD_ENET_TX_UN)
940 ecp->txeacc.un++;
941 if (sc & BD_ENET_TX_CSL)
942 ecp->txeacc.csl++;
943
944 bdp->cbd_sc &= \
945 ~BD_ENET_TX_STATS;
946 }
947
948 if (ecp->state == Closing)
949 ecp->clstime = get_timer (0);
950
951 /* make it ready again */
952 bdp->cbd_sc |= BD_ENET_TX_READY;
953 }
954
955 for (i = 0; i < ELBT_NRXBD; i++) {
956 cbd_t *bdp = &ecp->rxbd[i];
957 ushort sc = bdp->cbd_sc, mask;
958
959 if ((sc & BD_ENET_RX_EMPTY) != 0)
960 continue;
961
962 /* we have a new frame in this buffer */
963 ecp->nrcvd++;
964
965 mask = BD_ENET_RX_LAST|BD_ENET_RX_FIRST;
966 if ((sc & mask) != mask) {
967 /* somethings wrong here ... */
968 if (!(sc & BD_ENET_RX_LAST))
969 ecp->rxeacc._l++;
970 if (!(sc & BD_ENET_RX_FIRST))
971 ecp->rxeacc._f++;
972 }
973
974 if (sc & BD_ENET_RX_ERRS) {
975 ulong n;
976
977 /*
978 * we had some sort of error
979 * on the frame
980 */
981 n = ecp->nrxerr++;
982 if (n < ELBT_MAXRXERR)
983 ecp->rxerrs[n] = sc;
984
985 if (sc & BD_ENET_RX_MISS)
986 ecp->rxeacc.m++;
987 if (sc & BD_ENET_RX_BC)
988 ecp->rxeacc.bc++;
989 if (sc & BD_ENET_RX_MC)
990 ecp->rxeacc.mc++;
991 if (sc & BD_ENET_RX_LG)
992 ecp->rxeacc.lg++;
993 if (sc & BD_ENET_RX_NO)
994 ecp->rxeacc.no++;
995 if (sc & BD_ENET_RX_SH)
996 ecp->rxeacc.sh++;
997 if (sc & BD_ENET_RX_CR)
998 ecp->rxeacc.cr++;
999 if (sc & BD_ENET_RX_OV)
1000 ecp->rxeacc.ov++;
1001 if (sc & BD_ENET_RX_CL)
1002 ecp->rxeacc.cl++;
1003
1004 bdp->cbd_sc &= \
1005 ~BD_ENET_RX_ERRS;
1006 }
1007 else {
1008 ushort datlen = bdp->cbd_datlen;
1009 struct ethernet_hdr *ehp;
1010 ushort prot;
1011 int ours, tb, n, nbytes;
1012
1013 ehp = (struct ethernet_hdr *) \
1014 &ecp->rxbufs[i][0];
1015
1016 ours = memcmp (ehp->et_src, \
1017 net_ethaddr, 6);
1018
1019 prot = swap16 (ehp->et_protlen);
1020 tb = prot & 0x8000;
1021 n = prot & 0x7fff;
1022
1023 nbytes = ELBT_BUFSZ -
1024 ETHER_HDR_SIZE -
1025 ELBT_CRCSZ;
1026
1027 /* check the frame is correct */
1028 if (datlen != ELBT_BUFSZ)
1029 ecp->rxeacc.badlen++;
1030 else if (!ours)
1031 ecp->rxeacc.badsrc++;
1032 else if (!tb || n >= ELBT_NTXBD)
1033 ecp->rxeacc.badtyp++;
1034 else {
1035 ulong patword = \
1036 patwords[n];
1037 uint nbb;
1038
1039 nbb = badbits(
1040 ((uchar *)&ehp) +
1041 ETHER_HDR_SIZE,
1042 nbytes, patword);
1043
1044 ecp->rxeacc.badbit += \
1045 nbb;
1046 }
1047 }
1048
1049 if (ecp->state == Closing)
1050 ecp->clstime = get_timer (0);
1051
1052 /* make it empty again */
1053 bdp->cbd_sc |= BD_ENET_RX_EMPTY;
1054 }
1055
1056 if (ecp->state != Closing)
1057 break;
1058
1059 /*
1060 * (while Closing) check to see if
1061 * waited long enough
1062 */
1063
1064 if (get_timer (ecp->clstime) >= ELBT_CLSWAIT) {
1065 /* write GFMR: disable tx/rx */
1066 fcp->fcc_gfmr &= \
1067 ~(FCC_GFMR_ENT | FCC_GFMR_ENR);
1068 ecp->state = Closed;
1069 }
1070
1071 break;
1072
1073 case Closed:
1074 nclosed++;
1075 break;
1076 }
1077 }
1078
1079 } while (nclosed < (FCC_END_LOOP - FCC_START_LOOP + 1));
1080
1081 runtime = get_timer (runtime);
1082 if (runtime <= ELBT_CLSWAIT) {
1083 printf ("Whoops! somehow elapsed time (%ld) is wrong (<= %d)\n",
1084 runtime, ELBT_CLSWAIT);
1085 return;
1086 }
1087 nmsec = runtime - ELBT_CLSWAIT;
1088
1089 printf ("Test Finished in %ldms (plus %dms close wait period)!\n\n",
1090 nmsec, ELBT_CLSWAIT);
1091
1092 /*
1093 * now print stats
1094 */
1095
1096 for (c = FCC_START_LOOP; c <= FCC_END_LOOP; c++) {
1097 elbt_chan *ecp = &elbt_chans[c];
1098 uint rxpps, txpps, nerr;
1099
1100 rxpps = (ecp->nrcvd * 1000) / nmsec;
1101 txpps = (ecp->nsent * 1000) / nmsec;
1102
1103 printf ("Channel %d: %d rcvd (%d pps, %d rxerrs), "
1104 "%d sent (%d pps, %d txerrs)\n\n", c,
1105 ecp->nrcvd, rxpps, ecp->nrxerr,
1106 ecp->nsent, txpps, ecp->ntxerr);
1107
1108 if ((nerr = ecp->nrxerr) > 0) {
1109 ulong i;
1110
1111 printf ("\tFirst %d rx errs:", nerr);
1112 for (i = 0; i < nerr; i++)
1113 printf (" %04x", ecp->rxerrs[i]);
1114 putc ('\n');
1115 }
1116
1117 if ((nerr = ecp->ntxerr) > 0) {
1118 ulong i;
1119
1120 printf ("\tFirst %d tx errs:", nerr);
1121 for (i = 0; i < nerr; i++)
1122 printf (" %04x", ecp->txerrs[i]);
1123 putc ('\n');
1124 }
1125 }
1126
1127 puts ("Receive Error Counts:\n");
1128 for (c = FCC_START_LOOP; c <= FCC_END_LOOP; c++)
1129 bases[c] = (uchar *)&elbt_chans[c].rxeacc;
1130 print_desc (rxeacc_descs, rxeacc_ndesc, bases, 3);
1131
1132 puts ("\nTransmit Error Counts:\n");
1133 for (c = FCC_START_LOOP; c <= FCC_END_LOOP; c++)
1134 bases[c] = (uchar *)&elbt_chans[c].txeacc;
1135 print_desc (txeacc_descs, txeacc_ndesc, bases, 3);
1136
1137 puts ("\nRMON(-like) Counters:\n");
1138 for (c = FCC_START_LOOP; c <= FCC_END_LOOP; c++)
1139 bases[c] = (uchar *)&immr->im_dprambase[elbt_chans[c].proff];
1140 print_desc (epram_descs, epram_ndesc, bases, 3);
1141 }
1142
1143 #endif /* CONFIG_ETHER_LOOPBACK_TEST */
1144
1145 #endif
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