arch/powerpc/cpu/mpc8260/serial_smc.c

   1 /*
   2  * (C) Copyright 2000, 2001, 2002
   3  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0+
   6  *
   7  * Hacked for MPC8260 by Murray.Jensen@cmst.csiro.au, 19-Oct-00, with
   8  * changes based on the file arch/powerpc/mbxboot/m8260_tty.c from the
   9  * Linux/PPC sources (m8260_tty.c had no copyright info in it).
  10  */
  11
  12 /*
  13  * Minimal serial functions needed to use one of the SMC ports
  14  * as serial console interface.
  15  */
  16
  17 #include <common.h>
  18 #include <mpc8260.h>
  19 #include <asm/cpm_8260.h>
  20 #include <serial.h>
  21 #include <linux/compiler.h>
  22
  23 DECLARE_GLOBAL_DATA_PTR;
  24
  25 #if defined(CONFIG_CONS_ON_SMC)
  26
  27 #if CONFIG_CONS_INDEX == 1      /* Console on SMC1 */
  28
  29 #define SMC_INDEX               0
  30 #define PROFF_SMC_BASE          PROFF_SMC1_BASE
  31 #define PROFF_SMC               PROFF_SMC1
  32 #define CPM_CR_SMC_PAGE         CPM_CR_SMC1_PAGE
  33 #define CPM_CR_SMC_SBLOCK       CPM_CR_SMC1_SBLOCK
  34 #define CMXSMR_MASK             (CMXSMR_SMC1|CMXSMR_SMC1CS_MSK)
  35 #define CMXSMR_VALUE            CMXSMR_SMC1CS_BRG7
  36
  37 #elif CONFIG_CONS_INDEX == 2    /* Console on SMC2 */
  38
  39 #define SMC_INDEX               1
  40 #define PROFF_SMC_BASE          PROFF_SMC2_BASE
  41 #define PROFF_SMC               PROFF_SMC2
  42 #define CPM_CR_SMC_PAGE         CPM_CR_SMC2_PAGE
  43 #define CPM_CR_SMC_SBLOCK       CPM_CR_SMC2_SBLOCK
  44 #define CMXSMR_MASK             (CMXSMR_SMC2|CMXSMR_SMC2CS_MSK)
  45 #define CMXSMR_VALUE            CMXSMR_SMC2CS_BRG8
  46
  47 #else
  48
  49 #error "console not correctly defined"
  50
  51 #endif
  52
  53 #if !defined(CONFIG_SYS_SMC_RXBUFLEN)
  54 #define CONFIG_SYS_SMC_RXBUFLEN 1
  55 #define CONFIG_SYS_MAXIDLE      0
  56 #else
  57 #if !defined(CONFIG_SYS_MAXIDLE)
  58 #error "you must define CONFIG_SYS_MAXIDLE"
  59 #endif
  60 #endif
  61
  62 typedef volatile struct serialbuffer {
  63         cbd_t   rxbd;           /* Rx BD */
  64         cbd_t   txbd;           /* Tx BD */
  65         uint    rxindex;        /* index for next character to read */
  66         volatile uchar  rxbuf[CONFIG_SYS_SMC_RXBUFLEN];/* rx buffers */
  67         volatile uchar  txbuf;  /* tx buffers */
  68 } serialbuffer_t;
  69
  70 /* map rs_table index to baud rate generator index */
  71 static unsigned char brg_map[] = {
  72         6,      /* BRG7 for SMC1 */
  73         7,      /* BRG8 for SMC2 */
  74         0,      /* BRG1 for SCC1 */
  75         1,      /* BRG1 for SCC2 */
  76         2,      /* BRG1 for SCC3 */
  77         3,      /* BRG1 for SCC4 */
  78 };
  79
  80 static int mpc8260_smc_serial_init(void)
  81 {
  82         volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
  83         volatile smc_t *sp;
  84         volatile smc_uart_t *up;
  85         volatile cpm8260_t *cp = &(im->im_cpm);
  86         uint    dpaddr;
  87         volatile serialbuffer_t *rtx;
  88
  89         /* initialize pointers to SMC */
  90
  91         sp = (smc_t *) &(im->im_smc[SMC_INDEX]);
  92         im->im_dprambase16[PROFF_SMC_BASE / sizeof(u16)] = PROFF_SMC;
  93         up = (smc_uart_t *)&im->im_dprambase[PROFF_SMC];
  94
  95         /* Disable transmitter/receiver. */
  96         sp->smc_smcmr &= ~(SMCMR_REN | SMCMR_TEN);
  97
  98         /* NOTE: I/O port pins are set up via the iop_conf_tab[] table */
  99
 100         /* Allocate space for two buffer descriptors in the DP ram.
 101          * damm: allocating space after the two buffers for rx/tx data
 102          */
 103
 104         /* allocate size of struct serialbuffer with bd rx/tx,
 105          * buffer rx/tx and rx index
 106          */
 107         dpaddr = m8260_cpm_dpalloc((sizeof(serialbuffer_t)), 16);
 108
 109         rtx = (serialbuffer_t *)&im->im_dprambase[dpaddr];
 110
 111         /* Set the physical address of the host memory buffers in
 112          * the buffer descriptors.
 113          */
 114         rtx->rxbd.cbd_bufaddr = (uint) &rtx->rxbuf;
 115         rtx->rxbd.cbd_sc      = 0;
 116
 117         rtx->txbd.cbd_bufaddr = (uint) &rtx->txbuf;
 118         rtx->txbd.cbd_sc      = 0;
 119
 120         /* Set up the uart parameters in the parameter ram. */
 121         up->smc_rbase = dpaddr;
 122         up->smc_tbase = dpaddr+sizeof(cbd_t);
 123         up->smc_rfcr = CPMFCR_EB;
 124         up->smc_tfcr = CPMFCR_EB;
 125         up->smc_brklen = 0;
 126         up->smc_brkec = 0;
 127         up->smc_brkcr = 0;
 128
 129         /* Set UART mode, 8 bit, no parity, one stop.
 130          * Enable receive and transmit.
 131          */
 132         sp->smc_smcmr = smcr_mk_clen(9) |  SMCMR_SM_UART;
 133
 134         /* Mask all interrupts and remove anything pending. */
 135         sp->smc_smcm = 0;
 136         sp->smc_smce = 0xff;
 137
 138         /* put the SMC channel into NMSI (non multiplexd serial interface)
 139          * mode and wire either BRG7 to SMC1 or BRG8 to SMC2 (15-17).
 140          */
 141         im->im_cpmux.cmx_smr = (im->im_cpmux.cmx_smr&~CMXSMR_MASK)|CMXSMR_VALUE;
 142
 143         /* Set up the baud rate generator. */
 144         serial_setbrg ();
 145
 146         /* Make the first buffer the only buffer. */
 147         rtx->txbd.cbd_sc |= BD_SC_WRAP;
 148         rtx->rxbd.cbd_sc |= BD_SC_EMPTY | BD_SC_WRAP;
 149
 150         /* single/multi character receive. */
 151         up->smc_mrblr = CONFIG_SYS_SMC_RXBUFLEN;
 152         up->smc_maxidl = CONFIG_SYS_MAXIDLE;
 153         rtx->rxindex = 0;
 154
 155         /* Initialize Tx/Rx parameters. */
 156
 157         while (cp->cp_cpcr & CPM_CR_FLG)  /* wait if cp is busy */
 158           ;
 159
 160         cp->cp_cpcr = mk_cr_cmd(CPM_CR_SMC_PAGE, CPM_CR_SMC_SBLOCK,
 161                                         0, CPM_CR_INIT_TRX) | CPM_CR_FLG;
 162
 163         while (cp->cp_cpcr & CPM_CR_FLG)  /* wait if cp is busy */
 164           ;
 165
 166         /* Enable transmitter/receiver. */
 167         sp->smc_smcmr |= SMCMR_REN | SMCMR_TEN;
 168
 169         return (0);
 170 }
 171
 172 static void mpc8260_smc_serial_setbrg(void)
 173 {
 174 #if defined(CONFIG_CONS_USE_EXTC)
 175         m8260_cpm_extcbrg(brg_map[SMC_INDEX], gd->baudrate,
 176                 CONFIG_CONS_EXTC_RATE, CONFIG_CONS_EXTC_PINSEL);
 177 #else
 178         m8260_cpm_setbrg(brg_map[SMC_INDEX], gd->baudrate);
 179 #endif
 180 }
 181
 182 static void mpc8260_smc_serial_putc(const char c)
 183 {
 184         volatile smc_uart_t     *up;
 185         volatile immap_t        *im = (immap_t *)CONFIG_SYS_IMMR;
 186         volatile serialbuffer_t *rtx;
 187
 188         if (c == '\n')
 189                 serial_putc ('\r');
 190
 191         up = (smc_uart_t *)&(im->im_dprambase[PROFF_SMC]);
 192
 193         rtx = (serialbuffer_t *)&im->im_dprambase[up->smc_rbase];
 194
 195         /* Wait for last character to go. */
 196         while (rtx->txbd.cbd_sc & BD_SC_READY & BD_SC_READY)
 197                 ;
 198         rtx->txbuf = c;
 199         rtx->txbd.cbd_datlen = 1;
 200         rtx->txbd.cbd_sc |= BD_SC_READY;
 201 }
 202
 203 static int mpc8260_smc_serial_getc(void)
 204 {
 205         volatile smc_uart_t     *up;
 206         volatile immap_t        *im = (immap_t *)CONFIG_SYS_IMMR;
 207         volatile serialbuffer_t *rtx;
 208         unsigned char  c;
 209
 210         up = (smc_uart_t *)&(im->im_dprambase[PROFF_SMC]);
 211
 212         rtx = (serialbuffer_t *)&im->im_dprambase[up->smc_rbase];
 213
 214         /* Wait for character to show up. */
 215         while (rtx->rxbd.cbd_sc & BD_SC_EMPTY)
 216                 ;
 217
 218         /* the characters are read one by one,
 219          * use the rxindex to know the next char to deliver
 220          */
 221         c = *(unsigned char *) (rtx->rxbd.cbd_bufaddr + rtx->rxindex);
 222         rtx->rxindex++;
 223
 224         /* check if all char are readout, then make prepare for next receive */
 225         if (rtx->rxindex >= rtx->rxbd.cbd_datlen) {
 226                 rtx->rxindex = 0;
 227                 rtx->rxbd.cbd_sc |= BD_SC_EMPTY;
 228         }
 229         return(c);
 230 }
 231
 232 static int mpc8260_smc_serial_tstc(void)
 233 {
 234         volatile smc_uart_t     *up;
 235         volatile immap_t        *im = (immap_t *)CONFIG_SYS_IMMR;
 236         volatile serialbuffer_t *rtx;
 237
 238         up = (smc_uart_t *)&(im->im_dprambase[PROFF_SMC]);
 239         rtx = (serialbuffer_t *)&im->im_dprambase[up->smc_rbase];
 240
 241         return !(rtx->rxbd.cbd_sc & BD_SC_EMPTY);
 242 }
 243
 244 static struct serial_device mpc8260_smc_serial_drv = {
 245         .name   = "mpc8260_smc_uart",
 246         .start  = mpc8260_smc_serial_init,
 247         .stop   = NULL,
 248         .setbrg = mpc8260_smc_serial_setbrg,
 249         .putc   = mpc8260_smc_serial_putc,
 250         .puts   = default_serial_puts,
 251         .getc   = mpc8260_smc_serial_getc,
 252         .tstc   = mpc8260_smc_serial_tstc,
 253 };
 254
 255 void mpc8260_smc_serial_initialize(void)
 256 {
 257         serial_register(&mpc8260_smc_serial_drv);
 258 }
 259
 260 __weak struct serial_device *default_serial_console(void)
 261 {
 262         return &mpc8260_smc_serial_drv;
 263 }
 264 #endif  /* CONFIG_CONS_ON_SMC */
 265
 266 #if defined(CONFIG_KGDB_ON_SMC)
 267
 268 #if defined(CONFIG_CONS_ON_SMC) && CONFIG_KGDB_INDEX == CONFIG_CONS_INDEX
 269 #error Whoops! serial console and kgdb are on the same smc serial port
 270 #endif
 271
 272 #if CONFIG_KGDB_INDEX == 1      /* KGDB Port on SMC1 */
 273
 274 #define KGDB_SMC_INDEX          0
 275 #define KGDB_PROFF_SMC_BASE     PROFF_SMC1_BASE
 276 #define KGDB_PROFF_SMC          PROFF_SMC1
 277 #define KGDB_CPM_CR_SMC_PAGE    CPM_CR_SMC1_PAGE
 278 #define KGDB_CPM_CR_SMC_SBLOCK  CPM_CR_SMC1_SBLOCK
 279 #define KGDB_CMXSMR_MASK        (CMXSMR_SMC1|CMXSMR_SMC1CS_MSK)
 280 #define KGDB_CMXSMR_VALUE       CMXSMR_SMC1CS_BRG7
 281
 282 #elif CONFIG_KGDB_INDEX == 2    /* KGDB Port on SMC2 */
 283
 284 #define KGDB_SMC_INDEX          1
 285 #define KGDB_PROFF_SMC_BASE     PROFF_SMC2_BASE
 286 #define KGDB_PROFF_SMC          PROFF_SMC2
 287 #define KGDB_CPM_CR_SMC_PAGE    CPM_CR_SMC2_PAGE
 288 #define KGDB_CPM_CR_SMC_SBLOCK  CPM_CR_SMC2_SBLOCK
 289 #define KGDB_CMXSMR_MASK        (CMXSMR_SMC2|CMXSMR_SMC2CS_MSK)
 290 #define KGDB_CMXSMR_VALUE       CMXSMR_SMC2CS_BRG8
 291
 292 #else
 293
 294 #error "console not correctly defined"
 295
 296 #endif
 297
 298 void
 299 kgdb_serial_init (void)
 300 {
 301         volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
 302         volatile smc_t *sp;
 303         volatile smc_uart_t *up;
 304         volatile cbd_t *tbdf, *rbdf;
 305         volatile cpm8260_t *cp = &(im->im_cpm);
 306         uint dpaddr, speed = CONFIG_KGDB_BAUDRATE;
 307         char *s, *e;
 308
 309         if ((s = getenv("kgdbrate")) != NULL && *s != '\0') {
 310                 ulong rate = simple_strtoul(s, &e, 10);
 311                 if (e > s && *e == '\0')
 312                         speed = rate;
 313         }
 314
 315         /* initialize pointers to SMC */
 316
 317         sp = (smc_t *) &(im->im_smc[KGDB_SMC_INDEX]);
 318         im->im_dprambase16[KGDB_PROFF_SMC_BASE / sizeof(u16)] = KGDB_PROFF_SMC;
 319         up = (smc_uart_t *)&im->im_dprambase[KGDB_PROFF_SMC];
 320
 321         /* Disable transmitter/receiver. */
 322         sp->smc_smcmr &= ~(SMCMR_REN | SMCMR_TEN);
 323
 324         /* NOTE: I/O port pins are set up via the iop_conf_tab[] table */
 325
 326         /* Allocate space for two buffer descriptors in the DP ram.
 327          * damm: allocating space after the two buffers for rx/tx data
 328          */
 329
 330         dpaddr = m8260_cpm_dpalloc((2 * sizeof (cbd_t)) + 2, 16);
 331
 332         /* Set the physical address of the host memory buffers in
 333          * the buffer descriptors.
 334          */
 335         rbdf = (cbd_t *)&im->im_dprambase[dpaddr];
 336         rbdf->cbd_bufaddr = (uint) (rbdf+2);
 337         rbdf->cbd_sc = 0;
 338         tbdf = rbdf + 1;
 339         tbdf->cbd_bufaddr = ((uint) (rbdf+2)) + 1;
 340         tbdf->cbd_sc = 0;
 341
 342         /* Set up the uart parameters in the parameter ram. */
 343         up->smc_rbase = dpaddr;
 344         up->smc_tbase = dpaddr+sizeof(cbd_t);
 345         up->smc_rfcr = CPMFCR_EB;
 346         up->smc_tfcr = CPMFCR_EB;
 347         up->smc_brklen = 0;
 348         up->smc_brkec = 0;
 349         up->smc_brkcr = 0;
 350
 351         /* Set UART mode, 8 bit, no parity, one stop.
 352          * Enable receive and transmit.
 353          */
 354         sp->smc_smcmr = smcr_mk_clen(9) |  SMCMR_SM_UART;
 355
 356         /* Mask all interrupts and remove anything pending. */
 357         sp->smc_smcm = 0;
 358         sp->smc_smce = 0xff;
 359
 360         /* put the SMC channel into NMSI (non multiplexd serial interface)
 361          * mode and wire either BRG7 to SMC1 or BRG8 to SMC2 (15-17).
 362          */
 363         im->im_cpmux.cmx_smr =
 364                 (im->im_cpmux.cmx_smr & ~KGDB_CMXSMR_MASK) | KGDB_CMXSMR_VALUE;
 365
 366         /* Set up the baud rate generator. */
 367 #if defined(CONFIG_KGDB_USE_EXTC)
 368         m8260_cpm_extcbrg(brg_map[KGDB_SMC_INDEX], speed,
 369                 CONFIG_KGDB_EXTC_RATE, CONFIG_KGDB_EXTC_PINSEL);
 370 #else
 371         m8260_cpm_setbrg(brg_map[KGDB_SMC_INDEX], speed);
 372 #endif
 373
 374         /* Make the first buffer the only buffer. */
 375         tbdf->cbd_sc |= BD_SC_WRAP;
 376         rbdf->cbd_sc |= BD_SC_EMPTY | BD_SC_WRAP;
 377
 378         /* Single character receive. */
 379         up->smc_mrblr = 1;
 380         up->smc_maxidl = 0;
 381
 382         /* Initialize Tx/Rx parameters. */
 383
 384         while (cp->cp_cpcr & CPM_CR_FLG)  /* wait if cp is busy */
 385           ;
 386
 387         cp->cp_cpcr = mk_cr_cmd(KGDB_CPM_CR_SMC_PAGE, KGDB_CPM_CR_SMC_SBLOCK,
 388                                         0, CPM_CR_INIT_TRX) | CPM_CR_FLG;
 389
 390         while (cp->cp_cpcr & CPM_CR_FLG)  /* wait if cp is busy */
 391           ;
 392
 393         /* Enable transmitter/receiver. */
 394         sp->smc_smcmr |= SMCMR_REN | SMCMR_TEN;
 395
 396         printf("SMC%d at %dbps ", CONFIG_KGDB_INDEX, speed);
 397 }
 398
 399 void
 400 putDebugChar(const char c)
 401 {
 402         volatile cbd_t          *tbdf;
 403         volatile char           *buf;
 404         volatile smc_uart_t     *up;
 405         volatile immap_t        *im = (immap_t *)CONFIG_SYS_IMMR;
 406
 407         if (c == '\n')
 408                 putDebugChar ('\r');
 409
 410         up = (smc_uart_t *)&(im->im_dprambase[KGDB_PROFF_SMC]);
 411
 412         tbdf = (cbd_t *)&im->im_dprambase[up->smc_tbase];
 413
 414         /* Wait for last character to go. */
 415         buf = (char *)tbdf->cbd_bufaddr;
 416         while (tbdf->cbd_sc & BD_SC_READY)
 417                 ;
 418
 419         *buf = c;
 420         tbdf->cbd_datlen = 1;
 421         tbdf->cbd_sc |= BD_SC_READY;
 422 }
 423
 424 void
 425 putDebugStr (const char *s)
 426 {
 427         while (*s) {
 428                 putDebugChar (*s++);
 429         }
 430 }
 431
 432 int
 433 getDebugChar(void)
 434 {
 435         volatile cbd_t          *rbdf;
 436         volatile unsigned char  *buf;
 437         volatile smc_uart_t     *up;
 438         volatile immap_t        *im = (immap_t *)CONFIG_SYS_IMMR;
 439         unsigned char           c;
 440
 441         up = (smc_uart_t *)&(im->im_dprambase[KGDB_PROFF_SMC]);
 442
 443         rbdf = (cbd_t *)&im->im_dprambase[up->smc_rbase];
 444
 445         /* Wait for character to show up. */
 446         buf = (unsigned char *)rbdf->cbd_bufaddr;
 447         while (rbdf->cbd_sc & BD_SC_EMPTY)
 448                 ;
 449         c = *buf;
 450         rbdf->cbd_sc |= BD_SC_EMPTY;
 451
 452         return(c);
 453 }
 454
 455 void
 456 kgdb_interruptible(int yes)
 457 {
 458         return;
 459 }
 460
 461 #endif  /* CONFIG_KGDB_ON_SMC */