arch/powerpc/cpu/mpc83xx/start.S

   1 /*
   2  * Copyright (C) 1998  Dan Malek <dmalek@jlc.net>
   3  * Copyright (C) 1999  Magnus Damm <kieraypc01.p.y.kie.era.ericsson.se>
   4  * Copyright (C) 2000, 2001,2002 Wolfgang Denk <wd@denx.de>
   5  * Copyright Freescale Semiconductor, Inc. 2004, 2006, 2008.
   6  *
   7  * SPDX-License-Identifier:     GPL-2.0+
   8  */
   9
  10 /*
  11  *  U-Boot - Startup Code for MPC83xx PowerPC based Embedded Boards
  12  */
  13
  14 #include <asm-offsets.h>
  15 #include <config.h>
  16 #include <mpc83xx.h>
  17 #include <version.h>
  18
  19 #define CONFIG_83XX     1               /* needed for Linux kernel header files*/
  20
  21 #include <ppc_asm.tmpl>
  22 #include <ppc_defs.h>
  23
  24 #include <asm/cache.h>
  25 #include <asm/mmu.h>
  26 #include <asm/u-boot.h>
  27
  28 /* We don't want the  MMU yet.
  29  */
  30 #undef  MSR_KERNEL
  31
  32 /*
  33  * Floating Point enable, Machine Check and Recoverable Interr.
  34  */
  35 #ifdef DEBUG
  36 #define MSR_KERNEL (MSR_FP|MSR_RI)
  37 #else
  38 #define MSR_KERNEL (MSR_FP|MSR_ME|MSR_RI)
  39 #endif
  40
  41 #if defined(CONFIG_NAND_SPL) || \
  42         (defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_INIT_MINIMAL))
  43 #define MINIMAL_SPL
  44 #endif
  45
  46 #if !defined(CONFIG_SPL_BUILD) && !defined(CONFIG_NAND_SPL) && \
  47         !defined(CONFIG_SYS_RAMBOOT)
  48 #define CONFIG_SYS_FLASHBOOT
  49 #endif
  50
  51 /*
  52  * Set up GOT: Global Offset Table
  53  *
  54  * Use r12 to access the GOT
  55  */
  56         START_GOT
  57         GOT_ENTRY(_GOT2_TABLE_)
  58         GOT_ENTRY(__bss_start)
  59         GOT_ENTRY(__bss_end)
  60
  61 #ifndef MINIMAL_SPL
  62         GOT_ENTRY(_FIXUP_TABLE_)
  63         GOT_ENTRY(_start)
  64         GOT_ENTRY(_start_of_vectors)
  65         GOT_ENTRY(_end_of_vectors)
  66         GOT_ENTRY(transfer_to_handler)
  67 #endif
  68         END_GOT
  69
  70 /*
  71  * The Hard Reset Configuration Word (HRCW) table is in the first 64
  72  * (0x40) bytes of flash.  It has 8 bytes, but each byte is repeated 8
  73  * times so the processor can fetch it out of flash whether the flash
  74  * is 8, 16, 32, or 64 bits wide (hardware trickery).
  75  */
  76         .text
  77 #define _HRCW_TABLE_ENTRY(w)            \
  78         .fill   8,1,(((w)>>24)&0xff);   \
  79         .fill   8,1,(((w)>>16)&0xff);   \
  80         .fill   8,1,(((w)>> 8)&0xff);   \
  81         .fill   8,1,(((w)    )&0xff)
  82
  83         _HRCW_TABLE_ENTRY(CONFIG_SYS_HRCW_LOW)
  84         _HRCW_TABLE_ENTRY(CONFIG_SYS_HRCW_HIGH)
  85
  86 /*
  87  * Magic number and version string - put it after the HRCW since it
  88  * cannot be first in flash like it is in many other processors.
  89  */
  90         .long   0x27051956              /* U-Boot Magic Number */
  91
  92         .globl  version_string
  93 version_string:
  94         .ascii U_BOOT_VERSION_STRING, "\0"
  95
  96         .align 2
  97
  98         .globl enable_addr_trans
  99 enable_addr_trans:
 100         /* enable address translation */
 101         mfmsr   r5
 102         ori     r5, r5, (MSR_IR | MSR_DR)
 103         mtmsr   r5
 104         isync
 105         blr
 106
 107         .globl disable_addr_trans
 108 disable_addr_trans:
 109         /* disable address translation */
 110         mflr    r4
 111         mfmsr   r3
 112         andi.   r0, r3, (MSR_IR | MSR_DR)
 113         beqlr
 114         andc    r3, r3, r0
 115         mtspr   SRR0, r4
 116         mtspr   SRR1, r3
 117         rfi
 118
 119         .globl get_svr
 120 get_svr:
 121         mfspr   r3, SVR
 122         blr
 123
 124         .globl get_pvr
 125 get_pvr:
 126         mfspr   r3, PVR
 127         blr
 128
 129         .globl  ppcDWstore
 130 ppcDWstore:
 131         lfd     1, 0(r4)
 132         stfd    1, 0(r3)
 133         blr
 134
 135         .globl  ppcDWload
 136 ppcDWload:
 137         lfd     1, 0(r3)
 138         stfd    1, 0(r4)
 139         blr
 140
 141 #ifndef CONFIG_DEFAULT_IMMR
 142 #error CONFIG_DEFAULT_IMMR must be defined
 143 #endif /* CONFIG_SYS_DEFAULT_IMMR */
 144 #ifndef CONFIG_SYS_IMMR
 145 #define CONFIG_SYS_IMMR CONFIG_DEFAULT_IMMR
 146 #endif /* CONFIG_SYS_IMMR */
 147
 148 /*
 149  * After configuration, a system reset exception is executed using the
 150  * vector at offset 0x100 relative to the base set by MSR[IP]. If
 151  * MSR[IP] is 0, the base address is 0x00000000. If MSR[IP] is 1, the
 152  * base address is 0xfff00000. In the case of a Power On Reset or Hard
 153  * Reset, the value of MSR[IP] is determined by the CIP field in the
 154  * HRCW.
 155  *
 156  * Other bits in the HRCW set up the Base Address and Port Size in BR0.
 157  * This determines the location of the boot ROM (flash or EPROM) in the
 158  * processor's address space at boot time. As long as the HRCW is set up
 159  * so that we eventually end up executing the code below when the
 160  * processor executes the reset exception, the actual values used should
 161  * not matter.
 162  *
 163  * Once we have got here, the address mask in OR0 is cleared so that the
 164  * bottom 32K of the boot ROM is effectively repeated all throughout the
 165  * processor's address space, after which we can jump to the absolute
 166  * address at which the boot ROM was linked at compile time, and proceed
 167  * to initialise the memory controller without worrying if the rug will
 168  * be pulled out from under us, so to speak (it will be fine as long as
 169  * we configure BR0 with the same boot ROM link address).
 170  */
 171         . = EXC_OFF_SYS_RESET
 172
 173         .globl  _start
 174 _start: /* time t 0 */
 175         lis     r4, CONFIG_DEFAULT_IMMR@h
 176         nop
 177
 178         mfmsr   r5                      /* save msr contents    */
 179
 180         /* 83xx manuals prescribe a specific sequence for updating IMMRBAR. */
 181         bl      1f
 182 1:      mflr    r7
 183
 184         lis     r3, CONFIG_SYS_IMMR@h
 185         ori     r3, r3, CONFIG_SYS_IMMR@l
 186
 187         lwz     r6, IMMRBAR(r4)
 188         isync
 189
 190         stw     r3, IMMRBAR(r4)
 191         lwz     r6, 0(r7)               /* Arbitrary external load */
 192         isync
 193
 194         lwz     r6, IMMRBAR(r3)
 195         isync
 196
 197         /* Initialise the E300 processor core           */
 198         /*------------------------------------------*/
 199
 200 #if (defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_MPC83XX_WAIT_FOR_NAND)) || \
 201                 defined(CONFIG_NAND_SPL)
 202         /* The FCM begins execution after only the first page
 203          * is loaded.  Wait for the rest before branching
 204          * to another flash page.
 205          */
 206 1:      lwz     r6, 0x50b0(r3)
 207         andi.   r6, r6, 1
 208         beq     1b
 209 #endif
 210
 211         bl      init_e300_core
 212
 213 #ifdef CONFIG_SYS_FLASHBOOT
 214
 215         /* Inflate flash location so it appears everywhere, calculate */
 216         /* the absolute address in final location of the FLASH, jump  */
 217         /* there and deflate the flash size back to minimal size      */
 218         /*------------------------------------------------------------*/
 219         bl map_flash_by_law1
 220         lis r4, (CONFIG_SYS_MONITOR_BASE)@h
 221         ori r4, r4, (CONFIG_SYS_MONITOR_BASE)@l
 222         addi r5, r4, in_flash - _start + EXC_OFF_SYS_RESET
 223         mtlr r5
 224         blr
 225 in_flash:
 226 #if 1 /* Remapping flash with LAW0. */
 227         bl remap_flash_by_law0
 228 #endif
 229 #endif  /* CONFIG_SYS_FLASHBOOT */
 230
 231         /* setup the bats */
 232         bl      setup_bats
 233         sync
 234
 235         /*
 236          * Cache must be enabled here for stack-in-cache trick.
 237          * This means we need to enable the BATS.
 238          * This means:
 239          *   1) for the EVB, original gt regs need to be mapped
 240          *   2) need to have an IBAT for the 0xf region,
 241          *      we are running there!
 242          * Cache should be turned on after BATs, since by default
 243          * everything is write-through.
 244          * The init-mem BAT can be reused after reloc. The old
 245          * gt-regs BAT can be reused after board_init_f calls
 246          * board_early_init_f (EVB only).
 247          */
 248         /* enable address translation */
 249         bl      enable_addr_trans
 250         sync
 251
 252         /* enable the data cache */
 253         bl      dcache_enable
 254         sync
 255 #ifdef CONFIG_SYS_INIT_RAM_LOCK
 256         bl      lock_ram_in_cache
 257         sync
 258 #endif
 259
 260         /* set up the stack pointer in our newly created
 261          * cache-ram (r1) */
 262         lis     r1, (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET)@h
 263         ori     r1, r1, (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET)@l
 264
 265         li      r0, 0           /* Make room for stack frame header and */
 266         stwu    r0, -4(r1)      /* clear final stack frame so that      */
 267         stwu    r0, -4(r1)      /* stack backtraces terminate cleanly   */
 268
 269
 270         /* let the C-code set up the rest                           */
 271         /*                                                          */
 272         /* Be careful to keep code relocatable & stack humble   */
 273         /*------------------------------------------------------*/
 274
 275         GET_GOT                 /* initialize GOT access        */
 276
 277         /* r3: IMMR */
 278         lis     r3, CONFIG_SYS_IMMR@h
 279         /* run low-level CPU init code (in Flash)*/
 280         bl      cpu_init_f
 281
 282         /* run 1st part of board init code (in Flash)*/
 283         li      r3, 0           /* clear boot_flag for calling board_init_f */
 284         bl      board_init_f
 285
 286         /* NOTREACHED - board_init_f() does not return */
 287
 288 #ifndef MINIMAL_SPL
 289 /*
 290  * Vector Table
 291  */
 292
 293         .globl  _start_of_vectors
 294 _start_of_vectors:
 295
 296 /* Machine check */
 297         STD_EXCEPTION(0x200, MachineCheck, MachineCheckException)
 298
 299 /* Data Storage exception. */
 300         STD_EXCEPTION(0x300, DataStorage, UnknownException)
 301
 302 /* Instruction Storage exception. */
 303         STD_EXCEPTION(0x400, InstStorage, UnknownException)
 304
 305 /* External Interrupt exception. */
 306 #ifndef FIXME
 307         STD_EXCEPTION(0x500, ExtInterrupt, external_interrupt)
 308 #endif
 309
 310 /* Alignment exception. */
 311         . = 0x600
 312 Alignment:
 313         EXCEPTION_PROLOG(SRR0, SRR1)
 314         mfspr   r4,DAR
 315         stw     r4,_DAR(r21)
 316         mfspr   r5,DSISR
 317         stw     r5,_DSISR(r21)
 318         addi    r3,r1,STACK_FRAME_OVERHEAD
 319         EXC_XFER_TEMPLATE(Alignment, AlignmentException, MSR_KERNEL, COPY_EE)
 320
 321 /* Program check exception */
 322         . = 0x700
 323 ProgramCheck:
 324         EXCEPTION_PROLOG(SRR0, SRR1)
 325         addi    r3,r1,STACK_FRAME_OVERHEAD
 326         EXC_XFER_TEMPLATE(ProgramCheck, ProgramCheckException,
 327                 MSR_KERNEL, COPY_EE)
 328
 329         STD_EXCEPTION(0x800, FPUnavailable, UnknownException)
 330
 331         /* I guess we could implement decrementer, and may have
 332          * to someday for timekeeping.
 333          */
 334         STD_EXCEPTION(0x900, Decrementer, timer_interrupt)
 335
 336         STD_EXCEPTION(0xa00, Trap_0a, UnknownException)
 337         STD_EXCEPTION(0xb00, Trap_0b, UnknownException)
 338         STD_EXCEPTION(0xc00, SystemCall, UnknownException)
 339         STD_EXCEPTION(0xd00, SingleStep, UnknownException)
 340
 341         STD_EXCEPTION(0xe00, Trap_0e, UnknownException)
 342         STD_EXCEPTION(0xf00, Trap_0f, UnknownException)
 343
 344         STD_EXCEPTION(0x1000, InstructionTLBMiss, UnknownException)
 345         STD_EXCEPTION(0x1100, DataLoadTLBMiss, UnknownException)
 346         STD_EXCEPTION(0x1200, DataStoreTLBMiss, UnknownException)
 347 #ifdef DEBUG
 348         . = 0x1300
 349         /*
 350          * This exception occurs when the program counter matches the
 351          * Instruction Address Breakpoint Register (IABR).
 352          *
 353          * I want the cpu to halt if this occurs so I can hunt around
 354          * with the debugger and look at things.
 355          *
 356          * When DEBUG is defined, both machine check enable (in the MSR)
 357          * and checkstop reset enable (in the reset mode register) are
 358          * turned off and so a checkstop condition will result in the cpu
 359          * halting.
 360          *
 361          * I force the cpu into a checkstop condition by putting an illegal
 362          * instruction here (at least this is the theory).
 363          *
 364          * well - that didnt work, so just do an infinite loop!
 365          */
 366 1:      b       1b
 367 #else
 368         STD_EXCEPTION(0x1300, InstructionBreakpoint, DebugException)
 369 #endif
 370         STD_EXCEPTION(0x1400, SMI, UnknownException)
 371
 372         STD_EXCEPTION(0x1500, Trap_15, UnknownException)
 373         STD_EXCEPTION(0x1600, Trap_16, UnknownException)
 374         STD_EXCEPTION(0x1700, Trap_17, UnknownException)
 375         STD_EXCEPTION(0x1800, Trap_18, UnknownException)
 376         STD_EXCEPTION(0x1900, Trap_19, UnknownException)
 377         STD_EXCEPTION(0x1a00, Trap_1a, UnknownException)
 378         STD_EXCEPTION(0x1b00, Trap_1b, UnknownException)
 379         STD_EXCEPTION(0x1c00, Trap_1c, UnknownException)
 380         STD_EXCEPTION(0x1d00, Trap_1d, UnknownException)
 381         STD_EXCEPTION(0x1e00, Trap_1e, UnknownException)
 382         STD_EXCEPTION(0x1f00, Trap_1f, UnknownException)
 383         STD_EXCEPTION(0x2000, Trap_20, UnknownException)
 384         STD_EXCEPTION(0x2100, Trap_21, UnknownException)
 385         STD_EXCEPTION(0x2200, Trap_22, UnknownException)
 386         STD_EXCEPTION(0x2300, Trap_23, UnknownException)
 387         STD_EXCEPTION(0x2400, Trap_24, UnknownException)
 388         STD_EXCEPTION(0x2500, Trap_25, UnknownException)
 389         STD_EXCEPTION(0x2600, Trap_26, UnknownException)
 390         STD_EXCEPTION(0x2700, Trap_27, UnknownException)
 391         STD_EXCEPTION(0x2800, Trap_28, UnknownException)
 392         STD_EXCEPTION(0x2900, Trap_29, UnknownException)
 393         STD_EXCEPTION(0x2a00, Trap_2a, UnknownException)
 394         STD_EXCEPTION(0x2b00, Trap_2b, UnknownException)
 395         STD_EXCEPTION(0x2c00, Trap_2c, UnknownException)
 396         STD_EXCEPTION(0x2d00, Trap_2d, UnknownException)
 397         STD_EXCEPTION(0x2e00, Trap_2e, UnknownException)
 398         STD_EXCEPTION(0x2f00, Trap_2f, UnknownException)
 399
 400
 401         .globl  _end_of_vectors
 402 _end_of_vectors:
 403
 404         . = 0x3000
 405
 406 /*
 407  * This code finishes saving the registers to the exception frame
 408  * and jumps to the appropriate handler for the exception.
 409  * Register r21 is pointer into trap frame, r1 has new stack pointer.
 410  */
 411         .globl  transfer_to_handler
 412 transfer_to_handler:
 413         stw     r22,_NIP(r21)
 414         lis     r22,MSR_POW@h
 415         andc    r23,r23,r22
 416         stw     r23,_MSR(r21)
 417         SAVE_GPR(7, r21)
 418         SAVE_4GPRS(8, r21)
 419         SAVE_8GPRS(12, r21)
 420         SAVE_8GPRS(24, r21)
 421         mflr    r23
 422         andi.   r24,r23,0x3f00          /* get vector offset */
 423         stw     r24,TRAP(r21)
 424         li      r22,0
 425         stw     r22,RESULT(r21)
 426         lwz     r24,0(r23)              /* virtual address of handler */
 427         lwz     r23,4(r23)              /* where to go when done */
 428         mtspr   SRR0,r24
 429         mtspr   SRR1,r20
 430         mtlr    r23
 431         SYNC
 432         rfi                             /* jump to handler, enable MMU */
 433
 434 int_return:
 435         mfmsr   r28             /* Disable interrupts */
 436         li      r4,0
 437         ori     r4,r4,MSR_EE
 438         andc    r28,r28,r4
 439         SYNC                    /* Some chip revs need this... */
 440         mtmsr   r28
 441         SYNC
 442         lwz     r2,_CTR(r1)
 443         lwz     r0,_LINK(r1)
 444         mtctr   r2
 445         mtlr    r0
 446         lwz     r2,_XER(r1)
 447         lwz     r0,_CCR(r1)
 448         mtspr   XER,r2
 449         mtcrf   0xFF,r0
 450         REST_10GPRS(3, r1)
 451         REST_10GPRS(13, r1)
 452         REST_8GPRS(23, r1)
 453         REST_GPR(31, r1)
 454         lwz     r2,_NIP(r1)     /* Restore environment */
 455         lwz     r0,_MSR(r1)
 456         mtspr   SRR0,r2
 457         mtspr   SRR1,r0
 458         lwz     r0,GPR0(r1)
 459         lwz     r2,GPR2(r1)
 460         lwz     r1,GPR1(r1)
 461         SYNC
 462         rfi
 463 #endif /* !MINIMAL_SPL */
 464
 465 /*
 466  * This code initialises the E300 processor core
 467  * (conforms to PowerPC 603e spec)
 468  * Note: expects original MSR contents to be in r5.
 469  */
 470         .globl  init_e300_core
 471 init_e300_core: /* time t 10 */
 472         /* Initialize machine status; enable machine check interrupt */
 473         /*-----------------------------------------------------------*/
 474
 475         li      r3, MSR_KERNEL                  /* Set ME and RI flags */
 476         rlwimi  r3, r5, 0, 25, 25       /* preserve IP bit set by HRCW */
 477 #ifdef DEBUG
 478         rlwimi  r3, r5, 0, 21, 22   /* debugger might set SE & BE bits */
 479 #endif
 480         SYNC                                            /* Some chip revs need this... */
 481         mtmsr   r3
 482         SYNC
 483         mtspr   SRR1, r3                        /* Make SRR1 match MSR */
 484
 485
 486         lis     r3, CONFIG_SYS_IMMR@h
 487 #if defined(CONFIG_WATCHDOG)
 488         /* Initialise the Watchdog values and reset it (if req) */
 489         /*------------------------------------------------------*/
 490         lis r4, CONFIG_SYS_WATCHDOG_VALUE
 491         ori r4, r4, (SWCRR_SWEN | SWCRR_SWRI | SWCRR_SWPR)
 492         stw r4, SWCRR(r3)
 493
 494         /* and reset it */
 495
 496         li      r4, 0x556C
 497         sth     r4, SWSRR@l(r3)
 498         li      r4, -0x55C7
 499         sth     r4, SWSRR@l(r3)
 500 #else
 501         /* Disable Watchdog  */
 502         /*-------------------*/
 503         lwz r4, SWCRR(r3)
 504         /* Check to see if its enabled for disabling
 505            once disabled by SW you can't re-enable */
 506         andi. r4, r4, 0x4
 507         beq 1f
 508         xor r4, r4, r4
 509         stw r4, SWCRR(r3)
 510 1:
 511 #endif /* CONFIG_WATCHDOG */
 512
 513 #if defined(CONFIG_MASK_AER_AO)
 514         /* Write the Arbiter Event Enable to mask Address Only traps. */
 515         /* This prevents the dcbz instruction from being trapped when */
 516         /* HID0_ABE Address Broadcast Enable is set and the MEMORY    */
 517         /* COHERENCY bit is set in the WIMG bits, which is often      */
 518         /* needed for PCI operation.                                  */
 519         lwz     r4, 0x0808(r3)
 520         rlwinm  r0, r4, 0, ~AER_AO
 521         stw     r0, 0x0808(r3)
 522 #endif /* CONFIG_MASK_AER_AO */
 523
 524         /* Initialize the Hardware Implementation-dependent Registers */
 525         /* HID0 also contains cache control                     */
 526         /* - force invalidation of data and instruction caches  */
 527         /*------------------------------------------------------*/
 528
 529         lis     r3, CONFIG_SYS_HID0_INIT@h
 530         ori     r3, r3, (CONFIG_SYS_HID0_INIT | HID0_ICFI | HID0_DCFI)@l
 531         SYNC
 532         mtspr   HID0, r3
 533
 534         lis     r3, CONFIG_SYS_HID0_FINAL@h
 535         ori     r3, r3, (CONFIG_SYS_HID0_FINAL & ~(HID0_ICFI | HID0_DCFI))@l
 536         SYNC
 537         mtspr   HID0, r3
 538
 539         lis     r3, CONFIG_SYS_HID2@h
 540         ori     r3, r3, CONFIG_SYS_HID2@l
 541         SYNC
 542         mtspr   HID2, r3
 543
 544         /* Done!                                                */
 545         /*------------------------------*/
 546         blr
 547
 548         /* setup_bats - set them up to some initial state */
 549         .globl  setup_bats
 550 setup_bats:
 551         addis   r0, r0, 0x0000
 552
 553         /* IBAT 0 */
 554         addis   r4, r0, CONFIG_SYS_IBAT0L@h
 555         ori     r4, r4, CONFIG_SYS_IBAT0L@l
 556         addis   r3, r0, CONFIG_SYS_IBAT0U@h
 557         ori     r3, r3, CONFIG_SYS_IBAT0U@l
 558         mtspr   IBAT0L, r4
 559         mtspr   IBAT0U, r3
 560
 561         /* DBAT 0 */
 562         addis   r4, r0, CONFIG_SYS_DBAT0L@h
 563         ori     r4, r4, CONFIG_SYS_DBAT0L@l
 564         addis   r3, r0, CONFIG_SYS_DBAT0U@h
 565         ori     r3, r3, CONFIG_SYS_DBAT0U@l
 566         mtspr   DBAT0L, r4
 567         mtspr   DBAT0U, r3
 568
 569         /* IBAT 1 */
 570         addis   r4, r0, CONFIG_SYS_IBAT1L@h
 571         ori     r4, r4, CONFIG_SYS_IBAT1L@l
 572         addis   r3, r0, CONFIG_SYS_IBAT1U@h
 573         ori     r3, r3, CONFIG_SYS_IBAT1U@l
 574         mtspr   IBAT1L, r4
 575         mtspr   IBAT1U, r3
 576
 577         /* DBAT 1 */
 578         addis   r4, r0, CONFIG_SYS_DBAT1L@h
 579         ori     r4, r4, CONFIG_SYS_DBAT1L@l
 580         addis   r3, r0, CONFIG_SYS_DBAT1U@h
 581         ori     r3, r3, CONFIG_SYS_DBAT1U@l
 582         mtspr   DBAT1L, r4
 583         mtspr   DBAT1U, r3
 584
 585         /* IBAT 2 */
 586         addis   r4, r0, CONFIG_SYS_IBAT2L@h
 587         ori     r4, r4, CONFIG_SYS_IBAT2L@l
 588         addis   r3, r0, CONFIG_SYS_IBAT2U@h
 589         ori     r3, r3, CONFIG_SYS_IBAT2U@l
 590         mtspr   IBAT2L, r4
 591         mtspr   IBAT2U, r3
 592
 593         /* DBAT 2 */
 594         addis   r4, r0, CONFIG_SYS_DBAT2L@h
 595         ori     r4, r4, CONFIG_SYS_DBAT2L@l
 596         addis   r3, r0, CONFIG_SYS_DBAT2U@h
 597         ori     r3, r3, CONFIG_SYS_DBAT2U@l
 598         mtspr   DBAT2L, r4
 599         mtspr   DBAT2U, r3
 600
 601         /* IBAT 3 */
 602         addis   r4, r0, CONFIG_SYS_IBAT3L@h
 603         ori     r4, r4, CONFIG_SYS_IBAT3L@l
 604         addis   r3, r0, CONFIG_SYS_IBAT3U@h
 605         ori     r3, r3, CONFIG_SYS_IBAT3U@l
 606         mtspr   IBAT3L, r4
 607         mtspr   IBAT3U, r3
 608
 609         /* DBAT 3 */
 610         addis   r4, r0, CONFIG_SYS_DBAT3L@h
 611         ori     r4, r4, CONFIG_SYS_DBAT3L@l
 612         addis   r3, r0, CONFIG_SYS_DBAT3U@h
 613         ori     r3, r3, CONFIG_SYS_DBAT3U@l
 614         mtspr   DBAT3L, r4
 615         mtspr   DBAT3U, r3
 616
 617 #ifdef CONFIG_HIGH_BATS
 618         /* IBAT 4 */
 619         addis   r4, r0, CONFIG_SYS_IBAT4L@h
 620         ori     r4, r4, CONFIG_SYS_IBAT4L@l
 621         addis   r3, r0, CONFIG_SYS_IBAT4U@h
 622         ori     r3, r3, CONFIG_SYS_IBAT4U@l
 623         mtspr   IBAT4L, r4
 624         mtspr   IBAT4U, r3
 625
 626         /* DBAT 4 */
 627         addis   r4, r0, CONFIG_SYS_DBAT4L@h
 628         ori     r4, r4, CONFIG_SYS_DBAT4L@l
 629         addis   r3, r0, CONFIG_SYS_DBAT4U@h
 630         ori     r3, r3, CONFIG_SYS_DBAT4U@l
 631         mtspr   DBAT4L, r4
 632         mtspr   DBAT4U, r3
 633
 634         /* IBAT 5 */
 635         addis   r4, r0, CONFIG_SYS_IBAT5L@h
 636         ori     r4, r4, CONFIG_SYS_IBAT5L@l
 637         addis   r3, r0, CONFIG_SYS_IBAT5U@h
 638         ori     r3, r3, CONFIG_SYS_IBAT5U@l
 639         mtspr   IBAT5L, r4
 640         mtspr   IBAT5U, r3
 641
 642         /* DBAT 5 */
 643         addis   r4, r0, CONFIG_SYS_DBAT5L@h
 644         ori     r4, r4, CONFIG_SYS_DBAT5L@l
 645         addis   r3, r0, CONFIG_SYS_DBAT5U@h
 646         ori     r3, r3, CONFIG_SYS_DBAT5U@l
 647         mtspr   DBAT5L, r4
 648         mtspr   DBAT5U, r3
 649
 650         /* IBAT 6 */
 651         addis   r4, r0, CONFIG_SYS_IBAT6L@h
 652         ori     r4, r4, CONFIG_SYS_IBAT6L@l
 653         addis   r3, r0, CONFIG_SYS_IBAT6U@h
 654         ori     r3, r3, CONFIG_SYS_IBAT6U@l
 655         mtspr   IBAT6L, r4
 656         mtspr   IBAT6U, r3
 657
 658         /* DBAT 6 */
 659         addis   r4, r0, CONFIG_SYS_DBAT6L@h
 660         ori     r4, r4, CONFIG_SYS_DBAT6L@l
 661         addis   r3, r0, CONFIG_SYS_DBAT6U@h
 662         ori     r3, r3, CONFIG_SYS_DBAT6U@l
 663         mtspr   DBAT6L, r4
 664         mtspr   DBAT6U, r3
 665
 666         /* IBAT 7 */
 667         addis   r4, r0, CONFIG_SYS_IBAT7L@h
 668         ori     r4, r4, CONFIG_SYS_IBAT7L@l
 669         addis   r3, r0, CONFIG_SYS_IBAT7U@h
 670         ori     r3, r3, CONFIG_SYS_IBAT7U@l
 671         mtspr   IBAT7L, r4
 672         mtspr   IBAT7U, r3
 673
 674         /* DBAT 7 */
 675         addis   r4, r0, CONFIG_SYS_DBAT7L@h
 676         ori     r4, r4, CONFIG_SYS_DBAT7L@l
 677         addis   r3, r0, CONFIG_SYS_DBAT7U@h
 678         ori     r3, r3, CONFIG_SYS_DBAT7U@l
 679         mtspr   DBAT7L, r4
 680         mtspr   DBAT7U, r3
 681 #endif
 682
 683         isync
 684
 685         /* invalidate all tlb's
 686          *
 687          * From the 603e User Manual: "The 603e provides the ability to
 688          * invalidate a TLB entry. The TLB Invalidate Entry (tlbie)
 689          * instruction invalidates the TLB entry indexed by the EA, and
 690          * operates on both the instruction and data TLBs simultaneously
 691          * invalidating four TLB entries (both sets in each TLB). The
 692          * index corresponds to bits 15-19 of the EA. To invalidate all
 693          * entries within both TLBs, 32 tlbie instructions should be
 694          * issued, incrementing this field by one each time."
 695          *
 696          * "Note that the tlbia instruction is not implemented on the
 697          * 603e."
 698          *
 699          * bits 15-19 correspond to addresses 0x00000000 to 0x0001F000
 700          * incrementing by 0x1000 each time. The code below is sort of
 701          * based on code in "flush_tlbs" from arch/powerpc/kernel/head.S
 702          *
 703          */
 704         lis     r3, 0
 705         lis     r5, 2
 706
 707 1:
 708         tlbie   r3
 709         addi    r3, r3, 0x1000
 710         cmp     0, 0, r3, r5
 711         blt     1b
 712
 713         blr
 714
 715 /* Cache functions.
 716  *
 717  * Note: requires that all cache bits in
 718  * HID0 are in the low half word.
 719  */
 720 #ifndef MINIMAL_SPL
 721         .globl  icache_enable
 722 icache_enable:
 723         mfspr   r3, HID0
 724         ori     r3, r3, HID0_ICE
 725         li      r4, HID0_ICFI|HID0_ILOCK
 726         andc    r3, r3, r4
 727         ori     r4, r3, HID0_ICFI
 728         isync
 729         mtspr   HID0, r4    /* sets enable and invalidate, clears lock */
 730         isync
 731         mtspr   HID0, r3        /* clears invalidate */
 732         blr
 733
 734         .globl  icache_disable
 735 icache_disable:
 736         mfspr   r3, HID0
 737         lis     r4, 0
 738         ori     r4, r4, HID0_ICE|HID0_ICFI|HID0_ILOCK
 739         andc    r3, r3, r4
 740         isync
 741         mtspr   HID0, r3        /* clears invalidate, enable and lock */
 742         blr
 743
 744         .globl  icache_status
 745 icache_status:
 746         mfspr   r3, HID0
 747         rlwinm  r3, r3, (31 - HID0_ICE_SHIFT + 1), 31, 31
 748         blr
 749 #endif  /* !MINIMAL_SPL */
 750
 751         .globl  dcache_enable
 752 dcache_enable:
 753         mfspr   r3, HID0
 754         li      r5, HID0_DCFI|HID0_DLOCK
 755         andc    r3, r3, r5
 756         ori     r3, r3, HID0_DCE
 757         sync
 758         mtspr   HID0, r3                /* enable, no invalidate */
 759         blr
 760
 761         .globl  dcache_disable
 762 dcache_disable:
 763         mflr    r4
 764         bl      flush_dcache            /* uses r3 and r5 */
 765         mfspr   r3, HID0
 766         li      r5, HID0_DCE|HID0_DLOCK
 767         andc    r3, r3, r5
 768         ori     r5, r3, HID0_DCFI
 769         sync
 770         mtspr   HID0, r5        /* sets invalidate, clears enable and lock */
 771         sync
 772         mtspr   HID0, r3        /* clears invalidate */
 773         mtlr    r4
 774         blr
 775
 776         .globl  dcache_status
 777 dcache_status:
 778         mfspr   r3, HID0
 779         rlwinm  r3, r3, (31 - HID0_DCE_SHIFT + 1), 31, 31
 780         blr
 781
 782         .globl  flush_dcache
 783 flush_dcache:
 784         lis     r3, 0
 785         lis     r5, CONFIG_SYS_CACHELINE_SIZE
 786 1:      cmp     0, 1, r3, r5
 787         bge     2f
 788         lwz     r5, 0(r3)
 789         lis     r5, CONFIG_SYS_CACHELINE_SIZE
 790         addi    r3, r3, 0x4
 791         b       1b
 792 2:      blr
 793
 794 /*-------------------------------------------------------------------*/
 795
 796 /*
 797  * void relocate_code (addr_sp, gd, addr_moni)
 798  *
 799  * This "function" does not return, instead it continues in RAM
 800  * after relocating the monitor code.
 801  *
 802  * r3 = dest
 803  * r4 = src
 804  * r5 = length in bytes
 805  * r6 = cachelinesize
 806  */
 807         .globl  relocate_code
 808 relocate_code:
 809         mr      r1,  r3         /* Set new stack pointer        */
 810         mr      r9,  r4         /* Save copy of Global Data pointer */
 811         mr      r10, r5         /* Save copy of Destination Address */
 812
 813         GET_GOT
 814         mr      r3,  r5                         /* Destination Address */
 815         lis     r4, CONFIG_SYS_MONITOR_BASE@h           /* Source      Address */
 816         ori     r4, r4, CONFIG_SYS_MONITOR_BASE@l
 817         lwz     r5, GOT(__bss_start)
 818         sub     r5, r5, r4
 819         li      r6, CONFIG_SYS_CACHELINE_SIZE           /* Cache Line Size */
 820
 821         /*
 822          * Fix GOT pointer:
 823          *
 824          * New GOT-PTR = (old GOT-PTR - CONFIG_SYS_MONITOR_BASE)
 825          *              + Destination Address
 826          *
 827          * Offset:
 828          */
 829         sub     r15, r10, r4
 830
 831         /* First our own GOT */
 832         add     r12, r12, r15
 833         /* then the one used by the C code */
 834         add     r30, r30, r15
 835
 836         /*
 837          * Now relocate code
 838          */
 839
 840         cmplw   cr1,r3,r4
 841         addi    r0,r5,3
 842         srwi.   r0,r0,2
 843         beq     cr1,4f          /* In place copy is not necessary */
 844         beq     7f              /* Protect against 0 count        */
 845         mtctr   r0
 846         bge     cr1,2f
 847         la      r8,-4(r4)
 848         la      r7,-4(r3)
 849
 850         /* copy */
 851 1:      lwzu    r0,4(r8)
 852         stwu    r0,4(r7)
 853         bdnz    1b
 854
 855         addi    r0,r5,3
 856         srwi.   r0,r0,2
 857         mtctr   r0
 858         la      r8,-4(r4)
 859         la      r7,-4(r3)
 860
 861         /* and compare */
 862 20:     lwzu    r20,4(r8)
 863         lwzu    r21,4(r7)
 864         xor. r22, r20, r21
 865         bne  30f
 866         bdnz    20b
 867         b 4f
 868
 869         /* compare failed */
 870 30:     li r3, 0
 871         blr
 872
 873 2:      slwi    r0,r0,2 /* re copy in reverse order ... y do we needed it? */
 874         add     r8,r4,r0
 875         add     r7,r3,r0
 876 3:      lwzu    r0,-4(r8)
 877         stwu    r0,-4(r7)
 878         bdnz    3b
 879
 880 /*
 881  * Now flush the cache: note that we must start from a cache aligned
 882  * address. Otherwise we might miss one cache line.
 883  */
 884 4:      cmpwi   r6,0
 885         add     r5,r3,r5
 886         beq     7f              /* Always flush prefetch queue in any case */
 887         subi    r0,r6,1
 888         andc    r3,r3,r0
 889         mr      r4,r3
 890 5:      dcbst   0,r4
 891         add     r4,r4,r6
 892         cmplw   r4,r5
 893         blt     5b
 894         sync                    /* Wait for all dcbst to complete on bus */
 895         mr      r4,r3
 896 6:      icbi    0,r4
 897         add     r4,r4,r6
 898         cmplw   r4,r5
 899         blt     6b
 900 7:      sync                    /* Wait for all icbi to complete on bus */
 901         isync
 902
 903 /*
 904  * We are done. Do not return, instead branch to second part of board
 905  * initialization, now running from RAM.
 906  */
 907         addi    r0, r10, in_ram - _start + EXC_OFF_SYS_RESET
 908         mtlr    r0
 909         blr
 910
 911 in_ram:
 912
 913         /*
 914          * Relocation Function, r12 point to got2+0x8000
 915          *
 916          * Adjust got2 pointers, no need to check for 0, this code
 917          * already puts a few entries in the table.
 918          */
 919         li      r0,__got2_entries@sectoff@l
 920         la      r3,GOT(_GOT2_TABLE_)
 921         lwz     r11,GOT(_GOT2_TABLE_)
 922         mtctr   r0
 923         sub     r11,r3,r11
 924         addi    r3,r3,-4
 925 1:      lwzu    r0,4(r3)
 926         cmpwi   r0,0
 927         beq-    2f
 928         add     r0,r0,r11
 929         stw     r0,0(r3)
 930 2:      bdnz    1b
 931
 932 #ifndef MINIMAL_SPL
 933         /*
 934          * Now adjust the fixups and the pointers to the fixups
 935          * in case we need to move ourselves again.
 936          */
 937         li      r0,__fixup_entries@sectoff@l
 938         lwz     r3,GOT(_FIXUP_TABLE_)
 939         cmpwi   r0,0
 940         mtctr   r0
 941         addi    r3,r3,-4
 942         beq     4f
 943 3:      lwzu    r4,4(r3)
 944         lwzux   r0,r4,r11
 945         cmpwi   r0,0
 946         add     r0,r0,r11
 947         stw     r4,0(r3)
 948         beq-    5f
 949         stw     r0,0(r4)
 950 5:      bdnz    3b
 951 4:
 952 #endif
 953
 954 clear_bss:
 955         /*
 956          * Now clear BSS segment
 957          */
 958         lwz     r3,GOT(__bss_start)
 959         lwz     r4,GOT(__bss_end)
 960
 961         cmplw   0, r3, r4
 962         beq     6f
 963
 964         li      r0, 0
 965 5:
 966         stw     r0, 0(r3)
 967         addi    r3, r3, 4
 968         cmplw   0, r3, r4
 969         bne     5b
 970 6:
 971
 972         mr      r3, r9          /* Global Data pointer          */
 973         mr      r4, r10         /* Destination Address          */
 974         bl      board_init_r
 975
 976 #ifndef MINIMAL_SPL
 977         /*
 978          * Copy exception vector code to low memory
 979          *
 980          * r3: dest_addr
 981          * r7: source address, r8: end address, r9: target address
 982          */
 983         .globl  trap_init
 984 trap_init:
 985         mflr    r4              /* save link register */
 986         GET_GOT
 987         lwz     r7, GOT(_start)
 988         lwz     r8, GOT(_end_of_vectors)
 989
 990         li      r9, 0x100       /* reset vector always at 0x100 */
 991
 992         cmplw   0, r7, r8
 993         bgelr                   /* return if r7>=r8 - just in case */
 994 1:
 995         lwz     r0, 0(r7)
 996         stw     r0, 0(r9)
 997         addi    r7, r7, 4
 998         addi    r9, r9, 4
 999         cmplw   0, r7, r8
1000         bne     1b
1001
1002         /*
1003          * relocate `hdlr' and `int_return' entries
1004          */
1005         li      r7, .L_MachineCheck - _start + EXC_OFF_SYS_RESET
1006         li      r8, Alignment - _start + EXC_OFF_SYS_RESET
1007 2:
1008         bl      trap_reloc
1009         addi    r7, r7, 0x100           /* next exception vector */
1010         cmplw   0, r7, r8
1011         blt     2b
1012
1013         li      r7, .L_Alignment - _start + EXC_OFF_SYS_RESET
1014         bl      trap_reloc
1015
1016         li      r7, .L_ProgramCheck - _start + EXC_OFF_SYS_RESET
1017         bl      trap_reloc
1018
1019         li      r7, .L_FPUnavailable - _start + EXC_OFF_SYS_RESET
1020         li      r8, SystemCall - _start + EXC_OFF_SYS_RESET
1021 3:
1022         bl      trap_reloc
1023         addi    r7, r7, 0x100           /* next exception vector */
1024         cmplw   0, r7, r8
1025         blt     3b
1026
1027         li      r7, .L_SingleStep - _start + EXC_OFF_SYS_RESET
1028         li      r8, _end_of_vectors - _start + EXC_OFF_SYS_RESET
1029 4:
1030         bl      trap_reloc
1031         addi    r7, r7, 0x100           /* next exception vector */
1032         cmplw   0, r7, r8
1033         blt     4b
1034
1035         mfmsr   r3                      /* now that the vectors have */
1036         lis     r7, MSR_IP@h            /* relocated into low memory */
1037         ori     r7, r7, MSR_IP@l        /* MSR[IP] can be turned off */
1038         andc    r3, r3, r7              /* (if it was on) */
1039         SYNC                            /* Some chip revs need this... */
1040         mtmsr   r3
1041         SYNC
1042
1043         mtlr    r4                      /* restore link register    */
1044         blr
1045
1046 #endif /* !MINIMAL_SPL */
1047
1048 #ifdef CONFIG_SYS_INIT_RAM_LOCK
1049 lock_ram_in_cache:
1050         /* Allocate Initial RAM in data cache.
1051          */
1052         lis     r3, (CONFIG_SYS_INIT_RAM_ADDR & ~31)@h
1053         ori     r3, r3, (CONFIG_SYS_INIT_RAM_ADDR & ~31)@l
1054         li      r4, ((CONFIG_SYS_INIT_RAM_SIZE & ~31) + \
1055                      (CONFIG_SYS_INIT_RAM_ADDR & 31) + 31) / 32
1056         mtctr   r4
1057 1:
1058         dcbz    r0, r3
1059         addi    r3, r3, 32
1060         bdnz    1b
1061
1062         /* Lock the data cache */
1063         mfspr   r0, HID0
1064         ori     r0, r0, HID0_DLOCK
1065         sync
1066         mtspr   HID0, r0
1067         sync
1068         blr
1069
1070 #ifndef MINIMAL_SPL
1071 .globl unlock_ram_in_cache
1072 unlock_ram_in_cache:
1073         /* invalidate the INIT_RAM section */
1074         lis     r3, (CONFIG_SYS_INIT_RAM_ADDR & ~31)@h
1075         ori     r3, r3, (CONFIG_SYS_INIT_RAM_ADDR & ~31)@l
1076         li      r4, ((CONFIG_SYS_INIT_RAM_SIZE & ~31) + \
1077                      (CONFIG_SYS_INIT_RAM_ADDR & 31) + 31) / 32
1078         mtctr   r4
1079 1:      icbi    r0, r3
1080         dcbi    r0, r3
1081         addi    r3, r3, 32
1082         bdnz    1b
1083         sync                    /* Wait for all icbi to complete on bus */
1084         isync
1085
1086         /* Unlock the data cache and invalidate it */
1087         mfspr   r3, HID0
1088         li      r5, HID0_DLOCK|HID0_DCFI
1089         andc    r3, r3, r5              /* no invalidate, unlock */
1090         ori     r5, r3, HID0_DCFI       /* invalidate, unlock */
1091         sync
1092         mtspr   HID0, r5                /* invalidate, unlock */
1093         sync
1094         mtspr   HID0, r3                /* no invalidate, unlock */
1095         blr
1096 #endif /* !MINIMAL_SPL */
1097 #endif /* CONFIG_SYS_INIT_RAM_LOCK */
1098
1099 #ifdef CONFIG_SYS_FLASHBOOT
1100 map_flash_by_law1:
1101         /* When booting from ROM (Flash or EPROM), clear the  */
1102         /* Address Mask in OR0 so ROM appears everywhere      */
1103         /*----------------------------------------------------*/
1104         lis     r3, (CONFIG_SYS_IMMR)@h  /* r3 <= CONFIG_SYS_IMMR    */
1105         lwz     r4, OR0@l(r3)
1106         li      r5, 0x7fff        /* r5 <= 0x00007FFFF */
1107         and     r4, r4, r5
1108         stw     r4, OR0@l(r3)     /* OR0 <= OR0 & 0x00007FFFF */
1109
1110         /* As MPC8349E User's Manual presented, when RCW[BMS] is set to 0,
1111          * system will boot from 0x0000_0100, and the LBLAWBAR0[BASE_ADDR]
1112          * reset value is 0x00000; when RCW[BMS] is set to 1, system will boot
1113          * from 0xFFF0_0100, and the LBLAWBAR0[BASE_ADDR] reset value is
1114          * 0xFF800.  From the hard resetting to here, the processor fetched and
1115          * executed the instructions one by one.  There is not absolutely
1116          * jumping happened.  Laterly, the u-boot code has to do an absolutely
1117          * jumping to tell the CPU instruction fetching component what the
1118          * u-boot TEXT base address is.  Because the TEXT base resides in the
1119          * boot ROM memory space, to garantee the code can run smoothly after
1120          * that jumping, we must map in the entire boot ROM by Local Access
1121          * Window.  Sometimes, we desire an non-0x00000 or non-0xFF800 starting
1122          * address for boot ROM, such as 0xFE000000.  In this case, the default
1123          * LBIU Local Access Widow 0 will not cover this memory space.  So, we
1124          * need another window to map in it.
1125          */
1126         lis r4, (CONFIG_SYS_FLASH_BASE)@h
1127         ori r4, r4, (CONFIG_SYS_FLASH_BASE)@l
1128         stw r4, LBLAWBAR1(r3) /* LBLAWBAR1 <= CONFIG_SYS_FLASH_BASE */
1129
1130         /* Store 0x80000012 + log2(CONFIG_SYS_FLASH_SIZE) into LBLAWAR1 */
1131         lis r4, (0x80000012)@h
1132         ori r4, r4, (0x80000012)@l
1133         li r5, CONFIG_SYS_FLASH_SIZE
1134 1:      srawi. r5, r5, 1        /* r5 = r5 >> 1 */
1135         addi r4, r4, 1
1136         bne 1b
1137
1138         stw r4, LBLAWAR1(r3) /* LBLAWAR1 <= 8MB Flash Size */
1139         /* Wait for HW to catch up */
1140         lwz r4, LBLAWAR1(r3)
1141         twi 0,r4,0
1142         isync
1143         blr
1144
1145         /* Though all the LBIU Local Access Windows and LBC Banks will be
1146          * initialized in the C code, we'd better configure boot ROM's
1147          * window 0 and bank 0 correctly at here.
1148          */
1149 remap_flash_by_law0:
1150         /* Initialize the BR0 with the boot ROM starting address. */
1151         lwz r4, BR0(r3)
1152         li  r5, 0x7FFF
1153         and r4, r4, r5
1154         lis r5, (CONFIG_SYS_FLASH_BASE & 0xFFFF8000)@h
1155         ori r5, r5, (CONFIG_SYS_FLASH_BASE & 0xFFFF8000)@l
1156         or  r5, r5, r4
1157         stw r5, BR0(r3) /* r5 <= (CONFIG_SYS_FLASH_BASE & 0xFFFF8000) | (BR0 & 0x00007FFF) */
1158
1159         lwz r4, OR0(r3)
1160         lis r5, ~((CONFIG_SYS_FLASH_SIZE << 4) - 1)
1161         or r4, r4, r5
1162         stw r4, OR0(r3)
1163
1164         lis r4, (CONFIG_SYS_FLASH_BASE)@h
1165         ori r4, r4, (CONFIG_SYS_FLASH_BASE)@l
1166         stw r4, LBLAWBAR0(r3) /* LBLAWBAR0 <= CONFIG_SYS_FLASH_BASE */
1167
1168         /* Store 0x80000012 + log2(CONFIG_SYS_FLASH_SIZE) into LBLAWAR0 */
1169         lis r4, (0x80000012)@h
1170         ori r4, r4, (0x80000012)@l
1171         li r5, CONFIG_SYS_FLASH_SIZE
1172 1:      srawi. r5, r5, 1 /* r5 = r5 >> 1 */
1173         addi r4, r4, 1
1174         bne 1b
1175         stw r4, LBLAWAR0(r3) /* LBLAWAR0 <= Flash Size */
1176
1177
1178         xor r4, r4, r4
1179         stw r4, LBLAWBAR1(r3)
1180         stw r4, LBLAWAR1(r3) /* Off LBIU LAW1 */
1181         /* Wait for HW to catch up */
1182         lwz r4, LBLAWAR1(r3)
1183         twi 0,r4,0
1184         isync
1185         blr
1186 #endif /* CONFIG_SYS_FLASHBOOT */