arch/powerpc/cpu/mpc85xx/Kconfig

   1 menu "mpc85xx CPU"
   2         depends on MPC85xx
   3
   4 config SYS_CPU
   5         default "mpc85xx"
   6
   7 choice
   8         prompt "Target select"
   9         optional
  10
  11 config TARGET_SBC8548
  12         bool "Support sbc8548"
  13         select ARCH_MPC8548
  14
  15 config TARGET_SOCRATES
  16         bool "Support socrates"
  17         select ARCH_MPC8544
  18
  19 config TARGET_B4420QDS
  20         bool "Support B4420QDS"
  21         select ARCH_B4420
  22         select SUPPORT_SPL
  23         select PHYS_64BIT
  24
  25 config TARGET_B4860QDS
  26         bool "Support B4860QDS"
  27         select ARCH_B4860
  28         select BOARD_LATE_INIT if CHAIN_OF_TRUST
  29         select SUPPORT_SPL
  30         select PHYS_64BIT
  31
  32 config TARGET_BSC9131RDB
  33         bool "Support BSC9131RDB"
  34         select ARCH_BSC9131
  35         select SUPPORT_SPL
  36         select BOARD_EARLY_INIT_F
  37
  38 config TARGET_BSC9132QDS
  39         bool "Support BSC9132QDS"
  40         select ARCH_BSC9132
  41         select BOARD_LATE_INIT if CHAIN_OF_TRUST
  42         select SUPPORT_SPL
  43         select BOARD_EARLY_INIT_F
  44
  45 config TARGET_C29XPCIE
  46         bool "Support C29XPCIE"
  47         select ARCH_C29X
  48         select BOARD_LATE_INIT if CHAIN_OF_TRUST
  49         select SUPPORT_SPL
  50         select SUPPORT_TPL
  51         select PHYS_64BIT
  52
  53 config TARGET_P3041DS
  54         bool "Support P3041DS"
  55         select PHYS_64BIT
  56         select ARCH_P3041
  57         select BOARD_LATE_INIT if CHAIN_OF_TRUST
  58
  59 config TARGET_P4080DS
  60         bool "Support P4080DS"
  61         select PHYS_64BIT
  62         select ARCH_P4080
  63         select BOARD_LATE_INIT if CHAIN_OF_TRUST
  64
  65 config TARGET_P5020DS
  66         bool "Support P5020DS"
  67         select PHYS_64BIT
  68         select ARCH_P5020
  69         select BOARD_LATE_INIT if CHAIN_OF_TRUST
  70
  71 config TARGET_P5040DS
  72         bool "Support P5040DS"
  73         select PHYS_64BIT
  74         select ARCH_P5040
  75         select BOARD_LATE_INIT if CHAIN_OF_TRUST
  76
  77 config TARGET_MPC8536DS
  78         bool "Support MPC8536DS"
  79         select ARCH_MPC8536
  80 # Use DDR3 controller with DDR2 DIMMs on this board
  81         select SYS_FSL_DDRC_GEN3
  82
  83 config TARGET_MPC8540ADS
  84         bool "Support MPC8540ADS"
  85         select ARCH_MPC8540
  86
  87 config TARGET_MPC8541CDS
  88         bool "Support MPC8541CDS"
  89         select ARCH_MPC8541
  90
  91 config TARGET_MPC8544DS
  92         bool "Support MPC8544DS"
  93         select ARCH_MPC8544
  94
  95 config TARGET_MPC8548CDS
  96         bool "Support MPC8548CDS"
  97         select ARCH_MPC8548
  98
  99 config TARGET_MPC8555CDS
 100         bool "Support MPC8555CDS"
 101         select ARCH_MPC8555
 102
 103 config TARGET_MPC8560ADS
 104         bool "Support MPC8560ADS"
 105         select ARCH_MPC8560
 106
 107 config TARGET_MPC8568MDS
 108         bool "Support MPC8568MDS"
 109         select ARCH_MPC8568
 110
 111 config TARGET_MPC8569MDS
 112         bool "Support MPC8569MDS"
 113         select ARCH_MPC8569
 114
 115 config TARGET_MPC8572DS
 116         bool "Support MPC8572DS"
 117         select ARCH_MPC8572
 118 # Use DDR3 controller with DDR2 DIMMs on this board
 119         select SYS_FSL_DDRC_GEN3
 120
 121 config TARGET_P1010RDB_PA
 122         bool "Support P1010RDB_PA"
 123         select ARCH_P1010
 124         select BOARD_LATE_INIT if CHAIN_OF_TRUST
 125         select SUPPORT_SPL
 126         select SUPPORT_TPL
 127
 128 config TARGET_P1010RDB_PB
 129         bool "Support P1010RDB_PB"
 130         select ARCH_P1010
 131         select BOARD_LATE_INIT if CHAIN_OF_TRUST
 132         select SUPPORT_SPL
 133         select SUPPORT_TPL
 134
 135 config TARGET_P1022DS
 136         bool "Support P1022DS"
 137         select ARCH_P1022
 138         select SUPPORT_SPL
 139         select SUPPORT_TPL
 140
 141 config TARGET_P1023RDB
 142         bool "Support P1023RDB"
 143         select ARCH_P1023
 144
 145 config TARGET_P1020MBG
 146         bool "Support P1020MBG-PC"
 147         select SUPPORT_SPL
 148         select SUPPORT_TPL
 149         select ARCH_P1020
 150
 151 config TARGET_P1020RDB_PC
 152         bool "Support P1020RDB-PC"
 153         select SUPPORT_SPL
 154         select SUPPORT_TPL
 155         select ARCH_P1020
 156
 157 config TARGET_P1020RDB_PD
 158         bool "Support P1020RDB-PD"
 159         select SUPPORT_SPL
 160         select SUPPORT_TPL
 161         select ARCH_P1020
 162
 163 config TARGET_P1020UTM
 164         bool "Support P1020UTM"
 165         select SUPPORT_SPL
 166         select SUPPORT_TPL
 167         select ARCH_P1020
 168
 169 config TARGET_P1021RDB
 170         bool "Support P1021RDB"
 171         select SUPPORT_SPL
 172         select SUPPORT_TPL
 173         select ARCH_P1021
 174
 175 config TARGET_P1024RDB
 176         bool "Support P1024RDB"
 177         select SUPPORT_SPL
 178         select SUPPORT_TPL
 179         select ARCH_P1024
 180
 181 config TARGET_P1025RDB
 182         bool "Support P1025RDB"
 183         select SUPPORT_SPL
 184         select SUPPORT_TPL
 185         select ARCH_P1025
 186
 187 config TARGET_P2020RDB
 188         bool "Support P2020RDB-PC"
 189         select SUPPORT_SPL
 190         select SUPPORT_TPL
 191         select ARCH_P2020
 192
 193 config TARGET_P1_TWR
 194         bool "Support p1_twr"
 195         select ARCH_P1025
 196
 197 config TARGET_P2041RDB
 198         bool "Support P2041RDB"
 199         select ARCH_P2041
 200         select BOARD_LATE_INIT if CHAIN_OF_TRUST
 201         select PHYS_64BIT
 202
 203 config TARGET_QEMU_PPCE500
 204         bool "Support qemu-ppce500"
 205         select ARCH_QEMU_E500
 206         select PHYS_64BIT
 207
 208 config TARGET_T1024QDS
 209         bool "Support T1024QDS"
 210         select ARCH_T1024
 211         select BOARD_LATE_INIT if CHAIN_OF_TRUST
 212         select SUPPORT_SPL
 213         select PHYS_64BIT
 214
 215 config TARGET_T1023RDB
 216         bool "Support T1023RDB"
 217         select ARCH_T1023
 218         select BOARD_LATE_INIT if CHAIN_OF_TRUST
 219         select SUPPORT_SPL
 220         select PHYS_64BIT
 221
 222 config TARGET_T1024RDB
 223         bool "Support T1024RDB"
 224         select ARCH_T1024
 225         select BOARD_LATE_INIT if CHAIN_OF_TRUST
 226         select SUPPORT_SPL
 227         select PHYS_64BIT
 228
 229 config TARGET_T1040QDS
 230         bool "Support T1040QDS"
 231         select ARCH_T1040
 232         select BOARD_LATE_INIT if CHAIN_OF_TRUST
 233         select PHYS_64BIT
 234
 235 config TARGET_T1040RDB
 236         bool "Support T1040RDB"
 237         select ARCH_T1040
 238         select BOARD_LATE_INIT if CHAIN_OF_TRUST
 239         select SUPPORT_SPL
 240         select PHYS_64BIT
 241
 242 config TARGET_T1040D4RDB
 243         bool "Support T1040D4RDB"
 244         select ARCH_T1040
 245         select BOARD_LATE_INIT if CHAIN_OF_TRUST
 246         select SUPPORT_SPL
 247         select PHYS_64BIT
 248
 249 config TARGET_T1042RDB
 250         bool "Support T1042RDB"
 251         select ARCH_T1042
 252         select BOARD_LATE_INIT if CHAIN_OF_TRUST
 253         select SUPPORT_SPL
 254         select PHYS_64BIT
 255
 256 config TARGET_T1042D4RDB
 257         bool "Support T1042D4RDB"
 258         select ARCH_T1042
 259         select BOARD_LATE_INIT if CHAIN_OF_TRUST
 260         select SUPPORT_SPL
 261         select PHYS_64BIT
 262
 263 config TARGET_T1042RDB_PI
 264         bool "Support T1042RDB_PI"
 265         select ARCH_T1042
 266         select BOARD_LATE_INIT if CHAIN_OF_TRUST
 267         select SUPPORT_SPL
 268         select PHYS_64BIT
 269
 270 config TARGET_T2080QDS
 271         bool "Support T2080QDS"
 272         select ARCH_T2080
 273         select BOARD_LATE_INIT if CHAIN_OF_TRUST
 274         select SUPPORT_SPL
 275         select PHYS_64BIT
 276
 277 config TARGET_T2080RDB
 278         bool "Support T2080RDB"
 279         select ARCH_T2080
 280         select BOARD_LATE_INIT if CHAIN_OF_TRUST
 281         select SUPPORT_SPL
 282         select PHYS_64BIT
 283
 284 config TARGET_T2081QDS
 285         bool "Support T2081QDS"
 286         select ARCH_T2081
 287         select SUPPORT_SPL
 288         select PHYS_64BIT
 289
 290 config TARGET_T4160QDS
 291         bool "Support T4160QDS"
 292         select ARCH_T4160
 293         select BOARD_LATE_INIT if CHAIN_OF_TRUST
 294         select SUPPORT_SPL
 295         select PHYS_64BIT
 296
 297 config TARGET_T4160RDB
 298         bool "Support T4160RDB"
 299         select ARCH_T4160
 300         select SUPPORT_SPL
 301         select PHYS_64BIT
 302
 303 config TARGET_T4240QDS
 304         bool "Support T4240QDS"
 305         select ARCH_T4240
 306         select BOARD_LATE_INIT if CHAIN_OF_TRUST
 307         select SUPPORT_SPL
 308         select PHYS_64BIT
 309
 310 config TARGET_T4240RDB
 311         bool "Support T4240RDB"
 312         select ARCH_T4240
 313         select SUPPORT_SPL
 314         select PHYS_64BIT
 315
 316 config TARGET_CONTROLCENTERD
 317         bool "Support controlcenterd"
 318         select ARCH_P1022
 319
 320 config TARGET_KMP204X
 321         bool "Support kmp204x"
 322         select ARCH_P2041
 323         select PHYS_64BIT
 324
 325 config TARGET_XPEDITE520X
 326         bool "Support xpedite520x"
 327         select ARCH_MPC8548
 328
 329 config TARGET_XPEDITE537X
 330         bool "Support xpedite537x"
 331         select ARCH_MPC8572
 332 # Use DDR3 controller with DDR2 DIMMs on this board
 333         select SYS_FSL_DDRC_GEN3
 334
 335 config TARGET_XPEDITE550X
 336         bool "Support xpedite550x"
 337         select ARCH_P2020
 338
 339 config TARGET_UCP1020
 340         bool "Support uCP1020"
 341         select ARCH_P1020
 342
 343 config TARGET_CYRUS_P5020
 344         bool "Support Varisys Cyrus P5020"
 345         select ARCH_P5020
 346         select PHYS_64BIT
 347
 348 config TARGET_CYRUS_P5040
 349          bool "Support Varisys Cyrus P5040"
 350         select ARCH_P5040
 351         select PHYS_64BIT
 352
 353 endchoice
 354
 355 config ARCH_B4420
 356         bool
 357         select E500MC
 358         select E6500
 359         select FSL_LAW
 360         select SYS_FSL_DDR_VER_47
 361         select SYS_FSL_ERRATUM_A004477
 362         select SYS_FSL_ERRATUM_A005871
 363         select SYS_FSL_ERRATUM_A006379
 364         select SYS_FSL_ERRATUM_A006384
 365         select SYS_FSL_ERRATUM_A006475
 366         select SYS_FSL_ERRATUM_A006593
 367         select SYS_FSL_ERRATUM_A007075
 368         select SYS_FSL_ERRATUM_A007186
 369         select SYS_FSL_ERRATUM_A007212
 370         select SYS_FSL_ERRATUM_A009942
 371         select SYS_FSL_HAS_DDR3
 372         select SYS_FSL_HAS_SEC
 373         select SYS_FSL_QORIQ_CHASSIS2
 374         select SYS_FSL_SEC_BE
 375         select SYS_FSL_SEC_COMPAT_4
 376         select SYS_PPC64
 377         select FSL_IFC
 378
 379 config ARCH_B4860
 380         bool
 381         select E500MC
 382         select E6500
 383         select FSL_LAW
 384         select SYS_FSL_DDR_VER_47
 385         select SYS_FSL_ERRATUM_A004477
 386         select SYS_FSL_ERRATUM_A005871
 387         select SYS_FSL_ERRATUM_A006379
 388         select SYS_FSL_ERRATUM_A006384
 389         select SYS_FSL_ERRATUM_A006475
 390         select SYS_FSL_ERRATUM_A006593
 391         select SYS_FSL_ERRATUM_A007075
 392         select SYS_FSL_ERRATUM_A007186
 393         select SYS_FSL_ERRATUM_A007212
 394         select SYS_FSL_ERRATUM_A007907
 395         select SYS_FSL_ERRATUM_A009942
 396         select SYS_FSL_HAS_DDR3
 397         select SYS_FSL_HAS_SEC
 398         select SYS_FSL_QORIQ_CHASSIS2
 399         select SYS_FSL_SEC_BE
 400         select SYS_FSL_SEC_COMPAT_4
 401         select SYS_PPC64
 402         select FSL_IFC
 403
 404 config ARCH_BSC9131
 405         bool
 406         select FSL_LAW
 407         select SYS_FSL_DDR_VER_44
 408         select SYS_FSL_ERRATUM_A004477
 409         select SYS_FSL_ERRATUM_A005125
 410         select SYS_FSL_ERRATUM_ESDHC111
 411         select SYS_FSL_HAS_DDR3
 412         select SYS_FSL_HAS_SEC
 413         select SYS_FSL_SEC_BE
 414         select SYS_FSL_SEC_COMPAT_4
 415         select FSL_IFC
 416
 417 config ARCH_BSC9132
 418         bool
 419         select FSL_LAW
 420         select SYS_FSL_DDR_VER_46
 421         select SYS_FSL_ERRATUM_A004477
 422         select SYS_FSL_ERRATUM_A005125
 423         select SYS_FSL_ERRATUM_A005434
 424         select SYS_FSL_ERRATUM_ESDHC111
 425         select SYS_FSL_ERRATUM_I2C_A004447
 426         select SYS_FSL_ERRATUM_IFC_A002769
 427         select SYS_FSL_HAS_DDR3
 428         select SYS_FSL_HAS_SEC
 429         select SYS_FSL_SEC_BE
 430         select SYS_FSL_SEC_COMPAT_4
 431         select SYS_PPC_E500_USE_DEBUG_TLB
 432         select FSL_IFC
 433
 434 config ARCH_C29X
 435         bool
 436         select FSL_LAW
 437         select SYS_FSL_DDR_VER_46
 438         select SYS_FSL_ERRATUM_A005125
 439         select SYS_FSL_ERRATUM_ESDHC111
 440         select SYS_FSL_HAS_DDR3
 441         select SYS_FSL_HAS_SEC
 442         select SYS_FSL_SEC_BE
 443         select SYS_FSL_SEC_COMPAT_6
 444         select SYS_PPC_E500_USE_DEBUG_TLB
 445         select FSL_IFC
 446
 447 config ARCH_MPC8536
 448         bool
 449         select FSL_LAW
 450         select SYS_FSL_ERRATUM_A004508
 451         select SYS_FSL_ERRATUM_A005125
 452         select SYS_FSL_HAS_DDR2
 453         select SYS_FSL_HAS_DDR3
 454         select SYS_FSL_HAS_SEC
 455         select SYS_FSL_SEC_BE
 456         select SYS_FSL_SEC_COMPAT_2
 457         select SYS_PPC_E500_USE_DEBUG_TLB
 458         select FSL_ELBC
 459
 460 config ARCH_MPC8540
 461         bool
 462         select FSL_LAW
 463         select SYS_FSL_HAS_DDR1
 464
 465 config ARCH_MPC8541
 466         bool
 467         select FSL_LAW
 468         select SYS_FSL_HAS_DDR1
 469         select SYS_FSL_HAS_SEC
 470         select SYS_FSL_SEC_BE
 471         select SYS_FSL_SEC_COMPAT_2
 472
 473 config ARCH_MPC8544
 474         bool
 475         select FSL_LAW
 476         select SYS_FSL_ERRATUM_A005125
 477         select SYS_FSL_HAS_DDR2
 478         select SYS_FSL_HAS_SEC
 479         select SYS_FSL_SEC_BE
 480         select SYS_FSL_SEC_COMPAT_2
 481         select SYS_PPC_E500_USE_DEBUG_TLB
 482         select FSL_ELBC
 483
 484 config ARCH_MPC8548
 485         bool
 486         select FSL_LAW
 487         select SYS_FSL_ERRATUM_A005125
 488         select SYS_FSL_ERRATUM_NMG_DDR120
 489         select SYS_FSL_ERRATUM_NMG_LBC103
 490         select SYS_FSL_ERRATUM_NMG_ETSEC129
 491         select SYS_FSL_ERRATUM_I2C_A004447
 492         select SYS_FSL_HAS_DDR2
 493         select SYS_FSL_HAS_DDR1
 494         select SYS_FSL_HAS_SEC
 495         select SYS_FSL_SEC_BE
 496         select SYS_FSL_SEC_COMPAT_2
 497         select SYS_PPC_E500_USE_DEBUG_TLB
 498
 499 config ARCH_MPC8555
 500         bool
 501         select FSL_LAW
 502         select SYS_FSL_HAS_DDR1
 503         select SYS_FSL_HAS_SEC
 504         select SYS_FSL_SEC_BE
 505         select SYS_FSL_SEC_COMPAT_2
 506
 507 config ARCH_MPC8560
 508         bool
 509         select FSL_LAW
 510         select SYS_FSL_HAS_DDR1
 511
 512 config ARCH_MPC8568
 513         bool
 514         select FSL_LAW
 515         select SYS_FSL_HAS_DDR2
 516         select SYS_FSL_HAS_SEC
 517         select SYS_FSL_SEC_BE
 518         select SYS_FSL_SEC_COMPAT_2
 519
 520 config ARCH_MPC8569
 521         bool
 522         select FSL_LAW
 523         select SYS_FSL_ERRATUM_A004508
 524         select SYS_FSL_ERRATUM_A005125
 525         select SYS_FSL_HAS_DDR3
 526         select SYS_FSL_HAS_SEC
 527         select SYS_FSL_SEC_BE
 528         select SYS_FSL_SEC_COMPAT_2
 529         select FSL_ELBC
 530
 531 config ARCH_MPC8572
 532         bool
 533         select FSL_LAW
 534         select SYS_FSL_ERRATUM_A004508
 535         select SYS_FSL_ERRATUM_A005125
 536         select SYS_FSL_ERRATUM_DDR_115
 537         select SYS_FSL_ERRATUM_DDR111_DDR134
 538         select SYS_FSL_HAS_DDR2
 539         select SYS_FSL_HAS_DDR3
 540         select SYS_FSL_HAS_SEC
 541         select SYS_FSL_SEC_BE
 542         select SYS_FSL_SEC_COMPAT_2
 543         select SYS_PPC_E500_USE_DEBUG_TLB
 544         select FSL_ELBC
 545
 546 config ARCH_P1010
 547         bool
 548         select FSL_LAW
 549         select SYS_FSL_ERRATUM_A004477
 550         select SYS_FSL_ERRATUM_A004508
 551         select SYS_FSL_ERRATUM_A005125
 552         select SYS_FSL_ERRATUM_A006261
 553         select SYS_FSL_ERRATUM_A007075
 554         select SYS_FSL_ERRATUM_ESDHC111
 555         select SYS_FSL_ERRATUM_I2C_A004447
 556         select SYS_FSL_ERRATUM_IFC_A002769
 557         select SYS_FSL_ERRATUM_P1010_A003549
 558         select SYS_FSL_ERRATUM_SEC_A003571
 559         select SYS_FSL_ERRATUM_IFC_A003399
 560         select SYS_FSL_HAS_DDR3
 561         select SYS_FSL_HAS_SEC
 562         select SYS_FSL_SEC_BE
 563         select SYS_FSL_SEC_COMPAT_4
 564         select SYS_PPC_E500_USE_DEBUG_TLB
 565         select FSL_IFC
 566
 567 config ARCH_P1011
 568         bool
 569         select FSL_LAW
 570         select SYS_FSL_ERRATUM_A004508
 571         select SYS_FSL_ERRATUM_A005125
 572         select SYS_FSL_ERRATUM_ELBC_A001
 573         select SYS_FSL_ERRATUM_ESDHC111
 574         select SYS_FSL_HAS_DDR3
 575         select SYS_FSL_HAS_SEC
 576         select SYS_FSL_SEC_BE
 577         select SYS_FSL_SEC_COMPAT_2
 578         select SYS_PPC_E500_USE_DEBUG_TLB
 579         select FSL_ELBC
 580
 581 config ARCH_P1020
 582         bool
 583         select FSL_LAW
 584         select SYS_FSL_ERRATUM_A004508
 585         select SYS_FSL_ERRATUM_A005125
 586         select SYS_FSL_ERRATUM_ELBC_A001
 587         select SYS_FSL_ERRATUM_ESDHC111
 588         select SYS_FSL_HAS_DDR3
 589         select SYS_FSL_HAS_SEC
 590         select SYS_FSL_SEC_BE
 591         select SYS_FSL_SEC_COMPAT_2
 592         select SYS_PPC_E500_USE_DEBUG_TLB
 593         select FSL_ELBC
 594
 595 config ARCH_P1021
 596         bool
 597         select FSL_LAW
 598         select SYS_FSL_ERRATUM_A004508
 599         select SYS_FSL_ERRATUM_A005125
 600         select SYS_FSL_ERRATUM_ELBC_A001
 601         select SYS_FSL_ERRATUM_ESDHC111
 602         select SYS_FSL_HAS_DDR3
 603         select SYS_FSL_HAS_SEC
 604         select SYS_FSL_SEC_BE
 605         select SYS_FSL_SEC_COMPAT_2
 606         select SYS_PPC_E500_USE_DEBUG_TLB
 607         select FSL_ELBC
 608
 609 config ARCH_P1022
 610         bool
 611         select FSL_LAW
 612         select SYS_FSL_ERRATUM_A004477
 613         select SYS_FSL_ERRATUM_A004508
 614         select SYS_FSL_ERRATUM_A005125
 615         select SYS_FSL_ERRATUM_ELBC_A001
 616         select SYS_FSL_ERRATUM_ESDHC111
 617         select SYS_FSL_ERRATUM_SATA_A001
 618         select SYS_FSL_HAS_DDR3
 619         select SYS_FSL_HAS_SEC
 620         select SYS_FSL_SEC_BE
 621         select SYS_FSL_SEC_COMPAT_2
 622         select SYS_PPC_E500_USE_DEBUG_TLB
 623         select FSL_ELBC
 624
 625 config ARCH_P1023
 626         bool
 627         select FSL_LAW
 628         select SYS_FSL_ERRATUM_A004508
 629         select SYS_FSL_ERRATUM_A005125
 630         select SYS_FSL_ERRATUM_I2C_A004447
 631         select SYS_FSL_HAS_DDR3
 632         select SYS_FSL_HAS_SEC
 633         select SYS_FSL_SEC_BE
 634         select SYS_FSL_SEC_COMPAT_4
 635         select FSL_ELBC
 636
 637 config ARCH_P1024
 638         bool
 639         select FSL_LAW
 640         select SYS_FSL_ERRATUM_A004508
 641         select SYS_FSL_ERRATUM_A005125
 642         select SYS_FSL_ERRATUM_ELBC_A001
 643         select SYS_FSL_ERRATUM_ESDHC111
 644         select SYS_FSL_HAS_DDR3
 645         select SYS_FSL_HAS_SEC
 646         select SYS_FSL_SEC_BE
 647         select SYS_FSL_SEC_COMPAT_2
 648         select SYS_PPC_E500_USE_DEBUG_TLB
 649         select FSL_ELBC
 650
 651 config ARCH_P1025
 652         bool
 653         select FSL_LAW
 654         select SYS_FSL_ERRATUM_A004508
 655         select SYS_FSL_ERRATUM_A005125
 656         select SYS_FSL_ERRATUM_ELBC_A001
 657         select SYS_FSL_ERRATUM_ESDHC111
 658         select SYS_FSL_HAS_DDR3
 659         select SYS_FSL_HAS_SEC
 660         select SYS_FSL_SEC_BE
 661         select SYS_FSL_SEC_COMPAT_2
 662         select SYS_PPC_E500_USE_DEBUG_TLB
 663         select FSL_ELBC
 664
 665 config ARCH_P2020
 666         bool
 667         select FSL_LAW
 668         select SYS_FSL_ERRATUM_A004477
 669         select SYS_FSL_ERRATUM_A004508
 670         select SYS_FSL_ERRATUM_A005125
 671         select SYS_FSL_ERRATUM_ESDHC111
 672         select SYS_FSL_ERRATUM_ESDHC_A001
 673         select SYS_FSL_HAS_DDR3
 674         select SYS_FSL_HAS_SEC
 675         select SYS_FSL_SEC_BE
 676         select SYS_FSL_SEC_COMPAT_2
 677         select SYS_PPC_E500_USE_DEBUG_TLB
 678         select FSL_ELBC
 679
 680 config ARCH_P2041
 681         bool
 682         select E500MC
 683         select FSL_LAW
 684         select SYS_FSL_ERRATUM_A004510
 685         select SYS_FSL_ERRATUM_A004849
 686         select SYS_FSL_ERRATUM_A006261
 687         select SYS_FSL_ERRATUM_CPU_A003999
 688         select SYS_FSL_ERRATUM_DDR_A003
 689         select SYS_FSL_ERRATUM_DDR_A003474
 690         select SYS_FSL_ERRATUM_ESDHC111
 691         select SYS_FSL_ERRATUM_I2C_A004447
 692         select SYS_FSL_ERRATUM_NMG_CPU_A011
 693         select SYS_FSL_ERRATUM_SRIO_A004034
 694         select SYS_FSL_ERRATUM_USB14
 695         select SYS_FSL_HAS_DDR3
 696         select SYS_FSL_HAS_SEC
 697         select SYS_FSL_QORIQ_CHASSIS1
 698         select SYS_FSL_SEC_BE
 699         select SYS_FSL_SEC_COMPAT_4
 700         select FSL_ELBC
 701
 702 config ARCH_P3041
 703         bool
 704         select E500MC
 705         select FSL_LAW
 706         select SYS_FSL_DDR_VER_44
 707         select SYS_FSL_ERRATUM_A004510
 708         select SYS_FSL_ERRATUM_A004849
 709         select SYS_FSL_ERRATUM_A005812
 710         select SYS_FSL_ERRATUM_A006261
 711         select SYS_FSL_ERRATUM_CPU_A003999
 712         select SYS_FSL_ERRATUM_DDR_A003
 713         select SYS_FSL_ERRATUM_DDR_A003474
 714         select SYS_FSL_ERRATUM_ESDHC111
 715         select SYS_FSL_ERRATUM_I2C_A004447
 716         select SYS_FSL_ERRATUM_NMG_CPU_A011
 717         select SYS_FSL_ERRATUM_SRIO_A004034
 718         select SYS_FSL_ERRATUM_USB14
 719         select SYS_FSL_HAS_DDR3
 720         select SYS_FSL_HAS_SEC
 721         select SYS_FSL_QORIQ_CHASSIS1
 722         select SYS_FSL_SEC_BE
 723         select SYS_FSL_SEC_COMPAT_4
 724         select FSL_ELBC
 725
 726 config ARCH_P4080
 727         bool
 728         select E500MC
 729         select FSL_LAW
 730         select SYS_FSL_DDR_VER_44
 731         select SYS_FSL_ERRATUM_A004510
 732         select SYS_FSL_ERRATUM_A004580
 733         select SYS_FSL_ERRATUM_A004849
 734         select SYS_FSL_ERRATUM_A005812
 735         select SYS_FSL_ERRATUM_A007075
 736         select SYS_FSL_ERRATUM_CPC_A002
 737         select SYS_FSL_ERRATUM_CPC_A003
 738         select SYS_FSL_ERRATUM_CPU_A003999
 739         select SYS_FSL_ERRATUM_DDR_A003
 740         select SYS_FSL_ERRATUM_DDR_A003474
 741         select SYS_FSL_ERRATUM_ELBC_A001
 742         select SYS_FSL_ERRATUM_ESDHC111
 743         select SYS_FSL_ERRATUM_ESDHC13
 744         select SYS_FSL_ERRATUM_ESDHC135
 745         select SYS_FSL_ERRATUM_I2C_A004447
 746         select SYS_FSL_ERRATUM_NMG_CPU_A011
 747         select SYS_FSL_ERRATUM_SRIO_A004034
 748         select SYS_P4080_ERRATUM_CPU22
 749         select SYS_P4080_ERRATUM_PCIE_A003
 750         select SYS_P4080_ERRATUM_SERDES8
 751         select SYS_P4080_ERRATUM_SERDES9
 752         select SYS_P4080_ERRATUM_SERDES_A001
 753         select SYS_P4080_ERRATUM_SERDES_A005
 754         select SYS_FSL_HAS_DDR3
 755         select SYS_FSL_HAS_SEC
 756         select SYS_FSL_QORIQ_CHASSIS1
 757         select SYS_FSL_SEC_BE
 758         select SYS_FSL_SEC_COMPAT_4
 759         select FSL_ELBC
 760
 761 config ARCH_P5020
 762         bool
 763         select E500MC
 764         select FSL_LAW
 765         select SYS_FSL_DDR_VER_44
 766         select SYS_FSL_ERRATUM_A004510
 767         select SYS_FSL_ERRATUM_A006261
 768         select SYS_FSL_ERRATUM_DDR_A003
 769         select SYS_FSL_ERRATUM_DDR_A003474
 770         select SYS_FSL_ERRATUM_ESDHC111
 771         select SYS_FSL_ERRATUM_I2C_A004447
 772         select SYS_FSL_ERRATUM_SRIO_A004034
 773         select SYS_FSL_ERRATUM_USB14
 774         select SYS_FSL_HAS_DDR3
 775         select SYS_FSL_HAS_SEC
 776         select SYS_FSL_QORIQ_CHASSIS1
 777         select SYS_FSL_SEC_BE
 778         select SYS_FSL_SEC_COMPAT_4
 779         select SYS_PPC64
 780         select FSL_ELBC
 781
 782 config ARCH_P5040
 783         bool
 784         select E500MC
 785         select FSL_LAW
 786         select SYS_FSL_DDR_VER_44
 787         select SYS_FSL_ERRATUM_A004510
 788         select SYS_FSL_ERRATUM_A004699
 789         select SYS_FSL_ERRATUM_A005812
 790         select SYS_FSL_ERRATUM_A006261
 791         select SYS_FSL_ERRATUM_DDR_A003
 792         select SYS_FSL_ERRATUM_DDR_A003474
 793         select SYS_FSL_ERRATUM_ESDHC111
 794         select SYS_FSL_ERRATUM_USB14
 795         select SYS_FSL_HAS_DDR3
 796         select SYS_FSL_HAS_SEC
 797         select SYS_FSL_QORIQ_CHASSIS1
 798         select SYS_FSL_SEC_BE
 799         select SYS_FSL_SEC_COMPAT_4
 800         select SYS_PPC64
 801         select FSL_ELBC
 802
 803 config ARCH_QEMU_E500
 804         bool
 805
 806 config ARCH_T1023
 807         bool
 808         select E500MC
 809         select FSL_LAW
 810         select SYS_FSL_DDR_VER_50
 811         select SYS_FSL_ERRATUM_A008378
 812         select SYS_FSL_ERRATUM_A009663
 813         select SYS_FSL_ERRATUM_A009942
 814         select SYS_FSL_ERRATUM_ESDHC111
 815         select SYS_FSL_HAS_DDR3
 816         select SYS_FSL_HAS_DDR4
 817         select SYS_FSL_HAS_SEC
 818         select SYS_FSL_QORIQ_CHASSIS2
 819         select SYS_FSL_SEC_BE
 820         select SYS_FSL_SEC_COMPAT_5
 821         select FSL_IFC
 822
 823 config ARCH_T1024
 824         bool
 825         select E500MC
 826         select FSL_LAW
 827         select SYS_FSL_DDR_VER_50
 828         select SYS_FSL_ERRATUM_A008378
 829         select SYS_FSL_ERRATUM_A009663
 830         select SYS_FSL_ERRATUM_A009942
 831         select SYS_FSL_ERRATUM_ESDHC111
 832         select SYS_FSL_HAS_DDR3
 833         select SYS_FSL_HAS_DDR4
 834         select SYS_FSL_HAS_SEC
 835         select SYS_FSL_QORIQ_CHASSIS2
 836         select SYS_FSL_SEC_BE
 837         select SYS_FSL_SEC_COMPAT_5
 838         select FSL_IFC
 839
 840 config ARCH_T1040
 841         bool
 842         select E500MC
 843         select FSL_LAW
 844         select SYS_FSL_DDR_VER_50
 845         select SYS_FSL_ERRATUM_A008044
 846         select SYS_FSL_ERRATUM_A008378
 847         select SYS_FSL_ERRATUM_A009663
 848         select SYS_FSL_ERRATUM_A009942
 849         select SYS_FSL_ERRATUM_ESDHC111
 850         select SYS_FSL_HAS_DDR3
 851         select SYS_FSL_HAS_DDR4
 852         select SYS_FSL_HAS_SEC
 853         select SYS_FSL_QORIQ_CHASSIS2
 854         select SYS_FSL_SEC_BE
 855         select SYS_FSL_SEC_COMPAT_5
 856         select FSL_IFC
 857
 858 config ARCH_T1042
 859         bool
 860         select E500MC
 861         select FSL_LAW
 862         select SYS_FSL_DDR_VER_50
 863         select SYS_FSL_ERRATUM_A008044
 864         select SYS_FSL_ERRATUM_A008378
 865         select SYS_FSL_ERRATUM_A009663
 866         select SYS_FSL_ERRATUM_A009942
 867         select SYS_FSL_ERRATUM_ESDHC111
 868         select SYS_FSL_HAS_DDR3
 869         select SYS_FSL_HAS_DDR4
 870         select SYS_FSL_HAS_SEC
 871         select SYS_FSL_QORIQ_CHASSIS2
 872         select SYS_FSL_SEC_BE
 873         select SYS_FSL_SEC_COMPAT_5
 874         select FSL_IFC
 875
 876 config ARCH_T2080
 877         bool
 878         select E500MC
 879         select E6500
 880         select FSL_LAW
 881         select SYS_FSL_DDR_VER_47
 882         select SYS_FSL_ERRATUM_A006379
 883         select SYS_FSL_ERRATUM_A006593
 884         select SYS_FSL_ERRATUM_A007186
 885         select SYS_FSL_ERRATUM_A007212
 886         select SYS_FSL_ERRATUM_A007815
 887         select SYS_FSL_ERRATUM_A007907
 888         select SYS_FSL_ERRATUM_A009942
 889         select SYS_FSL_ERRATUM_ESDHC111
 890         select SYS_FSL_HAS_DDR3
 891         select SYS_FSL_HAS_SEC
 892         select SYS_FSL_QORIQ_CHASSIS2
 893         select SYS_FSL_SEC_BE
 894         select SYS_FSL_SEC_COMPAT_4
 895         select SYS_PPC64
 896         select FSL_IFC
 897
 898 config ARCH_T2081
 899         bool
 900         select E500MC
 901         select E6500
 902         select FSL_LAW
 903         select SYS_FSL_DDR_VER_47
 904         select SYS_FSL_ERRATUM_A006379
 905         select SYS_FSL_ERRATUM_A006593
 906         select SYS_FSL_ERRATUM_A007186
 907         select SYS_FSL_ERRATUM_A007212
 908         select SYS_FSL_ERRATUM_A009942
 909         select SYS_FSL_ERRATUM_ESDHC111
 910         select SYS_FSL_HAS_DDR3
 911         select SYS_FSL_HAS_SEC
 912         select SYS_FSL_QORIQ_CHASSIS2
 913         select SYS_FSL_SEC_BE
 914         select SYS_FSL_SEC_COMPAT_4
 915         select SYS_PPC64
 916         select FSL_IFC
 917
 918 config ARCH_T4160
 919         bool
 920         select E500MC
 921         select E6500
 922         select FSL_LAW
 923         select SYS_FSL_DDR_VER_47
 924         select SYS_FSL_ERRATUM_A004468
 925         select SYS_FSL_ERRATUM_A005871
 926         select SYS_FSL_ERRATUM_A006379
 927         select SYS_FSL_ERRATUM_A006593
 928         select SYS_FSL_ERRATUM_A007186
 929         select SYS_FSL_ERRATUM_A007798
 930         select SYS_FSL_ERRATUM_A009942
 931         select SYS_FSL_HAS_DDR3
 932         select SYS_FSL_HAS_SEC
 933         select SYS_FSL_QORIQ_CHASSIS2
 934         select SYS_FSL_SEC_BE
 935         select SYS_FSL_SEC_COMPAT_4
 936         select SYS_PPC64
 937         select FSL_IFC
 938
 939 config ARCH_T4240
 940         bool
 941         select E500MC
 942         select E6500
 943         select FSL_LAW
 944         select SYS_FSL_DDR_VER_47
 945         select SYS_FSL_ERRATUM_A004468
 946         select SYS_FSL_ERRATUM_A005871
 947         select SYS_FSL_ERRATUM_A006261
 948         select SYS_FSL_ERRATUM_A006379
 949         select SYS_FSL_ERRATUM_A006593
 950         select SYS_FSL_ERRATUM_A007186
 951         select SYS_FSL_ERRATUM_A007798
 952         select SYS_FSL_ERRATUM_A007815
 953         select SYS_FSL_ERRATUM_A007907
 954         select SYS_FSL_ERRATUM_A009942
 955         select SYS_FSL_HAS_DDR3
 956         select SYS_FSL_HAS_SEC
 957         select SYS_FSL_QORIQ_CHASSIS2
 958         select SYS_FSL_SEC_BE
 959         select SYS_FSL_SEC_COMPAT_4
 960         select SYS_PPC64
 961         select FSL_IFC
 962
 963 config BOOKE
 964         bool
 965         default y
 966
 967 config E500
 968         bool
 969         default y
 970         help
 971                 Enable PowerPC E500 cores, including e500v1, e500v2, e500mc
 972
 973 config E500MC
 974         bool
 975         help
 976                 Enble PowerPC E500MC core
 977
 978 config E6500
 979         bool
 980         help
 981                 Enable PowerPC E6500 core
 982
 983 config FSL_LAW
 984         bool
 985         help
 986                 Use Freescale common code for Local Access Window
 987
 988 config SECURE_BOOT
 989         bool    "Secure Boot"
 990         help
 991                 Enable Freescale Secure Boot feature. Normally selected
 992                 by defconfig. If unsure, do not change.
 993
 994 config MAX_CPUS
 995         int "Maximum number of CPUs permitted for MPC85xx"
 996         default 12 if ARCH_T4240
 997         default 8 if ARCH_P4080 || \
 998                      ARCH_T4160
 999         default 4 if ARCH_B4860 || \
1000                      ARCH_P2041 || \
1001                      ARCH_P3041 || \
1002                      ARCH_P5040 || \
1003                      ARCH_T1040 || \
1004                      ARCH_T1042 || \
1005                      ARCH_T2080 || \
1006                      ARCH_T2081
1007         default 2 if ARCH_B4420 || \
1008                      ARCH_BSC9132 || \
1009                      ARCH_MPC8572 || \
1010                      ARCH_P1020 || \
1011                      ARCH_P1021 || \
1012                      ARCH_P1022 || \
1013                      ARCH_P1023 || \
1014                      ARCH_P1024 || \
1015                      ARCH_P1025 || \
1016                      ARCH_P2020 || \
1017                      ARCH_P5020 || \
1018                      ARCH_T1023 || \
1019                      ARCH_T1024
1020         default 1
1021         help
1022           Set this number to the maximum number of possible CPUs in the SoC.
1023           SoCs may have multiple clusters with each cluster may have multiple
1024           ports. If some ports are reserved but higher ports are used for
1025           cores, count the reserved ports. This will allocate enough memory
1026           in spin table to properly handle all cores.
1027
1028 config SYS_CCSRBAR_DEFAULT
1029         hex "Default CCSRBAR address"
1030         default 0xff700000 if   ARCH_BSC9131    || \
1031                                 ARCH_BSC9132    || \
1032                                 ARCH_C29X       || \
1033                                 ARCH_MPC8536    || \
1034                                 ARCH_MPC8540    || \
1035                                 ARCH_MPC8541    || \
1036                                 ARCH_MPC8544    || \
1037                                 ARCH_MPC8548    || \
1038                                 ARCH_MPC8555    || \
1039                                 ARCH_MPC8560    || \
1040                                 ARCH_MPC8568    || \
1041                                 ARCH_MPC8569    || \
1042                                 ARCH_MPC8572    || \
1043                                 ARCH_P1010      || \
1044                                 ARCH_P1011      || \
1045                                 ARCH_P1020      || \
1046                                 ARCH_P1021      || \
1047                                 ARCH_P1022      || \
1048                                 ARCH_P1024      || \
1049                                 ARCH_P1025      || \
1050                                 ARCH_P2020
1051         default 0xff600000 if   ARCH_P1023
1052         default 0xfe000000 if   ARCH_B4420      || \
1053                                 ARCH_B4860      || \
1054                                 ARCH_P2041      || \
1055                                 ARCH_P3041      || \
1056                                 ARCH_P4080      || \
1057                                 ARCH_P5020      || \
1058                                 ARCH_P5040      || \
1059                                 ARCH_T1023      || \
1060                                 ARCH_T1024      || \
1061                                 ARCH_T1040      || \
1062                                 ARCH_T1042      || \
1063                                 ARCH_T2080      || \
1064                                 ARCH_T2081      || \
1065                                 ARCH_T4160      || \
1066                                 ARCH_T4240
1067         default 0xe0000000 if ARCH_QEMU_E500
1068         help
1069                 Default value of CCSRBAR comes from power-on-reset. It
1070                 is fixed on each SoC. Some SoCs can have different value
1071                 if changed by pre-boot regime. The value here must match
1072                 the current value in SoC. If not sure, do not change.
1073
1074 config SYS_FSL_ERRATUM_A004468
1075         bool
1076
1077 config SYS_FSL_ERRATUM_A004477
1078         bool
1079
1080 config SYS_FSL_ERRATUM_A004508
1081         bool
1082
1083 config SYS_FSL_ERRATUM_A004580
1084         bool
1085
1086 config SYS_FSL_ERRATUM_A004699
1087         bool
1088
1089 config SYS_FSL_ERRATUM_A004849
1090         bool
1091
1092 config SYS_FSL_ERRATUM_A004510
1093         bool
1094
1095 config SYS_FSL_ERRATUM_A004510_SVR_REV
1096         hex
1097         depends on SYS_FSL_ERRATUM_A004510
1098         default 0x20 if ARCH_P4080
1099         default 0x10
1100
1101 config SYS_FSL_ERRATUM_A004510_SVR_REV2
1102         hex
1103         depends on (SYS_FSL_ERRATUM_A004510 && (ARCH_P2041 || ARCH_P3041))
1104         default 0x11
1105
1106 config SYS_FSL_ERRATUM_A005125
1107         bool
1108
1109 config SYS_FSL_ERRATUM_A005434
1110         bool
1111
1112 config SYS_FSL_ERRATUM_A005812
1113         bool
1114
1115 config SYS_FSL_ERRATUM_A005871
1116         bool
1117
1118 config SYS_FSL_ERRATUM_A006261
1119         bool
1120
1121 config SYS_FSL_ERRATUM_A006379
1122         bool
1123
1124 config SYS_FSL_ERRATUM_A006384
1125         bool
1126
1127 config SYS_FSL_ERRATUM_A006475
1128         bool
1129
1130 config SYS_FSL_ERRATUM_A006593
1131         bool
1132
1133 config SYS_FSL_ERRATUM_A007075
1134         bool
1135
1136 config SYS_FSL_ERRATUM_A007186
1137         bool
1138
1139 config SYS_FSL_ERRATUM_A007212
1140         bool
1141
1142 config SYS_FSL_ERRATUM_A007815
1143         bool
1144
1145 config SYS_FSL_ERRATUM_A007798
1146         bool
1147
1148 config SYS_FSL_ERRATUM_A007907
1149         bool
1150
1151 config SYS_FSL_ERRATUM_A008044
1152         bool
1153
1154 config SYS_FSL_ERRATUM_CPC_A002
1155         bool
1156
1157 config SYS_FSL_ERRATUM_CPC_A003
1158         bool
1159
1160 config SYS_FSL_ERRATUM_CPU_A003999
1161         bool
1162
1163 config SYS_FSL_ERRATUM_ELBC_A001
1164         bool
1165
1166 config SYS_FSL_ERRATUM_I2C_A004447
1167         bool
1168
1169 config SYS_FSL_A004447_SVR_REV
1170         hex
1171         depends on SYS_FSL_ERRATUM_I2C_A004447
1172         default 0x00 if ARCH_MPC8548
1173         default 0x10 if ARCH_P1010
1174         default 0x11 if ARCH_P1023 || ARCH_P2041 || ARCH_BSC9132
1175         default 0x20 if ARCH_P3041 || ARCH_P4080 || ARCH_P5020
1176
1177 config SYS_FSL_ERRATUM_IFC_A002769
1178         bool
1179
1180 config SYS_FSL_ERRATUM_IFC_A003399
1181         bool
1182
1183 config SYS_FSL_ERRATUM_NMG_CPU_A011
1184         bool
1185
1186 config SYS_FSL_ERRATUM_NMG_ETSEC129
1187         bool
1188
1189 config SYS_FSL_ERRATUM_NMG_LBC103
1190         bool
1191
1192 config SYS_FSL_ERRATUM_P1010_A003549
1193         bool
1194
1195 config SYS_FSL_ERRATUM_SATA_A001
1196         bool
1197
1198 config SYS_FSL_ERRATUM_SEC_A003571
1199         bool
1200
1201 config SYS_FSL_ERRATUM_SRIO_A004034
1202         bool
1203
1204 config SYS_FSL_ERRATUM_USB14
1205         bool
1206
1207 config SYS_P4080_ERRATUM_CPU22
1208         bool
1209
1210 config SYS_P4080_ERRATUM_PCIE_A003
1211         bool
1212
1213 config SYS_P4080_ERRATUM_SERDES8
1214         bool
1215
1216 config SYS_P4080_ERRATUM_SERDES9
1217         bool
1218
1219 config SYS_P4080_ERRATUM_SERDES_A001
1220         bool
1221
1222 config SYS_P4080_ERRATUM_SERDES_A005
1223         bool
1224
1225 config SYS_FSL_QORIQ_CHASSIS1
1226         bool
1227
1228 config SYS_FSL_QORIQ_CHASSIS2
1229         bool
1230
1231 config SYS_FSL_NUM_LAWS
1232         int "Number of local access windows"
1233         depends on FSL_LAW
1234         default 32 if   ARCH_B4420      || \
1235                         ARCH_B4860      || \
1236                         ARCH_P2041      || \
1237                         ARCH_P3041      || \
1238                         ARCH_P4080      || \
1239                         ARCH_P5020      || \
1240                         ARCH_P5040      || \
1241                         ARCH_T2080      || \
1242                         ARCH_T2081      || \
1243                         ARCH_T4160      || \
1244                         ARCH_T4240
1245         default 16 if   ARCH_T1023      || \
1246                         ARCH_T1024      || \
1247                         ARCH_T1040      || \
1248                         ARCH_T1042
1249         default 12 if   ARCH_BSC9131    || \
1250                         ARCH_BSC9132    || \
1251                         ARCH_C29X       || \
1252                         ARCH_MPC8536    || \
1253                         ARCH_MPC8572    || \
1254                         ARCH_P1010      || \
1255                         ARCH_P1011      || \
1256                         ARCH_P1020      || \
1257                         ARCH_P1021      || \
1258                         ARCH_P1022      || \
1259                         ARCH_P1023      || \
1260                         ARCH_P1024      || \
1261                         ARCH_P1025      || \
1262                         ARCH_P2020
1263         default 10 if   ARCH_MPC8544    || \
1264                         ARCH_MPC8548    || \
1265                         ARCH_MPC8568    || \
1266                         ARCH_MPC8569
1267         default 8 if    ARCH_MPC8540    || \
1268                         ARCH_MPC8541    || \
1269                         ARCH_MPC8555    || \
1270                         ARCH_MPC8560
1271         help
1272                 Number of local access windows. This is fixed per SoC.
1273                 If not sure, do not change.
1274
1275 config SYS_FSL_THREADS_PER_CORE
1276         int
1277         default 2 if E6500
1278         default 1
1279
1280 config SYS_NUM_TLBCAMS
1281         int "Number of TLB CAM entries"
1282         default 64 if E500MC
1283         default 16
1284         help
1285                 Number of TLB CAM entries for Book-E chips. 64 for E500MC,
1286                 16 for other E500 SoCs.
1287
1288 config SYS_PPC64
1289         bool
1290
1291 config SYS_PPC_E500_USE_DEBUG_TLB
1292         bool
1293
1294 config FSL_IFC
1295         bool
1296
1297 config FSL_ELBC
1298         bool
1299
1300 config SYS_PPC_E500_DEBUG_TLB
1301         int "Temporary TLB entry for external debugger"
1302         depends on SYS_PPC_E500_USE_DEBUG_TLB
1303         default 0 if    ARCH_MPC8544 || ARCH_MPC8548
1304         default 1 if    ARCH_MPC8536
1305         default 2 if    ARCH_MPC8572    || \
1306                         ARCH_P1011      || \
1307                         ARCH_P1020      || \
1308                         ARCH_P1021      || \
1309                         ARCH_P1022      || \
1310                         ARCH_P1024      || \
1311                         ARCH_P1025      || \
1312                         ARCH_P2020
1313         default 3 if    ARCH_P1010      || \
1314                         ARCH_BSC9132    || \
1315                         ARCH_C29X
1316         help
1317                 Select a temporary TLB entry to be used during boot to work
1318                 around limitations in e500v1 and e500v2 external debugger
1319                 support. This reduces the portions of the boot code where
1320                 breakpoints and single stepping do not work. The value of this
1321                 symbol should be set to the TLB1 entry to be used for this
1322                 purpose. If unsure, do not change.
1323
1324 config SYS_FSL_IFC_CLK_DIV
1325         int "Divider of platform clock"
1326         depends on FSL_IFC
1327         default 2 if    ARCH_B4420      || \
1328                         ARCH_B4860      || \
1329                         ARCH_T1024      || \
1330                         ARCH_T1023      || \
1331                         ARCH_T1040      || \
1332                         ARCH_T1042      || \
1333                         ARCH_T4160      || \
1334                         ARCH_T4240
1335         default 1
1336         help
1337                 Defines divider of platform clock(clock input to
1338                 IFC controller).
1339
1340 config SYS_FSL_LBC_CLK_DIV
1341         int "Divider of platform clock"
1342         depends on FSL_ELBC || ARCH_MPC8540 || \
1343                 ARCH_MPC8548 || ARCH_MPC8541 || \
1344                 ARCH_MPC8555 || ARCH_MPC8560 || \
1345                 ARCH_MPC8568
1346
1347         default 2 if    ARCH_P2041      || \
1348                         ARCH_P3041      || \
1349                         ARCH_P4080      || \
1350                         ARCH_P5020      || \
1351                         ARCH_P5040
1352         default 1
1353
1354         help
1355                 Defines divider of platform clock(clock input to
1356                 eLBC controller).
1357
1358 source "board/freescale/b4860qds/Kconfig"
1359 source "board/freescale/bsc9131rdb/Kconfig"
1360 source "board/freescale/bsc9132qds/Kconfig"
1361 source "board/freescale/c29xpcie/Kconfig"
1362 source "board/freescale/corenet_ds/Kconfig"
1363 source "board/freescale/mpc8536ds/Kconfig"
1364 source "board/freescale/mpc8540ads/Kconfig"
1365 source "board/freescale/mpc8541cds/Kconfig"
1366 source "board/freescale/mpc8544ds/Kconfig"
1367 source "board/freescale/mpc8548cds/Kconfig"
1368 source "board/freescale/mpc8555cds/Kconfig"
1369 source "board/freescale/mpc8560ads/Kconfig"
1370 source "board/freescale/mpc8568mds/Kconfig"
1371 source "board/freescale/mpc8569mds/Kconfig"
1372 source "board/freescale/mpc8572ds/Kconfig"
1373 source "board/freescale/p1010rdb/Kconfig"
1374 source "board/freescale/p1022ds/Kconfig"
1375 source "board/freescale/p1023rdb/Kconfig"
1376 source "board/freescale/p1_p2_rdb_pc/Kconfig"
1377 source "board/freescale/p1_twr/Kconfig"
1378 source "board/freescale/p2041rdb/Kconfig"
1379 source "board/freescale/qemu-ppce500/Kconfig"
1380 source "board/freescale/t102xqds/Kconfig"
1381 source "board/freescale/t102xrdb/Kconfig"
1382 source "board/freescale/t1040qds/Kconfig"
1383 source "board/freescale/t104xrdb/Kconfig"
1384 source "board/freescale/t208xqds/Kconfig"
1385 source "board/freescale/t208xrdb/Kconfig"
1386 source "board/freescale/t4qds/Kconfig"
1387 source "board/freescale/t4rdb/Kconfig"
1388 source "board/gdsys/p1022/Kconfig"
1389 source "board/keymile/kmp204x/Kconfig"
1390 source "board/sbc8548/Kconfig"
1391 source "board/socrates/Kconfig"
1392 source "board/varisys/cyrus/Kconfig"
1393 source "board/xes/xpedite520x/Kconfig"
1394 source "board/xes/xpedite537x/Kconfig"
1395 source "board/xes/xpedite550x/Kconfig"
1396 source "board/Arcturus/ucp1020/Kconfig"
1397
1398 endmenu