arch/powerpc/cpu/mpc85xx/bsc9132_serdes.c

   1 /*
   2  * Copyright 2013 Freescale Semiconductor, Inc.
   3  * Author: Prabhakar Kushwaha <prabhakar@freescale.com>
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0+
   6  */
   7
   8 #include <config.h>
   9 #include <common.h>
  10 #include <asm/io.h>
  11 #include <asm/immap_85xx.h>
  12 #include <asm/fsl_serdes.h>
  13
  14 #define SRDS1_MAX_LANES         4
  15
  16 static u32 serdes1_prtcl_map;
  17
  18 static u8 serdes1_cfg_tbl[][SRDS1_MAX_LANES] = {
  19          [0] = {NONE, NONE, NONE, NONE},
  20          [1] = {PCIE1, PCIE2, CPRI2, CPRI1},
  21          [2] = {PCIE1, PCIE2, CPRI2, CPRI1},
  22          [3] = {PCIE1, PCIE2, CPRI2, CPRI1},
  23          [4] = {PCIE1, PCIE2, CPRI2, CPRI1},
  24          [5] = {PCIE1, PCIE2, CPRI2, CPRI1},
  25          [6] = {PCIE1, PCIE2, SGMII_TSEC1, CPRI1},
  26          [7] = {PCIE1, PCIE2, SGMII_TSEC1, CPRI1},
  27          [8] = {PCIE1, PCIE2, SGMII_TSEC1, CPRI1},
  28          [9] = {PCIE1, PCIE2, SGMII_TSEC1, CPRI1},
  29         [10] = {PCIE1, PCIE2, SGMII_TSEC1, CPRI1},
  30         [11] = {PCIE1, PCIE2, SGMII_TSEC1, SGMII_TSEC2},
  31         [12] = {PCIE1, SGMII_TSEC2, CPRI2, CPRI1},
  32         [13] = {PCIE1, SGMII_TSEC2, CPRI2, CPRI1},
  33         [14] = {PCIE1, SGMII_TSEC2, CPRI2, CPRI1},
  34         [15] = {PCIE1, SGMII_TSEC2, CPRI2, CPRI1},
  35         [16] = {PCIE1, SGMII_TSEC2, CPRI2, CPRI1},
  36         [17] = {PCIE1, SGMII_TSEC2, SGMII_TSEC1, CPRI1},
  37         [18] = {PCIE1, SGMII_TSEC2, SGMII_TSEC1, CPRI1},
  38         [19] = {PCIE1, SGMII_TSEC2, SGMII_TSEC1, CPRI1},
  39         [20] = {PCIE1, SGMII_TSEC2, SGMII_TSEC1, CPRI1},
  40         [21] = {PCIE1, SGMII_TSEC2, SGMII_TSEC1, CPRI1},
  41         [22] = {PCIE1, PCIE2, CPRI2, CPRI1},
  42         [23] = {PCIE1, PCIE2, CPRI2, CPRI1},
  43         [24] = {PCIE1, PCIE2, CPRI2, CPRI1},
  44         [25] = {PCIE1, PCIE2, CPRI2, CPRI1},
  45         [26] = {PCIE1, PCIE2, CPRI2, CPRI1},
  46         [27] = {PCIE1, PCIE2, SGMII_TSEC1, CPRI1},
  47         [28] = {PCIE1, PCIE2, SGMII_TSEC1, CPRI1},
  48         [29] = {PCIE1, PCIE2, SGMII_TSEC1, CPRI1},
  49         [30] = {PCIE1, PCIE2, SGMII_TSEC1, CPRI1},
  50         [31] = {PCIE1, PCIE2, SGMII_TSEC1, CPRI1},
  51         [32] = {PCIE1, PCIE2, SGMII_TSEC1, SGMII_TSEC2},
  52         [33] = {PCIE1, SGMII_TSEC2, CPRI2, CPRI1},
  53         [34] = {PCIE1, SGMII_TSEC2, CPRI2, CPRI1},
  54         [35] = {PCIE1, SGMII_TSEC2, CPRI2, CPRI1},
  55         [36] = {PCIE1, SGMII_TSEC2, CPRI2, CPRI1},
  56         [37] = {PCIE1, SGMII_TSEC2, CPRI2, CPRI1},
  57         [38] = {PCIE1, SGMII_TSEC2, SGMII_TSEC1, CPRI1},
  58         [39] = {PCIE1, SGMII_TSEC2, SGMII_TSEC1, CPRI1},
  59         [40] = {PCIE1, SGMII_TSEC2, SGMII_TSEC1, CPRI1},
  60         [41] = {PCIE1, SGMII_TSEC2, SGMII_TSEC1, CPRI1},
  61         [42] = {PCIE1, SGMII_TSEC2, SGMII_TSEC1, CPRI1},
  62         [43] = {SGMII_TSEC1, SGMII_TSEC2, CPRI2, CPRI1},
  63         [44] = {SGMII_TSEC1, SGMII_TSEC2, CPRI2, CPRI1},
  64         [45] = {SGMII_TSEC1, SGMII_TSEC2, CPRI2, CPRI1},
  65         [46] = {SGMII_TSEC1, SGMII_TSEC2, CPRI2, CPRI1},
  66         [47] = {SGMII_TSEC1, SGMII_TSEC2, CPRI2, CPRI1},
  67 };
  68
  69 int is_serdes_configured(enum srds_prtcl prtcl)
  70 {
  71         return (1 << prtcl) & serdes1_prtcl_map;
  72 }
  73
  74 void fsl_serdes_init(void)
  75 {
  76         ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
  77         u32 pordevsr = in_be32(&gur->pordevsr);
  78         u32 srds_cfg = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >>
  79                                 MPC85xx_PORDEVSR_IO_SEL_SHIFT;
  80         int lane;
  81
  82         debug("PORDEVSR[IO_SEL_SRDS] = %x\n", srds_cfg);
  83
  84         if (srds_cfg >= ARRAY_SIZE(serdes1_cfg_tbl)) {
  85                 printf("Invalid PORDEVSR[IO_SEL_SRDS] = %d\n", srds_cfg);
  86                 return;
  87         }
  88
  89         for (lane = 0; lane < SRDS1_MAX_LANES; lane++) {
  90                 enum srds_prtcl lane_prtcl = serdes1_cfg_tbl[srds_cfg][lane];
  91                 serdes1_prtcl_map |= (1 << lane_prtcl);
  92         }
  93 }