arch/powerpc/cpu/mpc85xx/cmd_errata.c

   1 /*
   2  * Copyright 2010-2011 Freescale Semiconductor, Inc.
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 #include <common.h>
   8 #include <command.h>
   9 #include <linux/compiler.h>
  10 #include <asm/processor.h>
  11 #include "fsl_corenet_serdes.h"
  12
  13 #ifdef CONFIG_SYS_FSL_ERRATUM_A004849
  14 /*
  15  * This work-around is implemented in PBI, so just check to see if the
  16  * work-around was actually applied.  To do this, we check for specific data
  17  * at specific addresses in DCSR.
  18  *
  19  * Array offsets[] contains a list of offsets within DCSR.  According to the
  20  * erratum document, the value at each offset should be 2.
  21  */
  22 static void check_erratum_a4849(uint32_t svr)
  23 {
  24         void __iomem *dcsr = (void *)CONFIG_SYS_DCSRBAR + 0xb0000;
  25         unsigned int i;
  26
  27 #if defined(CONFIG_PPC_P2041) || defined(CONFIG_PPC_P3041)
  28         static const uint8_t offsets[] = {
  29                 0x50, 0x54, 0x58, 0x90, 0x94, 0x98
  30         };
  31 #endif
  32 #ifdef CONFIG_PPC_P4080
  33         static const uint8_t offsets[] = {
  34                 0x60, 0x64, 0x68, 0x6c, 0xa0, 0xa4, 0xa8, 0xac
  35         };
  36 #endif
  37         uint32_t x108; /* The value that should be at offset 0x108 */
  38
  39         for (i = 0; i < ARRAY_SIZE(offsets); i++) {
  40                 if (in_be32(dcsr + offsets[i]) != 2) {
  41                         printf("Work-around for Erratum A004849 is not enabled\n");
  42                         return;
  43                 }
  44         }
  45
  46 #if defined(CONFIG_PPC_P2041) || defined(CONFIG_PPC_P3041)
  47         x108 = 0x12;
  48 #endif
  49
  50 #ifdef CONFIG_PPC_P4080
  51         /*
  52          * For P4080, the erratum document says that the value at offset 0x108
  53          * should be 0x12 on rev2, or 0x1c on rev3.
  54          */
  55         if (SVR_MAJ(svr) == 2)
  56                 x108 = 0x12;
  57         if (SVR_MAJ(svr) == 3)
  58                 x108 = 0x1c;
  59 #endif
  60
  61         if (in_be32(dcsr + 0x108) != x108) {
  62                 printf("Work-around for Erratum A004849 is not enabled\n");
  63                 return;
  64         }
  65
  66         /* Everything matches, so the erratum work-around was applied */
  67
  68         printf("Work-around for Erratum A004849 enabled\n");
  69 }
  70 #endif
  71
  72 #ifdef CONFIG_SYS_FSL_ERRATUM_A004580
  73 /*
  74  * This work-around is implemented in PBI, so just check to see if the
  75  * work-around was actually applied.  To do this, we check for specific data
  76  * at specific addresses in the SerDes register block.
  77  *
  78  * The work-around says that for each SerDes lane, write BnTTLCRy0 =
  79  * 0x1B00_0001, Register 2 = 0x0088_0000, and Register 3 = 0x4000_0000.
  80
  81  */
  82 static void check_erratum_a4580(uint32_t svr)
  83 {
  84         const serdes_corenet_t __iomem *srds_regs =
  85                 (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR;
  86         unsigned int lane;
  87
  88         for (lane = 0; lane < SRDS_MAX_LANES; lane++) {
  89                 if (serdes_lane_enabled(lane)) {
  90                         const struct serdes_lane __iomem *srds_lane =
  91                                 &srds_regs->lane[serdes_get_lane_idx(lane)];
  92
  93                         /*
  94                          * Verify that the values we were supposed to write in
  95                          * the PBI are actually there.  Also, the lower 15
  96                          * bits of res4[3] should be the same as the upper 15
  97                          * bits of res4[1].
  98                          */
  99                         if ((in_be32(&srds_lane->ttlcr0) != 0x1b000001) ||
 100                             (in_be32(&srds_lane->res4[1]) != 0x880000) ||
 101                             (in_be32(&srds_lane->res4[3]) != 0x40000044)) {
 102                                 printf("Work-around for Erratum A004580 is "
 103                                        "not enabled\n");
 104                                 return;
 105                         }
 106                 }
 107         }
 108
 109         /* Everything matches, so the erratum work-around was applied */
 110
 111         printf("Work-around for Erratum A004580 enabled\n");
 112 }
 113 #endif
 114
 115 static int do_errata(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 116 {
 117 #ifdef CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011
 118         extern int enable_cpu_a011_workaround;
 119 #endif
 120         __maybe_unused u32 svr = get_svr();
 121
 122 #if defined(CONFIG_FSL_SATA_V2) && defined(CONFIG_FSL_SATA_ERRATUM_A001)
 123         if (IS_SVR_REV(svr, 1, 0)) {
 124                 switch (SVR_SOC_VER(svr)) {
 125                 case SVR_P1013:
 126                 case SVR_P1022:
 127                         puts("Work-around for Erratum SATA A001 enabled\n");
 128                 }
 129         }
 130 #endif
 131
 132 #if defined(CONFIG_SYS_P4080_ERRATUM_SERDES8)
 133         puts("Work-around for Erratum SERDES8 enabled\n");
 134 #endif
 135 #if defined(CONFIG_SYS_P4080_ERRATUM_SERDES9)
 136         puts("Work-around for Erratum SERDES9 enabled\n");
 137 #endif
 138 #if defined(CONFIG_SYS_P4080_ERRATUM_SERDES_A005)
 139         puts("Work-around for Erratum SERDES-A005 enabled\n");
 140 #endif
 141 #if defined(CONFIG_SYS_P4080_ERRATUM_CPU22)
 142         if (SVR_MAJ(svr) < 3)
 143                 puts("Work-around for Erratum CPU22 enabled\n");
 144 #endif
 145 #ifdef CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011
 146         /*
 147          * NMG_CPU_A011 applies to P4080 rev 1.0, 2.0, fixed in 3.0
 148          * also applies to P3041 rev 1.0, 1.1, P2041 rev 1.0, 1.1
 149          * The SVR has been checked by cpu_init_r().
 150          */
 151         if (enable_cpu_a011_workaround)
 152                 puts("Work-around for Erratum CPU-A011 enabled\n");
 153 #endif
 154 #if defined(CONFIG_SYS_FSL_ERRATUM_CPU_A003999)
 155         puts("Work-around for Erratum CPU-A003999 enabled\n");
 156 #endif
 157 #if defined(CONFIG_SYS_FSL_ERRATUM_DDR_A003474)
 158         puts("Work-around for Erratum DDR-A003473 enabled\n");
 159 #endif
 160 #if defined(CONFIG_SYS_FSL_ERRATUM_DDR_MSYNC_IN)
 161         puts("Work-around for DDR MSYNC_IN Erratum enabled\n");
 162 #endif
 163 #if defined(CONFIG_SYS_FSL_ERRATUM_ESDHC111)
 164         puts("Work-around for Erratum ESDHC111 enabled\n");
 165 #endif
 166 #ifdef CONFIG_SYS_FSL_ERRATUM_A004468
 167         puts("Work-around for Erratum A004468 enabled\n");
 168 #endif
 169 #if defined(CONFIG_SYS_FSL_ERRATUM_ESDHC135)
 170         puts("Work-around for Erratum ESDHC135 enabled\n");
 171 #endif
 172 #if defined(CONFIG_SYS_FSL_ERRATUM_ESDHC13)
 173         if (SVR_MAJ(svr) < 3)
 174                 puts("Work-around for Erratum ESDHC13 enabled\n");
 175 #endif
 176 #if defined(CONFIG_SYS_FSL_ERRATUM_ESDHC_A001)
 177         puts("Work-around for Erratum ESDHC-A001 enabled\n");
 178 #endif
 179 #ifdef CONFIG_SYS_FSL_ERRATUM_CPC_A002
 180         puts("Work-around for Erratum CPC-A002 enabled\n");
 181 #endif
 182 #ifdef CONFIG_SYS_FSL_ERRATUM_CPC_A003
 183         puts("Work-around for Erratum CPC-A003 enabled\n");
 184 #endif
 185 #ifdef CONFIG_SYS_FSL_ERRATUM_ELBC_A001
 186         puts("Work-around for Erratum ELBC-A001 enabled\n");
 187 #endif
 188 #ifdef CONFIG_SYS_FSL_ERRATUM_DDR_A003
 189         puts("Work-around for Erratum DDR-A003 enabled\n");
 190 #endif
 191 #ifdef CONFIG_SYS_FSL_ERRATUM_DDR_115
 192         puts("Work-around for Erratum DDR115 enabled\n");
 193 #endif
 194 #ifdef CONFIG_SYS_FSL_ERRATUM_DDR111_DDR134
 195         puts("Work-around for Erratum DDR111 enabled\n");
 196         puts("Work-around for Erratum DDR134 enabled\n");
 197 #endif
 198 #ifdef CONFIG_SYS_FSL_ERRATUM_IFC_A002769
 199         puts("Work-around for Erratum IFC-A002769 enabled\n");
 200 #endif
 201 #ifdef CONFIG_SYS_FSL_ERRATUM_P1010_A003549
 202         puts("Work-around for Erratum P1010-A003549 enabled\n");
 203 #endif
 204 #ifdef CONFIG_SYS_FSL_ERRATUM_IFC_A003399
 205         puts("Work-around for Erratum IFC A-003399 enabled\n");
 206 #endif
 207 #ifdef CONFIG_SYS_FSL_ERRATUM_NMG_DDR120
 208         if ((SVR_MAJ(svr) == 1) || IS_SVR_REV(svr, 2, 0))
 209                 puts("Work-around for Erratum NMG DDR120 enabled\n");
 210 #endif
 211 #ifdef CONFIG_SYS_FSL_ERRATUM_NMG_LBC103
 212         puts("Work-around for Erratum NMG_LBC103 enabled\n");
 213 #endif
 214 #ifdef CONFIG_SYS_FSL_ERRATUM_NMG_ETSEC129
 215         if ((SVR_MAJ(svr) == 1) || IS_SVR_REV(svr, 2, 0))
 216                 puts("Work-around for Erratum NMG ETSEC129 enabled\n");
 217 #endif
 218 #ifdef CONFIG_SYS_FSL_ERRATUM_A004510
 219         puts("Work-around for Erratum A004510 enabled\n");
 220 #endif
 221 #ifdef CONFIG_SYS_FSL_ERRATUM_SRIO_A004034
 222         puts("Work-around for Erratum SRIO-A004034 enabled\n");
 223 #endif
 224 #ifdef CONFIG_SYS_FSL_ERRATUM_A_004934
 225         puts("Work-around for Erratum A004934 enabled\n");
 226 #endif
 227 #ifdef CONFIG_SYS_FSL_ERRATUM_A005871
 228         if (IS_SVR_REV(svr, 1, 0))
 229                 puts("Work-around for Erratum A005871 enabled\n");
 230 #endif
 231 #ifdef CONFIG_SYS_FSL_ERRATUM_A004849
 232         /* This work-around is implemented in PBI, so just check for it */
 233         check_erratum_a4849(svr);
 234 #endif
 235 #ifdef CONFIG_SYS_FSL_ERRATUM_A004580
 236         /* This work-around is implemented in PBI, so just check for it */
 237         check_erratum_a4580(svr);
 238 #endif
 239 #ifdef CONFIG_SYS_P4080_ERRATUM_PCIE_A003
 240         puts("Work-around for Erratum PCIe-A003 enabled\n");
 241 #endif
 242 #ifdef CONFIG_SYS_FSL_ERRATUM_USB14
 243         puts("Work-around for Erratum USB14 enabled\n");
 244 #endif
 245 #ifdef CONFIG_SYS_FSL_ERRATUM_A006593
 246         puts("Work-around for Erratum A006593 enabled\n");
 247 #endif
 248         return 0;
 249 }
 250
 251 U_BOOT_CMD(
 252         errata, 1, 0,   do_errata,
 253         "Report errata workarounds",
 254         ""
 255 );