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Merge branch 'u-boot-samsung/master' into 'u-boot-arm/master'
[people/ms/u-boot.git] / arch / powerpc / cpu / mpc85xx / cpu_init.c
1 /*
2 * Copyright 2007-2011 Freescale Semiconductor, Inc.
3 *
4 * (C) Copyright 2003 Motorola Inc.
5 * Modified by Xianghua Xiao, X.Xiao@motorola.com
6 *
7 * (C) Copyright 2000
8 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
9 *
10 * SPDX-License-Identifier: GPL-2.0+
11 */
12
13 #include <common.h>
14 #include <watchdog.h>
15 #include <asm/processor.h>
16 #include <ioports.h>
17 #include <sata.h>
18 #include <fm_eth.h>
19 #include <asm/io.h>
20 #include <asm/cache.h>
21 #include <asm/mmu.h>
22 #include <asm/fsl_errata.h>
23 #include <asm/fsl_law.h>
24 #include <asm/fsl_serdes.h>
25 #include <asm/fsl_srio.h>
26 #include <fsl_usb.h>
27 #include <hwconfig.h>
28 #include <linux/compiler.h>
29 #include "mp.h"
30 #ifdef CONFIG_SYS_QE_FMAN_FW_IN_NAND
31 #include <nand.h>
32 #include <errno.h>
33 #endif
34
35 #include "../../../../drivers/block/fsl_sata.h"
36 #ifdef CONFIG_U_QE
37 #include "../../../../drivers/qe/qe.h"
38 #endif
39
40 DECLARE_GLOBAL_DATA_PTR;
41
42 #ifdef CONFIG_SYS_FSL_SINGLE_SOURCE_CLK
43 /*
44 * For deriving usb clock from 100MHz sysclk, reference divisor is set
45 * to a value of 5, which gives an intermediate value 20(100/5). The
46 * multiplication factor integer is set to 24, which when multiplied to
47 * above intermediate value provides clock for usb ip.
48 */
49 void usb_single_source_clk_configure(struct ccsr_usb_phy *usb_phy)
50 {
51 sys_info_t sysinfo;
52
53 get_sys_info(&sysinfo);
54 if (sysinfo.diff_sysclk == 1) {
55 clrbits_be32(&usb_phy->pllprg[1],
56 CONFIG_SYS_FSL_USB_PLLPRG2_MFI);
57 setbits_be32(&usb_phy->pllprg[1],
58 CONFIG_SYS_FSL_USB_PLLPRG2_REF_DIV_INTERNAL_CLK |
59 CONFIG_SYS_FSL_USB_PLLPRG2_MFI_INTERNAL_CLK |
60 CONFIG_SYS_FSL_USB_INTERNAL_SOC_CLK_EN);
61 }
62 }
63 #endif
64
65 #ifdef CONFIG_SYS_FSL_ERRATUM_A006261
66 void fsl_erratum_a006261_workaround(struct ccsr_usb_phy __iomem *usb_phy)
67 {
68 #ifdef CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE
69 u32 xcvrprg = in_be32(&usb_phy->port1.xcvrprg);
70
71 /* Increase Disconnect Threshold by 50mV */
72 xcvrprg &= ~CONFIG_SYS_FSL_USB_XCVRPRG_HS_DCNT_PROG_MASK |
73 INC_DCNT_THRESHOLD_50MV;
74 /* Enable programming of USB High speed Disconnect threshold */
75 xcvrprg |= CONFIG_SYS_FSL_USB_XCVRPRG_HS_DCNT_PROG_EN;
76 out_be32(&usb_phy->port1.xcvrprg, xcvrprg);
77
78 xcvrprg = in_be32(&usb_phy->port2.xcvrprg);
79 /* Increase Disconnect Threshold by 50mV */
80 xcvrprg &= ~CONFIG_SYS_FSL_USB_XCVRPRG_HS_DCNT_PROG_MASK |
81 INC_DCNT_THRESHOLD_50MV;
82 /* Enable programming of USB High speed Disconnect threshold */
83 xcvrprg |= CONFIG_SYS_FSL_USB_XCVRPRG_HS_DCNT_PROG_EN;
84 out_be32(&usb_phy->port2.xcvrprg, xcvrprg);
85 #else
86
87 u32 temp = 0;
88 u32 status = in_be32(&usb_phy->status1);
89
90 u32 squelch_prog_rd_0_2 =
91 (status >> CONFIG_SYS_FSL_USB_SQUELCH_PROG_RD_0)
92 & CONFIG_SYS_FSL_USB_SQUELCH_PROG_MASK;
93
94 u32 squelch_prog_rd_3_5 =
95 (status >> CONFIG_SYS_FSL_USB_SQUELCH_PROG_RD_3)
96 & CONFIG_SYS_FSL_USB_SQUELCH_PROG_MASK;
97
98 setbits_be32(&usb_phy->config1,
99 CONFIG_SYS_FSL_USB_HS_DISCNCT_INC);
100 setbits_be32(&usb_phy->config2,
101 CONFIG_SYS_FSL_USB_RX_AUTO_CAL_RD_WR_SEL);
102
103 temp = squelch_prog_rd_0_2 << CONFIG_SYS_FSL_USB_SQUELCH_PROG_WR_0;
104 out_be32(&usb_phy->config2, in_be32(&usb_phy->config2) | temp);
105
106 temp = squelch_prog_rd_3_5 << CONFIG_SYS_FSL_USB_SQUELCH_PROG_WR_3;
107 out_be32(&usb_phy->config2, in_be32(&usb_phy->config2) | temp);
108 #endif
109 }
110 #endif
111
112
113 #if defined(CONFIG_QE) && !defined(CONFIG_U_QE)
114 extern qe_iop_conf_t qe_iop_conf_tab[];
115 extern void qe_config_iopin(u8 port, u8 pin, int dir,
116 int open_drain, int assign);
117 extern void qe_init(uint qe_base);
118 extern void qe_reset(void);
119
120 static void config_qe_ioports(void)
121 {
122 u8 port, pin;
123 int dir, open_drain, assign;
124 int i;
125
126 for (i = 0; qe_iop_conf_tab[i].assign != QE_IOP_TAB_END; i++) {
127 port = qe_iop_conf_tab[i].port;
128 pin = qe_iop_conf_tab[i].pin;
129 dir = qe_iop_conf_tab[i].dir;
130 open_drain = qe_iop_conf_tab[i].open_drain;
131 assign = qe_iop_conf_tab[i].assign;
132 qe_config_iopin(port, pin, dir, open_drain, assign);
133 }
134 }
135 #endif
136
137 #ifdef CONFIG_CPM2
138 void config_8560_ioports (volatile ccsr_cpm_t * cpm)
139 {
140 int portnum;
141
142 for (portnum = 0; portnum < 4; portnum++) {
143 uint pmsk = 0,
144 ppar = 0,
145 psor = 0,
146 pdir = 0,
147 podr = 0,
148 pdat = 0;
149 iop_conf_t *iopc = (iop_conf_t *) & iop_conf_tab[portnum][0];
150 iop_conf_t *eiopc = iopc + 32;
151 uint msk = 1;
152
153 /*
154 * NOTE:
155 * index 0 refers to pin 31,
156 * index 31 refers to pin 0
157 */
158 while (iopc < eiopc) {
159 if (iopc->conf) {
160 pmsk |= msk;
161 if (iopc->ppar)
162 ppar |= msk;
163 if (iopc->psor)
164 psor |= msk;
165 if (iopc->pdir)
166 pdir |= msk;
167 if (iopc->podr)
168 podr |= msk;
169 if (iopc->pdat)
170 pdat |= msk;
171 }
172
173 msk <<= 1;
174 iopc++;
175 }
176
177 if (pmsk != 0) {
178 volatile ioport_t *iop = ioport_addr (cpm, portnum);
179 uint tpmsk = ~pmsk;
180
181 /*
182 * the (somewhat confused) paragraph at the
183 * bottom of page 35-5 warns that there might
184 * be "unknown behaviour" when programming
185 * PSORx and PDIRx, if PPARx = 1, so I
186 * decided this meant I had to disable the
187 * dedicated function first, and enable it
188 * last.
189 */
190 iop->ppar &= tpmsk;
191 iop->psor = (iop->psor & tpmsk) | psor;
192 iop->podr = (iop->podr & tpmsk) | podr;
193 iop->pdat = (iop->pdat & tpmsk) | pdat;
194 iop->pdir = (iop->pdir & tpmsk) | pdir;
195 iop->ppar |= ppar;
196 }
197 }
198 }
199 #endif
200
201 #ifdef CONFIG_SYS_FSL_CPC
202 #if defined(CONFIG_RAMBOOT_PBL) || defined(CONFIG_SYS_CPC_REINIT_F)
203 static void disable_cpc_sram(void)
204 {
205 int i;
206
207 cpc_corenet_t *cpc = (cpc_corenet_t *)CONFIG_SYS_FSL_CPC_ADDR;
208
209 for (i = 0; i < CONFIG_SYS_NUM_CPC; i++, cpc++) {
210 if (in_be32(&cpc->cpcsrcr0) & CPC_SRCR0_SRAMEN) {
211 /* find and disable LAW of SRAM */
212 struct law_entry law = find_law(CONFIG_SYS_INIT_L3_ADDR);
213
214 if (law.index == -1) {
215 printf("\nFatal error happened\n");
216 return;
217 }
218 disable_law(law.index);
219
220 clrbits_be32(&cpc->cpchdbcr0, CPC_HDBCR0_CDQ_SPEC_DIS);
221 out_be32(&cpc->cpccsr0, 0);
222 out_be32(&cpc->cpcsrcr0, 0);
223 }
224 }
225 }
226 #endif
227
228 static void enable_cpc(void)
229 {
230 int i;
231 u32 size = 0;
232
233 cpc_corenet_t *cpc = (cpc_corenet_t *)CONFIG_SYS_FSL_CPC_ADDR;
234
235 for (i = 0; i < CONFIG_SYS_NUM_CPC; i++, cpc++) {
236 u32 cpccfg0 = in_be32(&cpc->cpccfg0);
237 size += CPC_CFG0_SZ_K(cpccfg0);
238
239 #ifdef CONFIG_SYS_FSL_ERRATUM_CPC_A002
240 setbits_be32(&cpc->cpchdbcr0, CPC_HDBCR0_TAG_ECC_SCRUB_DIS);
241 #endif
242 #ifdef CONFIG_SYS_FSL_ERRATUM_CPC_A003
243 setbits_be32(&cpc->cpchdbcr0, CPC_HDBCR0_DATA_ECC_SCRUB_DIS);
244 #endif
245 #ifdef CONFIG_SYS_FSL_ERRATUM_A006593
246 setbits_be32(&cpc->cpchdbcr0, 1 << (31 - 21));
247 #endif
248 #ifdef CONFIG_SYS_FSL_ERRATUM_A006379
249 if (has_erratum_a006379()) {
250 setbits_be32(&cpc->cpchdbcr0,
251 CPC_HDBCR0_SPLRU_LEVEL_EN);
252 }
253 #endif
254
255 out_be32(&cpc->cpccsr0, CPC_CSR0_CE | CPC_CSR0_PE);
256 /* Read back to sync write */
257 in_be32(&cpc->cpccsr0);
258
259 }
260
261 puts("Corenet Platform Cache: ");
262 print_size(size * 1024, " enabled\n");
263 }
264
265 static void invalidate_cpc(void)
266 {
267 int i;
268 cpc_corenet_t *cpc = (cpc_corenet_t *)CONFIG_SYS_FSL_CPC_ADDR;
269
270 for (i = 0; i < CONFIG_SYS_NUM_CPC; i++, cpc++) {
271 /* skip CPC when it used as all SRAM */
272 if (in_be32(&cpc->cpcsrcr0) & CPC_SRCR0_SRAMEN)
273 continue;
274 /* Flash invalidate the CPC and clear all the locks */
275 out_be32(&cpc->cpccsr0, CPC_CSR0_FI | CPC_CSR0_LFC);
276 while (in_be32(&cpc->cpccsr0) & (CPC_CSR0_FI | CPC_CSR0_LFC))
277 ;
278 }
279 }
280 #else
281 #define enable_cpc()
282 #define invalidate_cpc()
283 #endif /* CONFIG_SYS_FSL_CPC */
284
285 /*
286 * Breathe some life into the CPU...
287 *
288 * Set up the memory map
289 * initialize a bunch of registers
290 */
291
292 #ifdef CONFIG_FSL_CORENET
293 static void corenet_tb_init(void)
294 {
295 volatile ccsr_rcpm_t *rcpm =
296 (void *)(CONFIG_SYS_FSL_CORENET_RCPM_ADDR);
297 volatile ccsr_pic_t *pic =
298 (void *)(CONFIG_SYS_MPC8xxx_PIC_ADDR);
299 u32 whoami = in_be32(&pic->whoami);
300
301 /* Enable the timebase register for this core */
302 out_be32(&rcpm->ctbenrl, (1 << whoami));
303 }
304 #endif
305
306 #ifdef CONFIG_SYS_FSL_ERRATUM_A007212
307 void fsl_erratum_a007212_workaround(void)
308 {
309 ccsr_gur_t __iomem *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
310 u32 ddr_pll_ratio;
311 u32 __iomem *plldgdcr1 = (void *)(CONFIG_SYS_DCSRBAR + 0x21c20);
312 u32 __iomem *plldadcr1 = (void *)(CONFIG_SYS_DCSRBAR + 0x21c28);
313 u32 __iomem *dpdovrcr4 = (void *)(CONFIG_SYS_DCSRBAR + 0x21e80);
314 #if (CONFIG_NUM_DDR_CONTROLLERS >= 2)
315 u32 __iomem *plldgdcr2 = (void *)(CONFIG_SYS_DCSRBAR + 0x21c40);
316 u32 __iomem *plldadcr2 = (void *)(CONFIG_SYS_DCSRBAR + 0x21c48);
317 #if (CONFIG_NUM_DDR_CONTROLLERS >= 3)
318 u32 __iomem *plldgdcr3 = (void *)(CONFIG_SYS_DCSRBAR + 0x21c60);
319 u32 __iomem *plldadcr3 = (void *)(CONFIG_SYS_DCSRBAR + 0x21c68);
320 #endif
321 #endif
322 /*
323 * Even this workaround applies to selected version of SoCs, it is
324 * safe to apply to all versions, with the limitation of odd ratios.
325 * If RCW has disabled DDR PLL, we have to apply this workaround,
326 * otherwise DDR will not work.
327 */
328 ddr_pll_ratio = (in_be32(&gur->rcwsr[0]) >>
329 FSL_CORENET_RCWSR0_MEM_PLL_RAT_SHIFT) &
330 FSL_CORENET_RCWSR0_MEM_PLL_RAT_MASK;
331 /* check if RCW sets ratio to 0, required by this workaround */
332 if (ddr_pll_ratio != 0)
333 return;
334 ddr_pll_ratio = (in_be32(&gur->rcwsr[0]) >>
335 FSL_CORENET_RCWSR0_MEM_PLL_RAT_RESV_SHIFT) &
336 FSL_CORENET_RCWSR0_MEM_PLL_RAT_MASK;
337 /* check if reserved bits have the desired ratio */
338 if (ddr_pll_ratio == 0) {
339 printf("Error: Unknown DDR PLL ratio!\n");
340 return;
341 }
342 ddr_pll_ratio >>= 1;
343
344 setbits_be32(plldadcr1, 0x02000001);
345 #if (CONFIG_NUM_DDR_CONTROLLERS >= 2)
346 setbits_be32(plldadcr2, 0x02000001);
347 #if (CONFIG_NUM_DDR_CONTROLLERS >= 3)
348 setbits_be32(plldadcr3, 0x02000001);
349 #endif
350 #endif
351 setbits_be32(dpdovrcr4, 0xe0000000);
352 out_be32(plldgdcr1, 0x08000001 | (ddr_pll_ratio << 1));
353 #if (CONFIG_NUM_DDR_CONTROLLERS >= 2)
354 out_be32(plldgdcr2, 0x08000001 | (ddr_pll_ratio << 1));
355 #if (CONFIG_NUM_DDR_CONTROLLERS >= 3)
356 out_be32(plldgdcr3, 0x08000001 | (ddr_pll_ratio << 1));
357 #endif
358 #endif
359 udelay(100);
360 clrbits_be32(plldadcr1, 0x02000001);
361 #if (CONFIG_NUM_DDR_CONTROLLERS >= 2)
362 clrbits_be32(plldadcr2, 0x02000001);
363 #if (CONFIG_NUM_DDR_CONTROLLERS >= 3)
364 clrbits_be32(plldadcr3, 0x02000001);
365 #endif
366 #endif
367 clrbits_be32(dpdovrcr4, 0xe0000000);
368 }
369 #endif
370
371 void cpu_init_f (void)
372 {
373 extern void m8560_cpm_reset (void);
374 #ifdef CONFIG_SYS_DCSRBAR_PHYS
375 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
376 gd = (gd_t *)(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET);
377 #endif
378 #if defined(CONFIG_SECURE_BOOT)
379 struct law_entry law;
380 #endif
381 #ifdef CONFIG_MPC8548
382 ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR);
383 uint svr = get_svr();
384
385 /*
386 * CPU2 errata workaround: A core hang possible while executing
387 * a msync instruction and a snoopable transaction from an I/O
388 * master tagged to make quick forward progress is present.
389 * Fixed in silicon rev 2.1.
390 */
391 if ((SVR_MAJ(svr) == 1) || ((SVR_MAJ(svr) == 2 && SVR_MIN(svr) == 0x0)))
392 out_be32(&ecm->eebpcr, in_be32(&ecm->eebpcr) | (1 << 16));
393 #endif
394
395 disable_tlb(14);
396 disable_tlb(15);
397
398 #if defined(CONFIG_SECURE_BOOT)
399 /* Disable the LAW created for NOR flash by the PBI commands */
400 law = find_law(CONFIG_SYS_PBI_FLASH_BASE);
401 if (law.index != -1)
402 disable_law(law.index);
403
404 #if defined(CONFIG_SYS_CPC_REINIT_F)
405 disable_cpc_sram();
406 #endif
407 #endif
408
409 #ifdef CONFIG_CPM2
410 config_8560_ioports((ccsr_cpm_t *)CONFIG_SYS_MPC85xx_CPM_ADDR);
411 #endif
412
413 init_early_memctl_regs();
414
415 #if defined(CONFIG_CPM2)
416 m8560_cpm_reset();
417 #endif
418
419 #if defined(CONFIG_QE) && !defined(CONFIG_U_QE)
420 /* Config QE ioports */
421 config_qe_ioports();
422 #endif
423
424 #if defined(CONFIG_FSL_DMA)
425 dma_init();
426 #endif
427 #ifdef CONFIG_FSL_CORENET
428 corenet_tb_init();
429 #endif
430 init_used_tlb_cams();
431
432 /* Invalidate the CPC before DDR gets enabled */
433 invalidate_cpc();
434
435 #ifdef CONFIG_SYS_DCSRBAR_PHYS
436 /* set DCSRCR so that DCSR space is 1G */
437 setbits_be32(&gur->dcsrcr, FSL_CORENET_DCSR_SZ_1G);
438 in_be32(&gur->dcsrcr);
439 #endif
440
441 #ifdef CONFIG_SYS_DCSRBAR_PHYS
442 #ifdef CONFIG_DEEP_SLEEP
443 /* disable the console if boot from deep sleep */
444 if (in_be32(&gur->scrtsr[0]) & (1 << 3))
445 gd->flags |= GD_FLG_SILENT | GD_FLG_DISABLE_CONSOLE;
446 #endif
447 #endif
448 #ifdef CONFIG_SYS_FSL_ERRATUM_A007212
449 fsl_erratum_a007212_workaround();
450 #endif
451
452 }
453
454 /* Implement a dummy function for those platforms w/o SERDES */
455 static void __fsl_serdes__init(void)
456 {
457 return ;
458 }
459 __attribute__((weak, alias("__fsl_serdes__init"))) void fsl_serdes_init(void);
460
461 #if defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2) && defined(CONFIG_E6500)
462 int enable_cluster_l2(void)
463 {
464 int i = 0;
465 u32 cluster;
466 ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
467 struct ccsr_cluster_l2 __iomem *l2cache;
468
469 cluster = in_be32(&gur->tp_cluster[i].lower);
470 if (cluster & TP_CLUSTER_EOC)
471 return 0;
472
473 /* The first cache has already been set up, so skip it */
474 i++;
475
476 /* Look through the remaining clusters, and set up their caches */
477 do {
478 int j, cluster_valid = 0;
479
480 l2cache = (void __iomem *)(CONFIG_SYS_FSL_CLUSTER_1_L2 + i * 0x40000);
481
482 cluster = in_be32(&gur->tp_cluster[i].lower);
483
484 /* check that at least one core/accel is enabled in cluster */
485 for (j = 0; j < 4; j++) {
486 u32 idx = (cluster >> (j*8)) & TP_CLUSTER_INIT_MASK;
487 u32 type = in_be32(&gur->tp_ityp[idx]);
488
489 if (type & TP_ITYP_AV)
490 cluster_valid = 1;
491 }
492
493 if (cluster_valid) {
494 /* set stash ID to (cluster) * 2 + 32 + 1 */
495 clrsetbits_be32(&l2cache->l2csr1, 0xff, 32 + i * 2 + 1);
496
497 printf("enable l2 for cluster %d %p\n", i, l2cache);
498
499 out_be32(&l2cache->l2csr0, L2CSR0_L2FI|L2CSR0_L2LFC);
500 while ((in_be32(&l2cache->l2csr0)
501 & (L2CSR0_L2FI|L2CSR0_L2LFC)) != 0)
502 ;
503 out_be32(&l2cache->l2csr0, L2CSR0_L2E|L2CSR0_L2PE|L2CSR0_L2REP_MODE);
504 }
505 i++;
506 } while (!(cluster & TP_CLUSTER_EOC));
507
508 return 0;
509 }
510 #endif
511
512 /*
513 * Initialize L2 as cache.
514 *
515 * The newer 8548, etc, parts have twice as much cache, but
516 * use the same bit-encoding as the older 8555, etc, parts.
517 *
518 */
519 int cpu_init_r(void)
520 {
521 __maybe_unused u32 svr = get_svr();
522 #ifdef CONFIG_SYS_LBC_LCRR
523 fsl_lbc_t *lbc = (void __iomem *)LBC_BASE_ADDR;
524 #endif
525 #ifdef CONFIG_L2_CACHE
526 ccsr_l2cache_t *l2cache = (void __iomem *)CONFIG_SYS_MPC85xx_L2_ADDR;
527 #elif defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2) && defined(CONFIG_E6500)
528 struct ccsr_cluster_l2 * l2cache = (void __iomem *)CONFIG_SYS_FSL_CLUSTER_1_L2;
529 #endif
530 #if defined(CONFIG_PPC_SPINTABLE_COMPATIBLE) && defined(CONFIG_MP)
531 extern int spin_table_compat;
532 const char *spin;
533 #endif
534 #ifdef CONFIG_SYS_FSL_ERRATUM_SEC_A003571
535 ccsr_sec_t __iomem *sec = (void *)CONFIG_SYS_FSL_SEC_ADDR;
536 #endif
537 #if defined(CONFIG_SYS_P4080_ERRATUM_CPU22) || \
538 defined(CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011)
539 /*
540 * CPU22 and NMG_CPU_A011 share the same workaround.
541 * CPU22 applies to P4080 rev 1.0, 2.0, fixed in 3.0
542 * NMG_CPU_A011 applies to P4080 rev 1.0, 2.0, fixed in 3.0
543 * also applies to P3041 rev 1.0, 1.1, P2041 rev 1.0, 1.1, both
544 * fixed in 2.0. NMG_CPU_A011 is activated by default and can
545 * be disabled by hwconfig with syntax:
546 *
547 * fsl_cpu_a011:disable
548 */
549 extern int enable_cpu_a011_workaround;
550 #ifdef CONFIG_SYS_P4080_ERRATUM_CPU22
551 enable_cpu_a011_workaround = (SVR_MAJ(svr) < 3);
552 #else
553 char buffer[HWCONFIG_BUFFER_SIZE];
554 char *buf = NULL;
555 int n, res;
556
557 n = getenv_f("hwconfig", buffer, sizeof(buffer));
558 if (n > 0)
559 buf = buffer;
560
561 res = hwconfig_arg_cmp_f("fsl_cpu_a011", "disable", buf);
562 if (res > 0)
563 enable_cpu_a011_workaround = 0;
564 else {
565 if (n >= HWCONFIG_BUFFER_SIZE) {
566 printf("fsl_cpu_a011 was not found. hwconfig variable "
567 "may be too long\n");
568 }
569 enable_cpu_a011_workaround =
570 (SVR_SOC_VER(svr) == SVR_P4080 && SVR_MAJ(svr) < 3) ||
571 (SVR_SOC_VER(svr) != SVR_P4080 && SVR_MAJ(svr) < 2);
572 }
573 #endif
574 if (enable_cpu_a011_workaround) {
575 flush_dcache();
576 mtspr(L1CSR2, (mfspr(L1CSR2) | L1CSR2_DCWS));
577 sync();
578 }
579 #endif
580 #ifdef CONFIG_SYS_FSL_ERRATUM_A005812
581 /*
582 * A-005812 workaround sets bit 32 of SPR 976 for SoCs running
583 * in write shadow mode. Checking DCWS before setting SPR 976.
584 */
585 if (mfspr(L1CSR2) & L1CSR2_DCWS)
586 mtspr(SPRN_HDBCR0, (mfspr(SPRN_HDBCR0) | 0x80000000));
587 #endif
588
589 #if defined(CONFIG_PPC_SPINTABLE_COMPATIBLE) && defined(CONFIG_MP)
590 spin = getenv("spin_table_compat");
591 if (spin && (*spin == 'n'))
592 spin_table_compat = 0;
593 else
594 spin_table_compat = 1;
595 #endif
596
597 puts ("L2: ");
598
599 #if defined(CONFIG_L2_CACHE)
600 volatile uint cache_ctl;
601 uint ver;
602 u32 l2siz_field;
603
604 ver = SVR_SOC_VER(svr);
605
606 asm("msync;isync");
607 cache_ctl = l2cache->l2ctl;
608
609 #if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L2_ADDR)
610 if (cache_ctl & MPC85xx_L2CTL_L2E) {
611 /* Clear L2 SRAM memory-mapped base address */
612 out_be32(&l2cache->l2srbar0, 0x0);
613 out_be32(&l2cache->l2srbar1, 0x0);
614
615 /* set MBECCDIS=0, SBECCDIS=0 */
616 clrbits_be32(&l2cache->l2errdis,
617 (MPC85xx_L2ERRDIS_MBECC |
618 MPC85xx_L2ERRDIS_SBECC));
619
620 /* set L2E=0, L2SRAM=0 */
621 clrbits_be32(&l2cache->l2ctl,
622 (MPC85xx_L2CTL_L2E |
623 MPC85xx_L2CTL_L2SRAM_ENTIRE));
624 }
625 #endif
626
627 l2siz_field = (cache_ctl >> 28) & 0x3;
628
629 switch (l2siz_field) {
630 case 0x0:
631 printf(" unknown size (0x%08x)\n", cache_ctl);
632 return -1;
633 break;
634 case 0x1:
635 if (ver == SVR_8540 || ver == SVR_8560 ||
636 ver == SVR_8541 || ver == SVR_8555) {
637 puts("128 KiB ");
638 /* set L2E=1, L2I=1, & L2BLKSZ=1 (128 KiBibyte) */
639 cache_ctl = 0xc4000000;
640 } else {
641 puts("256 KiB ");
642 cache_ctl = 0xc0000000; /* set L2E=1, L2I=1, & L2SRAM=0 */
643 }
644 break;
645 case 0x2:
646 if (ver == SVR_8540 || ver == SVR_8560 ||
647 ver == SVR_8541 || ver == SVR_8555) {
648 puts("256 KiB ");
649 /* set L2E=1, L2I=1, & L2BLKSZ=2 (256 KiBibyte) */
650 cache_ctl = 0xc8000000;
651 } else {
652 puts("512 KiB ");
653 /* set L2E=1, L2I=1, & L2SRAM=0 */
654 cache_ctl = 0xc0000000;
655 }
656 break;
657 case 0x3:
658 puts("1024 KiB ");
659 /* set L2E=1, L2I=1, & L2SRAM=0 */
660 cache_ctl = 0xc0000000;
661 break;
662 }
663
664 if (l2cache->l2ctl & MPC85xx_L2CTL_L2E) {
665 puts("already enabled");
666 #if defined(CONFIG_SYS_INIT_L2_ADDR) && defined(CONFIG_SYS_FLASH_BASE)
667 u32 l2srbar = l2cache->l2srbar0;
668 if (l2cache->l2ctl & MPC85xx_L2CTL_L2SRAM_ENTIRE
669 && l2srbar >= CONFIG_SYS_FLASH_BASE) {
670 l2srbar = CONFIG_SYS_INIT_L2_ADDR;
671 l2cache->l2srbar0 = l2srbar;
672 printf(", moving to 0x%08x", CONFIG_SYS_INIT_L2_ADDR);
673 }
674 #endif /* CONFIG_SYS_INIT_L2_ADDR */
675 puts("\n");
676 } else {
677 asm("msync;isync");
678 l2cache->l2ctl = cache_ctl; /* invalidate & enable */
679 asm("msync;isync");
680 puts("enabled\n");
681 }
682 #elif defined(CONFIG_BACKSIDE_L2_CACHE)
683 if (SVR_SOC_VER(svr) == SVR_P2040) {
684 puts("N/A\n");
685 goto skip_l2;
686 }
687
688 u32 l2cfg0 = mfspr(SPRN_L2CFG0);
689
690 /* invalidate the L2 cache */
691 mtspr(SPRN_L2CSR0, (L2CSR0_L2FI|L2CSR0_L2LFC));
692 while (mfspr(SPRN_L2CSR0) & (L2CSR0_L2FI|L2CSR0_L2LFC))
693 ;
694
695 #ifdef CONFIG_SYS_CACHE_STASHING
696 /* set stash id to (coreID) * 2 + 32 + L2 (1) */
697 mtspr(SPRN_L2CSR1, (32 + 1));
698 #endif
699
700 /* enable the cache */
701 mtspr(SPRN_L2CSR0, CONFIG_SYS_INIT_L2CSR0);
702
703 if (CONFIG_SYS_INIT_L2CSR0 & L2CSR0_L2E) {
704 while (!(mfspr(SPRN_L2CSR0) & L2CSR0_L2E))
705 ;
706 print_size((l2cfg0 & 0x3fff) * 64 * 1024, " enabled\n");
707 }
708
709 skip_l2:
710 #elif defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2) && defined(CONFIG_E6500)
711 if (l2cache->l2csr0 & L2CSR0_L2E)
712 print_size((l2cache->l2cfg0 & 0x3fff) * 64 * 1024,
713 " enabled\n");
714
715 enable_cluster_l2();
716 #else
717 puts("disabled\n");
718 #endif
719
720 #if defined(CONFIG_RAMBOOT_PBL)
721 disable_cpc_sram();
722 #endif
723 enable_cpc();
724
725 #ifndef CONFIG_SYS_FSL_NO_SERDES
726 /* needs to be in ram since code uses global static vars */
727 fsl_serdes_init();
728 #endif
729
730 #ifdef CONFIG_SYS_FSL_ERRATUM_SEC_A003571
731 #define MCFGR_AXIPIPE 0x000000f0
732 if (IS_SVR_REV(svr, 1, 0))
733 clrbits_be32(&sec->mcfgr, MCFGR_AXIPIPE);
734 #endif
735
736 #ifdef CONFIG_SYS_FSL_ERRATUM_A005871
737 if (IS_SVR_REV(svr, 1, 0)) {
738 int i;
739 __be32 *p = (void __iomem *)CONFIG_SYS_DCSRBAR + 0xb004c;
740
741 for (i = 0; i < 12; i++) {
742 p += i + (i > 5 ? 11 : 0);
743 out_be32(p, 0x2);
744 }
745 p = (void __iomem *)CONFIG_SYS_DCSRBAR + 0xb0108;
746 out_be32(p, 0x34);
747 }
748 #endif
749
750 #ifdef CONFIG_SYS_SRIO
751 srio_init();
752 #ifdef CONFIG_SRIO_PCIE_BOOT_MASTER
753 char *s = getenv("bootmaster");
754 if (s) {
755 if (!strcmp(s, "SRIO1")) {
756 srio_boot_master(1);
757 srio_boot_master_release_slave(1);
758 }
759 if (!strcmp(s, "SRIO2")) {
760 srio_boot_master(2);
761 srio_boot_master_release_slave(2);
762 }
763 }
764 #endif
765 #endif
766
767 #if defined(CONFIG_MP)
768 setup_mp();
769 #endif
770
771 #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC13
772 {
773 if (SVR_MAJ(svr) < 3) {
774 void *p;
775 p = (void *)CONFIG_SYS_DCSRBAR + 0x20520;
776 setbits_be32(p, 1 << (31 - 14));
777 }
778 }
779 #endif
780
781 #ifdef CONFIG_SYS_LBC_LCRR
782 /*
783 * Modify the CLKDIV field of LCRR register to improve the writing
784 * speed for NOR flash.
785 */
786 clrsetbits_be32(&lbc->lcrr, LCRR_CLKDIV, CONFIG_SYS_LBC_LCRR);
787 __raw_readl(&lbc->lcrr);
788 isync();
789 #ifdef CONFIG_SYS_FSL_ERRATUM_NMG_LBC103
790 udelay(100);
791 #endif
792 #endif
793
794 #ifdef CONFIG_SYS_FSL_USB1_PHY_ENABLE
795 {
796 struct ccsr_usb_phy __iomem *usb_phy1 =
797 (void *)CONFIG_SYS_MPC85xx_USB1_PHY_ADDR;
798 #ifdef CONFIG_SYS_FSL_ERRATUM_A006261
799 if (has_erratum_a006261())
800 fsl_erratum_a006261_workaround(usb_phy1);
801 #endif
802 out_be32(&usb_phy1->usb_enable_override,
803 CONFIG_SYS_FSL_USB_ENABLE_OVERRIDE);
804 }
805 #endif
806 #ifdef CONFIG_SYS_FSL_USB2_PHY_ENABLE
807 {
808 struct ccsr_usb_phy __iomem *usb_phy2 =
809 (void *)CONFIG_SYS_MPC85xx_USB2_PHY_ADDR;
810 #ifdef CONFIG_SYS_FSL_ERRATUM_A006261
811 if (has_erratum_a006261())
812 fsl_erratum_a006261_workaround(usb_phy2);
813 #endif
814 out_be32(&usb_phy2->usb_enable_override,
815 CONFIG_SYS_FSL_USB_ENABLE_OVERRIDE);
816 }
817 #endif
818
819 #ifdef CONFIG_SYS_FSL_ERRATUM_USB14
820 /* On P204x/P304x/P50x0 Rev1.0, USB transmit will result internal
821 * multi-bit ECC errors which has impact on performance, so software
822 * should disable all ECC reporting from USB1 and USB2.
823 */
824 if (IS_SVR_REV(get_svr(), 1, 0)) {
825 struct dcsr_dcfg_regs *dcfg = (struct dcsr_dcfg_regs *)
826 (CONFIG_SYS_DCSRBAR + CONFIG_SYS_DCSR_DCFG_OFFSET);
827 setbits_be32(&dcfg->ecccr1,
828 (DCSR_DCFG_ECC_DISABLE_USB1 |
829 DCSR_DCFG_ECC_DISABLE_USB2));
830 }
831 #endif
832
833 #if defined(CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE)
834 struct ccsr_usb_phy __iomem *usb_phy =
835 (void *)CONFIG_SYS_MPC85xx_USB1_PHY_ADDR;
836 setbits_be32(&usb_phy->pllprg[1],
837 CONFIG_SYS_FSL_USB_PLLPRG2_PHY2_CLK_EN |
838 CONFIG_SYS_FSL_USB_PLLPRG2_PHY1_CLK_EN |
839 CONFIG_SYS_FSL_USB_PLLPRG2_MFI |
840 CONFIG_SYS_FSL_USB_PLLPRG2_PLL_EN);
841 #ifdef CONFIG_SYS_FSL_SINGLE_SOURCE_CLK
842 usb_single_source_clk_configure(usb_phy);
843 #endif
844 setbits_be32(&usb_phy->port1.ctrl,
845 CONFIG_SYS_FSL_USB_CTRL_PHY_EN);
846 setbits_be32(&usb_phy->port1.drvvbuscfg,
847 CONFIG_SYS_FSL_USB_DRVVBUS_CR_EN);
848 setbits_be32(&usb_phy->port1.pwrfltcfg,
849 CONFIG_SYS_FSL_USB_PWRFLT_CR_EN);
850 setbits_be32(&usb_phy->port2.ctrl,
851 CONFIG_SYS_FSL_USB_CTRL_PHY_EN);
852 setbits_be32(&usb_phy->port2.drvvbuscfg,
853 CONFIG_SYS_FSL_USB_DRVVBUS_CR_EN);
854 setbits_be32(&usb_phy->port2.pwrfltcfg,
855 CONFIG_SYS_FSL_USB_PWRFLT_CR_EN);
856
857 #ifdef CONFIG_SYS_FSL_ERRATUM_A006261
858 if (has_erratum_a006261())
859 fsl_erratum_a006261_workaround(usb_phy);
860 #endif
861
862 #endif /* CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE */
863
864 #ifdef CONFIG_FMAN_ENET
865 fman_enet_init();
866 #endif
867
868 #if defined(CONFIG_FSL_SATA_V2) && defined(CONFIG_FSL_SATA_ERRATUM_A001)
869 /*
870 * For P1022/1013 Rev1.0 silicon, after power on SATA host
871 * controller is configured in legacy mode instead of the
872 * expected enterprise mode. Software needs to clear bit[28]
873 * of HControl register to change to enterprise mode from
874 * legacy mode. We assume that the controller is offline.
875 */
876 if (IS_SVR_REV(svr, 1, 0) &&
877 ((SVR_SOC_VER(svr) == SVR_P1022) ||
878 (SVR_SOC_VER(svr) == SVR_P1013))) {
879 fsl_sata_reg_t *reg;
880
881 /* first SATA controller */
882 reg = (void *)CONFIG_SYS_MPC85xx_SATA1_ADDR;
883 clrbits_le32(&reg->hcontrol, HCONTROL_ENTERPRISE_EN);
884
885 /* second SATA controller */
886 reg = (void *)CONFIG_SYS_MPC85xx_SATA2_ADDR;
887 clrbits_le32(&reg->hcontrol, HCONTROL_ENTERPRISE_EN);
888 }
889 #endif
890
891
892 return 0;
893 }
894
895 void arch_preboot_os(void)
896 {
897 u32 msr;
898
899 /*
900 * We are changing interrupt offsets and are about to boot the OS so
901 * we need to make sure we disable all async interrupts. EE is already
902 * disabled by the time we get called.
903 */
904 msr = mfmsr();
905 msr &= ~(MSR_ME|MSR_CE);
906 mtmsr(msr);
907 }
908
909 #if defined(CONFIG_CMD_SATA) && defined(CONFIG_FSL_SATA)
910 int sata_initialize(void)
911 {
912 if (is_serdes_configured(SATA1) || is_serdes_configured(SATA2))
913 return __sata_initialize();
914
915 return 1;
916 }
917 #endif
918
919 void cpu_secondary_init_r(void)
920 {
921 #ifdef CONFIG_U_QE
922 uint qe_base = CONFIG_SYS_IMMR + 0x00140000; /* QE immr base */
923 #elif defined CONFIG_QE
924 uint qe_base = CONFIG_SYS_IMMR + 0x00080000; /* QE immr base */
925 #endif
926
927 #ifdef CONFIG_QE
928 qe_init(qe_base);
929 qe_reset();
930 #endif
931 }
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