2 * Copyright 2007-2010 Freescale Semiconductor, Inc.
5 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
7 * See file CREDITS for list of people who contributed to this
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
28 #include <fdt_support.h>
29 #include <asm/processor.h>
30 #include <linux/ctype.h>
32 #include <asm/fsl_portals.h>
33 #ifdef CONFIG_FSL_ESDHC
34 #include <fsl_esdhc.h>
37 DECLARE_GLOBAL_DATA_PTR
;
39 extern void ft_qe_setup(void *blob
);
40 extern void ft_fixup_num_cores(void *blob
);
45 void ft_fixup_cpu(void *blob
, u64 memory_limit
)
48 ulong spin_tbl_addr
= get_spin_phys_addr();
49 u32 bootpg
= determine_mp_bootpg();
51 const char *enable_method
;
53 off
= fdt_node_offset_by_prop_value(blob
, -1, "device_type", "cpu", 4);
54 while (off
!= -FDT_ERR_NOTFOUND
) {
55 u32
*reg
= (u32
*)fdt_getprop(blob
, off
, "reg", 0);
58 u64 val
= *reg
* SIZE_BOOT_ENTRY
+ spin_tbl_addr
;
59 val
= cpu_to_fdt32(val
);
61 fdt_setprop_string(blob
, off
, "status",
64 fdt_setprop_string(blob
, off
, "status",
68 if (hold_cores_in_reset(0)) {
69 #ifdef CONFIG_FSL_CORENET
70 /* Cores held in reset, use BRR to release */
71 enable_method
= "fsl,brr-holdoff";
73 /* Cores held in reset, use EEBPCR to release */
74 enable_method
= "fsl,eebpcr-holdoff";
77 /* Cores out of reset and in a spin-loop */
78 enable_method
= "spin-table";
80 fdt_setprop(blob
, off
, "cpu-release-addr",
84 fdt_setprop_string(blob
, off
, "enable-method",
87 printf ("cpu NULL\n");
89 off
= fdt_node_offset_by_prop_value(blob
, off
,
90 "device_type", "cpu", 4);
93 /* Reserve the boot page so OSes dont use it */
94 if ((u64
)bootpg
< memory_limit
) {
95 off
= fdt_add_mem_rsv(blob
, bootpg
, (u64
)4096);
97 printf("%s: %s\n", __FUNCTION__
, fdt_strerror(off
));
102 #ifdef CONFIG_SYS_FSL_CPC
103 static inline void ft_fixup_l3cache(void *blob
, int off
)
105 u32 line_size
, num_ways
, size
, num_sets
;
106 cpc_corenet_t
*cpc
= (void *)CONFIG_SYS_FSL_CPC_ADDR
;
107 u32 cfg0
= in_be32(&cpc
->cpccfg0
);
109 size
= CPC_CFG0_SZ_K(cfg0
) * 1024 * CONFIG_SYS_NUM_CPC
;
110 num_ways
= CPC_CFG0_NUM_WAYS(cfg0
);
111 line_size
= CPC_CFG0_LINE_SZ(cfg0
);
112 num_sets
= size
/ (line_size
* num_ways
);
114 fdt_setprop(blob
, off
, "cache-unified", NULL
, 0);
115 fdt_setprop_cell(blob
, off
, "cache-block-size", line_size
);
116 fdt_setprop_cell(blob
, off
, "cache-size", size
);
117 fdt_setprop_cell(blob
, off
, "cache-sets", num_sets
);
118 fdt_setprop_cell(blob
, off
, "cache-level", 3);
119 #ifdef CONFIG_SYS_CACHE_STASHING
120 fdt_setprop_cell(blob
, off
, "cache-stash-id", 1);
124 #define ft_fixup_l3cache(x, y)
127 #if defined(CONFIG_L2_CACHE)
128 /* return size in kilobytes */
129 static inline u32
l2cache_size(void)
131 volatile ccsr_l2cache_t
*l2cache
= (void *)CONFIG_SYS_MPC85xx_L2_ADDR
;
132 volatile u32 l2siz_field
= (l2cache
->l2ctl
>> 28) & 0x3;
133 u32 ver
= SVR_SOC_VER(get_svr());
135 switch (l2siz_field
) {
139 if (ver
== SVR_8540
|| ver
== SVR_8560
||
140 ver
== SVR_8541
|| ver
== SVR_8541_E
||
141 ver
== SVR_8555
|| ver
== SVR_8555_E
)
147 if (ver
== SVR_8540
|| ver
== SVR_8560
||
148 ver
== SVR_8541
|| ver
== SVR_8541_E
||
149 ver
== SVR_8555
|| ver
== SVR_8555_E
)
162 static inline void ft_fixup_l2cache(void *blob
)
166 struct cpu_type
*cpu
= identify_cpu(SVR_SOC_VER(get_svr()));
169 const u32 line_size
= 32;
170 const u32 num_ways
= 8;
171 const u32 size
= l2cache_size() * 1024;
172 const u32 num_sets
= size
/ (line_size
* num_ways
);
174 off
= fdt_node_offset_by_prop_value(blob
, -1, "device_type", "cpu", 4);
176 debug("no cpu node fount\n");
180 ph
= (u32
*)fdt_getprop(blob
, off
, "next-level-cache", 0);
183 debug("no next-level-cache property\n");
187 off
= fdt_node_offset_by_phandle(blob
, *ph
);
189 printf("%s: %s\n", __func__
, fdt_strerror(off
));
194 if (isdigit(cpu
->name
[0]))
195 len
= sprintf(compat_buf
,
196 "fsl,mpc%s-l2-cache-controller", cpu
->name
);
198 len
= sprintf(compat_buf
,
199 "fsl,%c%s-l2-cache-controller",
200 tolower(cpu
->name
[0]), cpu
->name
+ 1);
202 sprintf(&compat_buf
[len
+ 1], "cache");
204 fdt_setprop(blob
, off
, "cache-unified", NULL
, 0);
205 fdt_setprop_cell(blob
, off
, "cache-block-size", line_size
);
206 fdt_setprop_cell(blob
, off
, "cache-size", size
);
207 fdt_setprop_cell(blob
, off
, "cache-sets", num_sets
);
208 fdt_setprop_cell(blob
, off
, "cache-level", 2);
209 fdt_setprop(blob
, off
, "compatible", compat_buf
, sizeof(compat_buf
));
211 /* we dont bother w/L3 since no platform of this type has one */
213 #elif defined(CONFIG_BACKSIDE_L2_CACHE)
214 static inline void ft_fixup_l2cache(void *blob
)
216 int off
, l2_off
, l3_off
= -1;
218 u32 l2cfg0
= mfspr(SPRN_L2CFG0
);
219 u32 size
, line_size
, num_ways
, num_sets
;
221 size
= (l2cfg0
& 0x3fff) * 64 * 1024;
222 num_ways
= ((l2cfg0
>> 14) & 0x1f) + 1;
223 line_size
= (((l2cfg0
>> 23) & 0x3) + 1) * 32;
224 num_sets
= size
/ (line_size
* num_ways
);
226 off
= fdt_node_offset_by_prop_value(blob
, -1, "device_type", "cpu", 4);
228 while (off
!= -FDT_ERR_NOTFOUND
) {
229 ph
= (u32
*)fdt_getprop(blob
, off
, "next-level-cache", 0);
232 debug("no next-level-cache property\n");
236 l2_off
= fdt_node_offset_by_phandle(blob
, *ph
);
238 printf("%s: %s\n", __func__
, fdt_strerror(off
));
242 #ifdef CONFIG_SYS_CACHE_STASHING
244 u32
*reg
= (u32
*)fdt_getprop(blob
, off
, "reg", 0);
246 fdt_setprop_cell(blob
, l2_off
, "cache-stash-id",
247 (*reg
* 2) + 32 + 1);
251 fdt_setprop(blob
, l2_off
, "cache-unified", NULL
, 0);
252 fdt_setprop_cell(blob
, l2_off
, "cache-block-size", line_size
);
253 fdt_setprop_cell(blob
, l2_off
, "cache-size", size
);
254 fdt_setprop_cell(blob
, l2_off
, "cache-sets", num_sets
);
255 fdt_setprop_cell(blob
, l2_off
, "cache-level", 2);
256 fdt_setprop(blob
, l2_off
, "compatible", "cache", 6);
259 ph
= (u32
*)fdt_getprop(blob
, l2_off
, "next-level-cache", 0);
262 debug("no next-level-cache property\n");
268 off
= fdt_node_offset_by_prop_value(blob
, off
,
269 "device_type", "cpu", 4);
272 l3_off
= fdt_node_offset_by_phandle(blob
, l3_off
);
274 printf("%s: %s\n", __func__
, fdt_strerror(off
));
277 ft_fixup_l3cache(blob
, l3_off
);
281 #define ft_fixup_l2cache(x)
284 static inline void ft_fixup_cache(void *blob
)
288 off
= fdt_node_offset_by_prop_value(blob
, -1, "device_type", "cpu", 4);
290 while (off
!= -FDT_ERR_NOTFOUND
) {
291 u32 l1cfg0
= mfspr(SPRN_L1CFG0
);
292 u32 l1cfg1
= mfspr(SPRN_L1CFG1
);
293 u32 isize
, iline_size
, inum_sets
, inum_ways
;
294 u32 dsize
, dline_size
, dnum_sets
, dnum_ways
;
297 dsize
= (l1cfg0
& 0x7ff) * 1024;
298 dnum_ways
= ((l1cfg0
>> 11) & 0xff) + 1;
299 dline_size
= (((l1cfg0
>> 23) & 0x3) + 1) * 32;
300 dnum_sets
= dsize
/ (dline_size
* dnum_ways
);
302 fdt_setprop_cell(blob
, off
, "d-cache-block-size", dline_size
);
303 fdt_setprop_cell(blob
, off
, "d-cache-size", dsize
);
304 fdt_setprop_cell(blob
, off
, "d-cache-sets", dnum_sets
);
306 #ifdef CONFIG_SYS_CACHE_STASHING
308 u32
*reg
= (u32
*)fdt_getprop(blob
, off
, "reg", 0);
310 fdt_setprop_cell(blob
, off
, "cache-stash-id",
311 (*reg
* 2) + 32 + 0);
316 isize
= (l1cfg1
& 0x7ff) * 1024;
317 inum_ways
= ((l1cfg1
>> 11) & 0xff) + 1;
318 iline_size
= (((l1cfg1
>> 23) & 0x3) + 1) * 32;
319 inum_sets
= isize
/ (iline_size
* inum_ways
);
321 fdt_setprop_cell(blob
, off
, "i-cache-block-size", iline_size
);
322 fdt_setprop_cell(blob
, off
, "i-cache-size", isize
);
323 fdt_setprop_cell(blob
, off
, "i-cache-sets", inum_sets
);
325 off
= fdt_node_offset_by_prop_value(blob
, off
,
326 "device_type", "cpu", 4);
329 ft_fixup_l2cache(blob
);
333 void fdt_add_enet_stashing(void *fdt
)
335 do_fixup_by_compat(fdt
, "gianfar", "bd-stash", NULL
, 0, 1);
337 do_fixup_by_compat_u32(fdt
, "gianfar", "rx-stash-len", 96, 1);
339 do_fixup_by_compat_u32(fdt
, "gianfar", "rx-stash-idx", 0, 1);
342 #if defined(CONFIG_SYS_DPAA_FMAN) || defined(CONFIG_SYS_DPAA_PME)
343 static void ft_fixup_clks(void *blob
, const char *compat
, u32 offset
,
346 phys_addr_t phys
= offset
+ CONFIG_SYS_CCSRBAR_PHYS
;
347 int off
= fdt_node_offset_by_compat_reg(blob
, compat
, phys
);
350 off
= fdt_setprop_cell(blob
, off
, "clock-frequency", freq
);
352 printf("WARNING enable to set clock-frequency "
353 "for %s: %s\n", compat
, fdt_strerror(off
));
357 static void ft_fixup_dpaa_clks(void *blob
)
361 get_sys_info(&sysinfo
);
362 ft_fixup_clks(blob
, "fsl,fman", CONFIG_SYS_FSL_FM1_OFFSET
,
363 sysinfo
.freqFMan
[0]);
365 #if (CONFIG_SYS_NUM_FMAN == 2)
366 ft_fixup_clks(blob
, "fsl,fman", CONFIG_SYS_FSL_FM2_OFFSET
,
367 sysinfo
.freqFMan
[1]);
370 #ifdef CONFIG_SYS_DPAA_PME
371 do_fixup_by_compat_u32(blob
, "fsl,pme",
372 "clock-frequency", sysinfo
.freqPME
, 1);
376 #define ft_fixup_dpaa_clks(x)
380 static void ft_fixup_qe_snum(void *blob
)
384 svr
= mfspr(SPRN_SVR
);
385 if (SVR_SOC_VER(svr
) == SVR_8569_E
) {
386 if(IS_SVR_REV(svr
, 1, 0))
387 do_fixup_by_compat_u32(blob
, "fsl,qe",
388 "fsl,qe-num-snums", 46, 1);
390 do_fixup_by_compat_u32(blob
, "fsl,qe",
391 "fsl,qe-num-snums", 76, 1);
396 void ft_cpu_setup(void *blob
, bd_t
*bd
)
402 /* delete crypto node if not on an E-processor */
403 if (!IS_E_PROCESSOR(get_svr()))
404 fdt_fixup_crypto_node(blob
, 0);
406 fdt_fixup_ethernet(blob
);
408 fdt_add_enet_stashing(blob
);
410 do_fixup_by_prop_u32(blob
, "device_type", "cpu", 4,
411 "timebase-frequency", get_tbclk(), 1);
412 do_fixup_by_prop_u32(blob
, "device_type", "cpu", 4,
413 "bus-frequency", bd
->bi_busfreq
, 1);
414 get_sys_info(&sysinfo
);
415 off
= fdt_node_offset_by_prop_value(blob
, -1, "device_type", "cpu", 4);
416 while (off
!= -FDT_ERR_NOTFOUND
) {
417 u32
*reg
= (u32
*)fdt_getprop(blob
, off
, "reg", 0);
418 val
= cpu_to_fdt32(sysinfo
.freqProcessor
[*reg
]);
419 fdt_setprop(blob
, off
, "clock-frequency", &val
, 4);
420 off
= fdt_node_offset_by_prop_value(blob
, off
, "device_type",
423 do_fixup_by_prop_u32(blob
, "device_type", "soc", 4,
424 "bus-frequency", bd
->bi_busfreq
, 1);
426 do_fixup_by_compat_u32(blob
, "fsl,pq3-localbus",
427 "bus-frequency", gd
->lbc_clk
, 1);
428 do_fixup_by_compat_u32(blob
, "fsl,elbc",
429 "bus-frequency", gd
->lbc_clk
, 1);
432 ft_fixup_qe_snum(blob
);
435 #ifdef CONFIG_SYS_NS16550
436 do_fixup_by_compat_u32(blob
, "ns16550",
437 "clock-frequency", CONFIG_SYS_NS16550_CLK
, 1);
441 do_fixup_by_compat_u32(blob
, "fsl,cpm2-scc-uart",
442 "current-speed", bd
->bi_baudrate
, 1);
444 do_fixup_by_compat_u32(blob
, "fsl,cpm2-brg",
445 "clock-frequency", bd
->bi_brgfreq
, 1);
448 #ifdef CONFIG_FSL_CORENET
449 do_fixup_by_compat_u32(blob
, "fsl,qoriq-clockgen-1.0",
450 "clock-frequency", CONFIG_SYS_CLK_FREQ
, 1);
453 fdt_fixup_memory(blob
, (u64
)bd
->bi_memstart
, (u64
)bd
->bi_memsize
);
456 ft_fixup_cpu(blob
, (u64
)bd
->bi_memstart
+ (u64
)bd
->bi_memsize
);
457 ft_fixup_num_cores(blob
);
460 ft_fixup_cache(blob
);
462 #if defined(CONFIG_FSL_ESDHC)
463 fdt_fixup_esdhc(blob
, bd
);
466 ft_fixup_dpaa_clks(blob
);
468 #if defined(CONFIG_SYS_BMAN_MEM_PHYS)
469 fdt_portal(blob
, "fsl,bman-portal", "bman-portals",
470 (u64
)CONFIG_SYS_BMAN_MEM_PHYS
,
471 CONFIG_SYS_BMAN_MEM_SIZE
);
474 #if defined(CONFIG_SYS_QMAN_MEM_PHYS)
475 fdt_portal(blob
, "fsl,qman-portal", "qman-portals",
476 (u64
)CONFIG_SYS_QMAN_MEM_PHYS
,
477 CONFIG_SYS_QMAN_MEM_SIZE
);
479 fdt_fixup_qportals(blob
);