arch/powerpc/cpu/mpc85xx/fsl_corenet2_serdes.c

   1 /*
   2  * Copyright 2012 Freescale Semiconductor, Inc.
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 #include <common.h>
   8 #include <asm/fsl_serdes.h>
   9 #include <asm/immap_85xx.h>
  10 #include <asm/io.h>
  11 #include <asm/processor.h>
  12 #include <asm/fsl_law.h>
  13 #include <asm/errno.h>
  14 #include "fsl_corenet2_serdes.h"
  15
  16 static u64 serdes1_prtcl_map;
  17 static u64 serdes2_prtcl_map;
  18 #ifdef CONFIG_SYS_FSL_SRDS_3
  19 static u64 serdes3_prtcl_map;
  20 #endif
  21 #ifdef CONFIG_SYS_FSL_SRDS_4
  22 static u64 serdes4_prtcl_map;
  23 #endif
  24
  25 #ifdef DEBUG
  26 static const char *serdes_prtcl_str[] = {
  27         [NONE] = "NA",
  28         [PCIE1] = "PCIE1",
  29         [PCIE2] = "PCIE2",
  30         [PCIE3] = "PCIE3",
  31         [PCIE4] = "PCIE4",
  32         [SATA1] = "SATA1",
  33         [SATA2] = "SATA2",
  34         [SRIO1] = "SRIO1",
  35         [SRIO2] = "SRIO2",
  36         [SGMII_FM1_DTSEC1] = "SGMII_FM1_DTSEC1",
  37         [SGMII_FM1_DTSEC2] = "SGMII_FM1_DTSEC2",
  38         [SGMII_FM1_DTSEC3] = "SGMII_FM1_DTSEC3",
  39         [SGMII_FM1_DTSEC4] = "SGMII_FM1_DTSEC4",
  40         [SGMII_FM1_DTSEC5] = "SGMII_FM1_DTSEC5",
  41         [SGMII_FM1_DTSEC6] = "SGMII_FM1_DTSEC6",
  42         [SGMII_FM2_DTSEC1] = "SGMII_FM2_DTSEC1",
  43         [SGMII_FM2_DTSEC2] = "SGMII_FM2_DTSEC2",
  44         [SGMII_FM2_DTSEC3] = "SGMII_FM2_DTSEC3",
  45         [SGMII_FM2_DTSEC4] = "SGMII_FM2_DTSEC4",
  46         [XAUI_FM1] = "XAUI_FM1",
  47         [XAUI_FM2] = "XAUI_FM2",
  48         [AURORA] = "DEBUG",
  49         [CPRI1] = "CPRI1",
  50         [CPRI2] = "CPRI2",
  51         [CPRI3] = "CPRI3",
  52         [CPRI4] = "CPRI4",
  53         [CPRI5] = "CPRI5",
  54         [CPRI6] = "CPRI6",
  55         [CPRI7] = "CPRI7",
  56         [CPRI8] = "CPRI8",
  57         [XAUI_FM1_MAC9] = "XAUI_FM1_MAC9",
  58         [XAUI_FM1_MAC10] = "XAUI_FM1_MAC10",
  59         [XAUI_FM2_MAC9] = "XAUI_FM2_MAC9",
  60         [XAUI_FM2_MAC10] = "XAUI_FM2_MAC10",
  61         [HIGIG_FM1_MAC9] = "HiGig_FM1_MAC9",
  62         [HIGIG_FM1_MAC10] = "HiGig_FM1_MAC10",
  63         [HIGIG_FM2_MAC9] = "HiGig_FM2_MAC9",
  64         [HIGIG_FM2_MAC10] = "HiGig_FM2_MAC10",
  65         [QSGMII_FM1_A] = "QSGMII_FM1_A",
  66         [QSGMII_FM1_B] = "QSGMII_FM1_B",
  67         [QSGMII_FM2_A] = "QSGMII_FM2_A",
  68         [QSGMII_FM2_B] = "QSGMII_FM2_B",
  69         [XFI_FM1_MAC9] = "XFI_FM1_MAC9",
  70         [XFI_FM1_MAC10] = "XFI_FM1_MAC10",
  71         [XFI_FM2_MAC9] = "XFI_FM2_MAC9",
  72         [XFI_FM2_MAC10] = "XFI_FM2_MAC10",
  73         [INTERLAKEN] = "INTERLAKEN",
  74 };
  75 #endif
  76
  77 int is_serdes_configured(enum srds_prtcl device)
  78 {
  79         u64 ret = 0;
  80
  81         ret |= (1ULL << device) & serdes1_prtcl_map;
  82         ret |= (1ULL << device) & serdes2_prtcl_map;
  83 #ifdef CONFIG_SYS_FSL_SRDS_3
  84         ret |= (1ULL << device) & serdes3_prtcl_map;
  85 #endif
  86 #ifdef CONFIG_SYS_FSL_SRDS_4
  87         ret |= (1ULL << device) & serdes4_prtcl_map;
  88 #endif
  89
  90         return !!ret;
  91 }
  92
  93 int serdes_get_first_lane(u32 sd, enum srds_prtcl device)
  94 {
  95         const ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
  96         u32 cfg = in_be32(&gur->rcwsr[4]);
  97         int i;
  98
  99         switch (sd) {
 100         case FSL_SRDS_1:
 101                 cfg &= FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
 102                 cfg >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
 103                 break;
 104         case FSL_SRDS_2:
 105                 cfg &= FSL_CORENET2_RCWSR4_SRDS2_PRTCL;
 106                 cfg >>= FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT;
 107                 break;
 108 #ifdef CONFIG_SYS_FSL_SRDS_3
 109         case FSL_SRDS_3:
 110                 cfg &= FSL_CORENET2_RCWSR4_SRDS3_PRTCL;
 111                 cfg >>= FSL_CORENET2_RCWSR4_SRDS3_PRTCL_SHIFT;
 112                 break;
 113 #endif
 114 #ifdef CONFIG_SYS_FSL_SRDS_4
 115         case FSL_SRDS_4:
 116                 cfg &= FSL_CORENET2_RCWSR4_SRDS4_PRTCL;
 117                 cfg >>= FSL_CORENET2_RCWSR4_SRDS4_PRTCL_SHIFT;
 118                 break;
 119 #endif
 120         default:
 121                 printf("invalid SerDes%d\n", sd);
 122                 break;
 123         }
 124         /* Is serdes enabled at all? */
 125         if (unlikely(cfg == 0))
 126                 return -ENODEV;
 127
 128         for (i = 0; i < SRDS_MAX_LANES; i++) {
 129                 if (serdes_get_prtcl(sd, cfg, i) == device)
 130                         return i;
 131         }
 132
 133         return -ENODEV;
 134 }
 135
 136 u64 serdes_init(u32 sd, u32 sd_addr, u32 sd_prctl_mask, u32 sd_prctl_shift)
 137 {
 138         ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
 139         u64 serdes_prtcl_map = 0;
 140         u32 cfg;
 141         int lane;
 142
 143         cfg = in_be32(&gur->rcwsr[4]) & sd_prctl_mask;
 144         /* Is serdes enabled at all? */
 145         if (!cfg) {
 146                 printf("SERDES%d is not enabled\n", sd + 1);
 147                 return 0;
 148         }
 149
 150         cfg >>= sd_prctl_shift;
 151         printf("Using SERDES%d Protocol: %d (0x%x)\n", sd + 1, cfg, cfg);
 152         if (!is_serdes_prtcl_valid(sd, cfg))
 153                 printf("SERDES%d[PRTCL] = 0x%x is not valid\n", sd + 1, cfg);
 154
 155         for (lane = 0; lane < SRDS_MAX_LANES; lane++) {
 156                 enum srds_prtcl lane_prtcl = serdes_get_prtcl(sd, cfg, lane);
 157                 serdes_prtcl_map |= (1ULL << lane_prtcl);
 158         }
 159
 160         return serdes_prtcl_map;
 161 }
 162
 163 void fsl_serdes_init(void)
 164 {
 165
 166         serdes1_prtcl_map = serdes_init(FSL_SRDS_1,
 167                 CONFIG_SYS_FSL_CORENET_SERDES_ADDR,
 168                 FSL_CORENET2_RCWSR4_SRDS1_PRTCL,
 169                 FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT);
 170         serdes2_prtcl_map = serdes_init(FSL_SRDS_2,
 171                 CONFIG_SYS_FSL_CORENET_SERDES_ADDR + FSL_SRDS_2 * 0x1000,
 172                 FSL_CORENET2_RCWSR4_SRDS2_PRTCL,
 173                 FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT);
 174 #ifdef CONFIG_SYS_FSL_SRDS_3
 175         serdes3_prtcl_map = serdes_init(FSL_SRDS_3,
 176                 CONFIG_SYS_FSL_CORENET_SERDES_ADDR + FSL_SRDS_3 * 0x1000,
 177                 FSL_CORENET2_RCWSR4_SRDS3_PRTCL,
 178                 FSL_CORENET2_RCWSR4_SRDS3_PRTCL_SHIFT);
 179 #endif
 180 #ifdef CONFIG_SYS_FSL_SRDS_4
 181         serdes4_prtcl_map = serdes_init(FSL_SRDS_4,
 182                 CONFIG_SYS_FSL_CORENET_SERDES_ADDR + FSL_SRDS_4 * 0x1000,
 183                 FSL_CORENET2_RCWSR4_SRDS4_PRTCL,
 184                 FSL_CORENET2_RCWSR4_SRDS4_PRTCL_SHIFT);
 185 #endif
 186
 187 }