arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c

   1 /*
   2  * Copyright 2009-2011 Freescale Semiconductor, Inc.
   3  *
   4  * See file CREDITS for list of people who contributed to this
   5  * project.
   6  *
   7  * This program is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU General Public License as
   9  * published by the Free Software Foundation; either version 2 of
  10  * the License, or (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  20  * MA 02111-1307 USA
  21  */
  22
  23 #include <common.h>
  24 #ifdef CONFIG_SYS_P4080_ERRATUM_SERDES8
  25 #include <hwconfig.h>
  26 #endif
  27 #include <asm/fsl_serdes.h>
  28 #include <asm/immap_85xx.h>
  29 #include <asm/io.h>
  30 #include <asm/processor.h>
  31 #include <asm/fsl_law.h>
  32 #include <asm/errno.h>
  33 #include "fsl_corenet_serdes.h"
  34
  35 /*
  36  * The work-arounds for erratum SERDES8 and SERDES-A001 are linked together.
  37  * The code is already very complicated as it is, and separating the two
  38  * completely would just make things worse.  We try to keep them as separate
  39  * as possible, but for now we require SERDES8 if SERDES_A001 is defined.
  40  */
  41 #ifdef CONFIG_SYS_P4080_ERRATUM_SERDES_A001
  42 #ifndef CONFIG_SYS_P4080_ERRATUM_SERDES8
  43 #error "CONFIG_SYS_P4080_ERRATUM_SERDES_A001 requires CONFIG_SYS_P4080_ERRATUM_SERDES8"
  44 #endif
  45 #endif
  46
  47 static u32 serdes_prtcl_map;
  48
  49 #ifdef DEBUG
  50 static const char *serdes_prtcl_str[] = {
  51         [NONE] = "NA",
  52         [PCIE1] = "PCIE1",
  53         [PCIE2] = "PCIE2",
  54         [PCIE3] = "PCIE3",
  55         [PCIE4] = "PCIE4",
  56         [SATA1] = "SATA1",
  57         [SATA2] = "SATA2",
  58         [SRIO1] = "SRIO1",
  59         [SRIO2] = "SRIO2",
  60         [SGMII_FM1_DTSEC1] = "SGMII_FM1_DTSEC1",
  61         [SGMII_FM1_DTSEC2] = "SGMII_FM1_DTSEC2",
  62         [SGMII_FM1_DTSEC3] = "SGMII_FM1_DTSEC3",
  63         [SGMII_FM1_DTSEC4] = "SGMII_FM1_DTSEC4",
  64         [SGMII_FM1_DTSEC5] = "SGMII_FM1_DTSEC5",
  65         [SGMII_FM2_DTSEC1] = "SGMII_FM2_DTSEC1",
  66         [SGMII_FM2_DTSEC2] = "SGMII_FM2_DTSEC2",
  67         [SGMII_FM2_DTSEC3] = "SGMII_FM2_DTSEC3",
  68         [SGMII_FM2_DTSEC4] = "SGMII_FM2_DTSEC4",
  69         [SGMII_FM2_DTSEC5] = "SGMII_FM2_DTSEC5",
  70         [XAUI_FM1] = "XAUI_FM1",
  71         [XAUI_FM2] = "XAUI_FM2",
  72         [AURORA] = "DEBUG",
  73 };
  74 #endif
  75
  76 static const struct {
  77         int idx;
  78         unsigned int lpd; /* RCW lane powerdown bit */
  79         int bank;
  80 } lanes[SRDS_MAX_LANES] = {
  81         { 0, 152, FSL_SRDS_BANK_1 },
  82         { 1, 153, FSL_SRDS_BANK_1 },
  83         { 2, 154, FSL_SRDS_BANK_1 },
  84         { 3, 155, FSL_SRDS_BANK_1 },
  85         { 4, 156, FSL_SRDS_BANK_1 },
  86         { 5, 157, FSL_SRDS_BANK_1 },
  87         { 6, 158, FSL_SRDS_BANK_1 },
  88         { 7, 159, FSL_SRDS_BANK_1 },
  89         { 8, 160, FSL_SRDS_BANK_1 },
  90         { 9, 161, FSL_SRDS_BANK_1 },
  91         { 16, 162, FSL_SRDS_BANK_2 },
  92         { 17, 163, FSL_SRDS_BANK_2 },
  93         { 18, 164, FSL_SRDS_BANK_2 },
  94         { 19, 165, FSL_SRDS_BANK_2 },
  95 #ifdef CONFIG_PPC_P4080
  96         { 20, 170, FSL_SRDS_BANK_3 },
  97         { 21, 171, FSL_SRDS_BANK_3 },
  98         { 22, 172, FSL_SRDS_BANK_3 },
  99         { 23, 173, FSL_SRDS_BANK_3 },
 100 #else
 101         { 20, 166, FSL_SRDS_BANK_3 },
 102         { 21, 167, FSL_SRDS_BANK_3 },
 103         { 22, 168, FSL_SRDS_BANK_3 },
 104         { 23, 169, FSL_SRDS_BANK_3 },
 105 #endif
 106 };
 107
 108 int serdes_get_lane_idx(int lane)
 109 {
 110         return lanes[lane].idx;
 111 }
 112
 113 int serdes_get_bank_by_lane(int lane)
 114 {
 115         return lanes[lane].bank;
 116 }
 117
 118 int serdes_lane_enabled(int lane)
 119 {
 120         ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
 121         serdes_corenet_t *regs = (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR;
 122
 123         int bank = lanes[lane].bank;
 124         int word = lanes[lane].lpd / 32;
 125         int bit = lanes[lane].lpd % 32;
 126
 127         if (in_be32(&regs->bank[bank].rstctl) & SRDS_RSTCTL_SDPD)
 128                 return 0;
 129
 130 #ifdef CONFIG_SYS_P4080_ERRATUM_SERDES8
 131         /*
 132          * For banks two and three, use the srds_lpd_b[] array instead of the
 133          * RCW, because this array contains the real values of SRDS_LPD_B2 and
 134          * SRDS_LPD_B3.
 135          */
 136         if (bank > 0)
 137                 return !(srds_lpd_b[bank] & (8 >> (lane - (6 + 4 * bank))));
 138 #endif
 139
 140         return !(in_be32(&gur->rcwsr[word]) & (0x80000000 >> bit));
 141 }
 142
 143 int is_serdes_configured(enum srds_prtcl device)
 144 {
 145         ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
 146
 147         /* Is serdes enabled at all? */
 148         if (!(in_be32(&gur->rcwsr[5]) & FSL_CORENET_RCWSR5_SRDS_EN))
 149                 return 0;
 150
 151         return (1 << device) & serdes_prtcl_map;
 152 }
 153
 154 static int __serdes_get_first_lane(uint32_t prtcl, enum srds_prtcl device)
 155 {
 156         int i;
 157
 158         for (i = 0; i < SRDS_MAX_LANES; i++) {
 159                 if (serdes_get_prtcl(prtcl, i) == device)
 160                         return i;
 161         }
 162
 163         return -ENODEV;
 164 }
 165
 166 /*
 167  * Returns the SERDES lane (0..SRDS_MAX_LANES-1) that routes to the given
 168  * device. This depends on the current SERDES protocol, as defined in the RCW.
 169  *
 170  * Returns a negative error code if SERDES is disabled or the given device is
 171  * not supported in the current SERDES protocol.
 172  */
 173 int serdes_get_first_lane(enum srds_prtcl device)
 174 {
 175         u32 prtcl;
 176         const ccsr_gur_t *gur;
 177
 178         gur = (typeof(gur))CONFIG_SYS_MPC85xx_GUTS_ADDR;
 179
 180         /* Is serdes enabled at all? */
 181         if (unlikely((in_be32(&gur->rcwsr[5]) & 0x2000) == 0))
 182                 return -ENODEV;
 183
 184         prtcl = (in_be32(&gur->rcwsr[4]) & FSL_CORENET_RCWSR4_SRDS_PRTCL) >> 26;
 185
 186         return __serdes_get_first_lane(prtcl, device);
 187 }
 188
 189 #ifdef CONFIG_SYS_P4080_ERRATUM_SERDES9
 190 /*
 191  * Returns the SERDES bank (1, 2, or 3) that a given device is on for a given
 192  * SERDES protocol.
 193  *
 194  * Returns a negative error code if the given device is not supported for the
 195  * given SERDES protocol.
 196  */
 197 static int serdes_get_bank_by_device(uint32_t prtcl, enum srds_prtcl device)
 198 {
 199         int lane;
 200
 201         lane = __serdes_get_first_lane(prtcl, device);
 202         if (unlikely(lane < 0))
 203                 return lane;
 204
 205         return serdes_get_bank_by_lane(lane);
 206 }
 207
 208 static uint32_t __serdes_get_lane_count(uint32_t prtcl, enum srds_prtcl device,
 209                                         int first)
 210 {
 211         int lane;
 212
 213         for (lane = first; lane < SRDS_MAX_LANES; lane++) {
 214                 if (serdes_get_prtcl(prtcl, lane) != device)
 215                         break;
 216         }
 217
 218         return lane - first;
 219 }
 220
 221 static void __serdes_reset_rx(serdes_corenet_t *regs,
 222                               uint32_t prtcl,
 223                               enum srds_prtcl device)
 224 {
 225         int lane, idx, first, last;
 226
 227         lane = __serdes_get_first_lane(prtcl, device);
 228         if (unlikely(lane < 0))
 229                 return;
 230         first = serdes_get_lane_idx(lane);
 231         last = first + __serdes_get_lane_count(prtcl, device, lane);
 232
 233         /*
 234          * Set BnGCRy0[RRST] = 0 for each lane in the each bank that is
 235          * selected as XAUI to place the lane into reset.
 236         */
 237         for (idx = first; idx < last; idx++)
 238                 clrbits_be32(&regs->lane[idx].gcr0, SRDS_GCR0_RRST);
 239
 240         /* Wait at least 250 ns */
 241         udelay(1);
 242
 243         /*
 244          * Set BnGCRy0[RRST] = 1 for each lane in the each bank that is
 245          * selected as XAUI to bring the lane out of reset.
 246          */
 247         for (idx = first; idx < last; idx++)
 248                 setbits_be32(&regs->lane[idx].gcr0, SRDS_GCR0_RRST);
 249 }
 250
 251 void serdes_reset_rx(enum srds_prtcl device)
 252 {
 253         u32 prtcl;
 254         const ccsr_gur_t *gur;
 255         serdes_corenet_t *regs;
 256
 257         if (unlikely(device == NONE))
 258                 return;
 259
 260         gur = (typeof(gur))CONFIG_SYS_MPC85xx_GUTS_ADDR;
 261
 262         /* Is serdes enabled at all? */
 263         if (unlikely((in_be32(&gur->rcwsr[5]) & 0x2000) == 0))
 264                 return;
 265
 266         regs = (typeof(regs))CONFIG_SYS_FSL_CORENET_SERDES_ADDR;
 267         prtcl = (in_be32(&gur->rcwsr[4]) & FSL_CORENET_RCWSR4_SRDS_PRTCL) >> 26;
 268
 269         __serdes_reset_rx(regs, prtcl, device);
 270 }
 271 #endif
 272
 273 #ifndef CONFIG_SYS_DCSRBAR_PHYS
 274 #define CONFIG_SYS_DCSRBAR_PHYS 0x80000000 /* Must be 1GB-aligned for rev1.0 */
 275 #define CONFIG_SYS_DCSRBAR      0x80000000
 276 #define __DCSR_NOT_DEFINED_BY_CONFIG
 277 #endif
 278
 279 #ifdef CONFIG_SYS_P4080_ERRATUM_SERDES8
 280 /*
 281  * Enable a SERDES bank that was disabled via the RCW
 282  *
 283  * We only call this function for SERDES8 and SERDES-A001 in cases we really
 284  * want to enable the bank, whether we actually want to use the lanes or not,
 285  * so make sure at least one lane is enabled.  We're only enabling this one
 286  * lane to satisfy errata requirements that the bank be enabled.
 287  *
 288  * We use a local variable instead of srds_lpd_b[] because we want drivers to
 289  * think that the lanes actually are disabled.
 290  */
 291 static void enable_bank(ccsr_gur_t *gur, int bank)
 292 {
 293         u32 rcw5;
 294         u32 temp_lpd_b = srds_lpd_b[bank];
 295
 296         /*
 297          * If we're asked to disable all lanes, just pretend we're doing
 298          * that.
 299          */
 300         if (temp_lpd_b == 0xF)
 301                 temp_lpd_b = 0xE;
 302
 303         /*
 304          * Enable the lanes SRDS_LPD_Bn.  The RCW bits are read-only in
 305          * CCSR, and read/write in DSCR.
 306          */
 307         rcw5 = in_be32(gur->rcwsr + 5);
 308         if (bank == FSL_SRDS_BANK_2) {
 309                 rcw5 &= ~FSL_CORENET_RCWSRn_SRDS_LPD_B2;
 310                 rcw5 |= temp_lpd_b << 26;
 311         } else if (bank == FSL_SRDS_BANK_3) {
 312                 rcw5 &= ~FSL_CORENET_RCWSRn_SRDS_LPD_B3;
 313                 rcw5 |= temp_lpd_b << 18;
 314         } else {
 315                 printf("SERDES: enable_bank: bad bank %d\n", bank + 1);
 316                 return;
 317         }
 318
 319         /* See similar code in cpu/mpc85xx/cpu_init.c for an explanation
 320          * of the DCSR mapping.
 321          */
 322         {
 323 #ifdef __DCSR_NOT_DEFINED_BY_CONFIG
 324                 struct law_entry law = find_law(CONFIG_SYS_DCSRBAR_PHYS);
 325                 int law_index;
 326                 if (law.index == -1)
 327                         law_index = set_next_law(CONFIG_SYS_DCSRBAR_PHYS,
 328                                                  LAW_SIZE_1M, LAW_TRGT_IF_DCSR);
 329                 else
 330                         set_law(law.index, CONFIG_SYS_DCSRBAR_PHYS, LAW_SIZE_1M,
 331                                 LAW_TRGT_IF_DCSR);
 332 #endif
 333                 u32 *p = (void *)CONFIG_SYS_DCSRBAR + 0x20114;
 334                 out_be32(p, rcw5);
 335 #ifdef __DCSR_NOT_DEFINED_BY_CONFIG
 336                 if (law.index == -1)
 337                         disable_law(law_index);
 338                 else
 339                         set_law(law.index, law.addr, law.size, law.trgt_id);
 340 #endif
 341         }
 342 }
 343
 344 /*
 345  * To avoid problems with clock jitter, rev 2 p4080 uses the pll from
 346  * bank 3 to clock banks 2 and 3, as well as a limited selection of
 347  * protocol configurations.  This requires that banks 2 and 3's lanes be
 348  * disabled in the RCW, and enabled with some fixup here to re-enable
 349  * them, and to configure bank 2's clock parameters in bank 3's pll in
 350  * cases where they differ.
 351  */
 352 static void p4080_erratum_serdes8(serdes_corenet_t *regs, ccsr_gur_t *gur,
 353                                   u32 devdisr, u32 devdisr2, int cfg)
 354 {
 355         int srds_ratio_b2;
 356         int rfck_sel;
 357
 358         /*
 359          * The disabled lanes of bank 2 will cause the associated
 360          * logic blocks to be disabled in DEVDISR.  We reverse that here.
 361          *
 362          * Note that normally it is not permitted to clear DEVDISR bits
 363          * once the device has been disabled, but the hardware people
 364          * say that this special case is OK.
 365          */
 366         clrbits_be32(&gur->devdisr, devdisr);
 367         clrbits_be32(&gur->devdisr2, devdisr2);
 368
 369         /*
 370          * Some protocols require special handling.  There are a few
 371          * additional protocol configurations that can be used, which are
 372          * not listed here.  See app note 4065 for supported protocol
 373          * configurations.
 374          */
 375         switch (cfg) {
 376         case 0x19:
 377                 /*
 378                  * Bank 2 has PCIe which wants BWSEL -- tell bank 3's PLL.
 379                  * SGMII on bank 3 should still be usable.
 380                  */
 381                 setbits_be32(&regs->bank[FSL_SRDS_BANK_3].pllcr1,
 382                              SRDS_PLLCR1_PLL_BWSEL);
 383                 break;
 384
 385         case 0x0f:
 386         case 0x10:
 387                 /*
 388                  * Banks 2 (XAUI) and 3 (SGMII) have different clocking
 389                  * requirements in these configurations.  Bank 3 cannot
 390                  * be used and should have its lanes (but not the bank
 391                  * itself) disabled in the RCW.  We set up bank 3's pll
 392                  * for bank 2's needs here.
 393                  */
 394                 srds_ratio_b2 = (in_be32(&gur->rcwsr[4]) >> 13) & 7;
 395
 396                 /* Determine refclock from XAUI ratio */
 397                 switch (srds_ratio_b2) {
 398                 case 1: /* 20:1 */
 399                         rfck_sel = SRDS_PLLCR0_RFCK_SEL_156_25;
 400                         break;
 401                 case 2: /* 25:1 */
 402                         rfck_sel = SRDS_PLLCR0_RFCK_SEL_125;
 403                         break;
 404                 default:
 405                         printf("SERDES: bad SRDS_RATIO_B2 %d\n",
 406                                srds_ratio_b2);
 407                         return;
 408                 }
 409
 410                 clrsetbits_be32(&regs->bank[FSL_SRDS_BANK_3].pllcr0,
 411                                 SRDS_PLLCR0_RFCK_SEL_MASK, rfck_sel);
 412
 413                 clrsetbits_be32(&regs->bank[FSL_SRDS_BANK_3].pllcr0,
 414                                 SRDS_PLLCR0_FRATE_SEL_MASK,
 415                                 SRDS_PLLCR0_FRATE_SEL_6_25);
 416                 break;
 417         }
 418
 419         enable_bank(gur, FSL_SRDS_BANK_3);
 420 }
 421 #endif
 422
 423 #ifdef CONFIG_SYS_P4080_ERRATUM_SERDES_A005
 424 /*
 425  * If PCIe is not selected as a protocol for any lanes driven by a given PLL,
 426  * that PLL should have SRDSBnPLLCR1[PLLBW_SEL] = 0.
 427  */
 428 static void p4080_erratum_serdes_a005(serdes_corenet_t *regs, unsigned int cfg)
 429 {
 430         enum srds_prtcl device;
 431
 432         switch (cfg) {
 433         case 0x13:
 434         case 0x16:
 435                 /*
 436                  * If SRDS_PRTCL = 0x13 or 0x16, set SRDSB1PLLCR1[PLLBW_SEL]
 437                  * to 0.
 438                  */
 439                 clrbits_be32(&regs->bank[FSL_SRDS_BANK_1].pllcr1,
 440                              SRDS_PLLCR1_PLL_BWSEL);
 441                 break;
 442         case 0x19:
 443                 /*
 444                  * If SRDS_PRTCL = 0x19, set SRDSB1PLLCR1[PLLBW_SEL] to 0 and
 445                  * SRDSB3PLLCR1[PLLBW_SEL] to 1.
 446                  */
 447                 clrbits_be32(&regs->bank[FSL_SRDS_BANK_1].pllcr1,
 448                              SRDS_PLLCR1_PLL_BWSEL);
 449                 setbits_be32(&regs->bank[FSL_SRDS_BANK_3].pllcr1,
 450                              SRDS_PLLCR1_PLL_BWSEL);
 451                 break;
 452         }
 453
 454         /*
 455          * Set SRDSBnPLLCR1[PLLBW_SEL] to 0 for each bank that selects XAUI
 456          * before XAUI is initialized.
 457          */
 458         for (device = XAUI_FM1; device <= XAUI_FM2; device++) {
 459                 if (is_serdes_configured(device)) {
 460                         int bank = serdes_get_bank_by_device(cfg, device);
 461
 462                         clrbits_be32(&regs->bank[bank].pllcr1,
 463                                      SRDS_PLLCR1_PLL_BWSEL);
 464                 }
 465         }
 466 }
 467 #endif
 468
 469 /*
 470  * Wait for the RSTDONE bit to get set, or a one-second timeout.
 471  */
 472 static void wait_for_rstdone(unsigned int bank)
 473 {
 474         serdes_corenet_t *srds_regs =
 475                 (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR;
 476         unsigned long long end_tick;
 477         u32 rstctl;
 478
 479         /* wait for reset complete or 1-second timeout */
 480         end_tick = usec2ticks(1000000) + get_ticks();
 481         do {
 482                 rstctl = in_be32(&srds_regs->bank[bank].rstctl);
 483                 if (rstctl & SRDS_RSTCTL_RSTDONE)
 484                         break;
 485         } while (end_tick > get_ticks());
 486
 487         if (!(rstctl & SRDS_RSTCTL_RSTDONE))
 488                 printf("SERDES: timeout resetting bank %u\n", bank + 1);
 489 }
 490
 491
 492 static void __soc_serdes_init(void)
 493 {
 494         /* Allow for SoC-specific initialization in <SOC>_serdes.c  */
 495 };
 496 void soc_serdes_init(void) __attribute__((weak, alias("__soc_serdes_init")));
 497
 498 void fsl_serdes_init(void)
 499 {
 500         ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
 501         int cfg;
 502         serdes_corenet_t *srds_regs;
 503 #ifdef CONFIG_PPC_P5040
 504         serdes_corenet_t *srds2_regs;
 505 #endif
 506         int lane, bank, idx;
 507         int have_bank[SRDS_MAX_BANK] = {};
 508 #ifdef CONFIG_SYS_P4080_ERRATUM_SERDES8
 509         u32 serdes8_devdisr = 0;
 510         u32 serdes8_devdisr2 = 0;
 511         char srds_lpd_opt[16];
 512         const char *srds_lpd_arg;
 513         size_t arglen;
 514 #endif
 515 #ifdef CONFIG_SYS_P4080_ERRATUM_SERDES_A001
 516         int need_serdes_a001;   /* TRUE == need work-around for SERDES A001 */
 517 #endif
 518 #ifdef CONFIG_SYS_P4080_ERRATUM_SERDES8
 519         char buffer[HWCONFIG_BUFFER_SIZE];
 520         char *buf = NULL;
 521
 522         /*
 523          * Extract hwconfig from environment since we have not properly setup
 524          * the environment but need it for ddr config params
 525          */
 526         if (getenv_f("hwconfig", buffer, sizeof(buffer)) > 0)
 527                 buf = buffer;
 528 #endif
 529
 530         /* Is serdes enabled at all? */
 531         if (!(in_be32(&gur->rcwsr[5]) & FSL_CORENET_RCWSR5_SRDS_EN))
 532                 return;
 533
 534         srds_regs = (void *)(CONFIG_SYS_FSL_CORENET_SERDES_ADDR);
 535         cfg = (in_be32(&gur->rcwsr[4]) & FSL_CORENET_RCWSR4_SRDS_PRTCL) >> 26;
 536         debug("Using SERDES configuration 0x%x, lane settings:\n", cfg);
 537
 538         if (!is_serdes_prtcl_valid(cfg)) {
 539                 printf("SERDES[PRTCL] = 0x%x is not valid\n", cfg);
 540                 return;
 541         }
 542
 543 #ifdef CONFIG_SYS_P4080_ERRATUM_SERDES8
 544         /*
 545          * Display a warning if banks two and three are not disabled in the RCW,
 546          * since our work-around for SERDES8 depends on these banks being
 547          * disabled at power-on.
 548          */
 549 #define B2_B3 (FSL_CORENET_RCWSRn_SRDS_LPD_B2 | FSL_CORENET_RCWSRn_SRDS_LPD_B3)
 550         if ((in_be32(&gur->rcwsr[5]) & B2_B3) != B2_B3) {
 551                 printf("Warning: SERDES8 requires banks two and "
 552                        "three to be disabled in the RCW\n");
 553         }
 554
 555         /*
 556          * Store the values of the fsl_srds_lpd_b2 and fsl_srds_lpd_b3
 557          * hwconfig options into the srds_lpd_b[] array.  See README.p4080ds
 558          * for a description of these options.
 559          */
 560         for (bank = 1; bank < ARRAY_SIZE(srds_lpd_b); bank++) {
 561                 sprintf(srds_lpd_opt, "fsl_srds_lpd_b%u", bank + 1);
 562                 srds_lpd_arg =
 563                         hwconfig_subarg_f("serdes", srds_lpd_opt, &arglen, buf);
 564                 if (srds_lpd_arg)
 565                         srds_lpd_b[bank] =
 566                                 simple_strtoul(srds_lpd_arg, NULL, 0) & 0xf;
 567         }
 568
 569         if ((cfg == 0xf) || (cfg == 0x10)) {
 570                 /*
 571                  * For SERDES protocols 0xF and 0x10, force bank 3 to be
 572                  * disabled, because it is not supported.
 573                  */
 574                 srds_lpd_b[FSL_SRDS_BANK_3] = 0xF;
 575         }
 576 #endif
 577
 578         /* Look for banks with all lanes disabled, and power down the bank. */
 579         for (lane = 0; lane < SRDS_MAX_LANES; lane++) {
 580                 enum srds_prtcl lane_prtcl = serdes_get_prtcl(cfg, lane);
 581                 if (serdes_lane_enabled(lane)) {
 582                         have_bank[serdes_get_bank_by_lane(lane)] = 1;
 583                         serdes_prtcl_map |= (1 << lane_prtcl);
 584                 }
 585         }
 586
 587 #ifdef CONFIG_PPC_P5040
 588         /*
 589          * Lanes on bank 4 on P5040 are commented-out, but for some SERDES
 590          * protocols, these lanes are routed to SATA.  We use serdes_prtcl_map
 591          * to decide whether a protocol is supported on a given lane, so SATA
 592          * will be identified as not supported, and therefore not initialized.
 593          * So for protocols which use SATA on bank4, we add SATA support in
 594          * serdes_prtcl_map.
 595          */
 596         switch (cfg) {
 597         case 0x0:
 598         case 0x1:
 599         case 0x2:
 600         case 0x3:
 601         case 0x4:
 602         case 0x5:
 603         case 0x6:
 604         case 0x7:
 605                 serdes_prtcl_map |= 1 << SATA1 | 1 << SATA2;
 606                 break;
 607         default:
 608                 srds2_regs = (void *)CONFIG_SYS_FSL_CORENET_SERDES2_ADDR;
 609
 610                 /* We don't need bank 4, so power it down */
 611                 setbits_be32(&srds2_regs->bank[0].rstctl, SRDS_RSTCTL_SDPD);
 612         }
 613 #endif
 614
 615         soc_serdes_init();
 616
 617 #ifdef CONFIG_SYS_P4080_ERRATUM_SERDES8
 618         /*
 619          * Bank two uses the clock from bank three, so if bank two is enabled,
 620          * then bank three must also be enabled.
 621          */
 622         if (have_bank[FSL_SRDS_BANK_2])
 623                 have_bank[FSL_SRDS_BANK_3] = 1;
 624 #endif
 625
 626 #ifdef CONFIG_SYS_P4080_ERRATUM_SERDES_A001
 627         /*
 628          * The work-aroud for erratum SERDES-A001 is needed only if bank two
 629          * is disabled and bank three is enabled.  The converse is also true,
 630          * but SERDES8 ensures that bank 3 is always enabled if bank 2 is
 631          * enabled, so there's no point in complicating the code to handle
 632          * that situation.
 633          */
 634         need_serdes_a001 =
 635                 !have_bank[FSL_SRDS_BANK_2] && have_bank[FSL_SRDS_BANK_3];
 636 #endif
 637
 638         /* Power down the banks we're not interested in */
 639         for (bank = 0; bank < SRDS_MAX_BANK; bank++) {
 640                 if (!have_bank[bank]) {
 641                         printf("SERDES: bank %d disabled\n", bank + 1);
 642 #ifdef CONFIG_SYS_P4080_ERRATUM_SERDES_A001
 643                         /*
 644                          * Erratum SERDES-A001 says bank two needs to be powered
 645                          * down after bank three is powered up, so don't power
 646                          * down bank two here.
 647                          */
 648                         if (!need_serdes_a001 || (bank != FSL_SRDS_BANK_2))
 649                                 setbits_be32(&srds_regs->bank[bank].rstctl,
 650                                              SRDS_RSTCTL_SDPD);
 651 #else
 652                         setbits_be32(&srds_regs->bank[bank].rstctl,
 653                                      SRDS_RSTCTL_SDPD);
 654 #endif
 655                 }
 656         }
 657
 658 #ifdef CONFIG_SYS_FSL_ERRATUM_A004699
 659         /*
 660          * To avoid the situation that resulted in the P4080 erratum
 661          * SERDES-8, a given SerDes bank will use the PLLs from the previous
 662          * bank if one of the PLL frequencies is a multiple of the other.  For
 663          * instance, if bank 3 is running at 2.5GHz and bank 2 is at 1.25GHz,
 664          * then bank 3 will use bank 2's PLL.  P5040 Erratum A-004699 says
 665          * that, in this situation, lane synchronization is not initiated.  So
 666          * when we detect a bank with a "borrowed" PLL, we have to manually
 667          * initiate lane synchronization.
 668          */
 669         for (bank = FSL_SRDS_BANK_2; bank <= FSL_SRDS_BANK_3; bank++) {
 670                 /* Determine the first lane for this bank */
 671                 unsigned int lane;
 672
 673                 for (lane = 0; lane < SRDS_MAX_LANES; lane++)
 674                         if (lanes[lane].bank == bank)
 675                                 break;
 676                 idx = lanes[lane].idx;
 677
 678                 /*
 679                  * Check if the PLL for the bank is borrowed.  The UOTHL
 680                  * bit of the first lane will tell us that.
 681                  */
 682                 if (in_be32(&srds_regs->lane[idx].gcr0) & SRDS_GCR0_UOTHL) {
 683                         /* Manually start lane synchronization */
 684                         setbits_be32(&srds_regs->bank[bank].pllcr0,
 685                                      SRDS_PLLCR0_PVCOCNT_EN);
 686                 }
 687         }
 688 #endif
 689
 690 #if defined(CONFIG_SYS_P4080_ERRATUM_SERDES8) || defined (CONFIG_SYS_P4080_ERRATUM_SERDES9)
 691         for (lane = 0; lane < SRDS_MAX_LANES; lane++) {
 692                 enum srds_prtcl lane_prtcl;
 693
 694                 idx = serdes_get_lane_idx(lane);
 695                 lane_prtcl = serdes_get_prtcl(cfg, lane);
 696
 697 #ifdef DEBUG
 698                 switch (lane) {
 699                 case 0:
 700                         puts("Bank1: ");
 701                         break;
 702                 case 10:
 703                         puts("\nBank2: ");
 704                         break;
 705                 case 14:
 706                         puts("\nBank3: ");
 707                         break;
 708                 default:
 709                         break;
 710                 }
 711
 712                 printf("%s ", serdes_prtcl_str[lane_prtcl]);
 713 #endif
 714
 715 #ifdef CONFIG_SYS_P4080_ERRATUM_SERDES9
 716                 /*
 717                  * Set BnTTLCRy0[FLT_SEL] = 011011 and set BnTTLCRy0[31] = 1
 718                  * for each of the SerDes lanes selected as SGMII, XAUI, SRIO,
 719                  * or AURORA before the device is initialized.
 720                  *
 721                  * Note that this part of the SERDES-9 work-around is
 722                  * redundant if the work-around for A-4580 has already been
 723                  * applied via PBI.
 724                  */
 725                 switch (lane_prtcl) {
 726                 case SGMII_FM1_DTSEC1:
 727                 case SGMII_FM1_DTSEC2:
 728                 case SGMII_FM1_DTSEC3:
 729                 case SGMII_FM1_DTSEC4:
 730                 case SGMII_FM2_DTSEC1:
 731                 case SGMII_FM2_DTSEC2:
 732                 case SGMII_FM2_DTSEC3:
 733                 case SGMII_FM2_DTSEC4:
 734                 case SGMII_FM2_DTSEC5:
 735                 case XAUI_FM1:
 736                 case XAUI_FM2:
 737                 case SRIO1:
 738                 case SRIO2:
 739                 case AURORA:
 740                         out_be32(&srds_regs->lane[idx].ttlcr0,
 741                                  SRDS_TTLCR0_FLT_SEL_KFR_26 |
 742                                  SRDS_TTLCR0_FLT_SEL_KPH_28 |
 743                                  SRDS_TTLCR0_FLT_SEL_750PPM |
 744                                  SRDS_TTLCR0_FREQOVD_EN);
 745                         break;
 746                 default:
 747                         break;
 748                 }
 749 #endif
 750
 751 #ifdef CONFIG_SYS_P4080_ERRATUM_SERDES8
 752                 switch (lane_prtcl) {
 753                 case PCIE1:
 754                 case PCIE2:
 755                 case PCIE3:
 756                         serdes8_devdisr |= FSL_CORENET_DEVDISR_PCIE1 >>
 757                                            (lane_prtcl - PCIE1);
 758                         break;
 759                 case SRIO1:
 760                 case SRIO2:
 761                         serdes8_devdisr |= FSL_CORENET_DEVDISR_SRIO1 >>
 762                                            (lane_prtcl - SRIO1);
 763                         break;
 764                 case SGMII_FM1_DTSEC1:
 765                         serdes8_devdisr2 |= FSL_CORENET_DEVDISR2_FM1 |
 766                                             FSL_CORENET_DEVDISR2_DTSEC1_1;
 767                         break;
 768                 case SGMII_FM1_DTSEC2:
 769                         serdes8_devdisr2 |= FSL_CORENET_DEVDISR2_FM1 |
 770                                             FSL_CORENET_DEVDISR2_DTSEC1_2;
 771                         break;
 772                 case SGMII_FM1_DTSEC3:
 773                         serdes8_devdisr2 |= FSL_CORENET_DEVDISR2_FM1 |
 774                                             FSL_CORENET_DEVDISR2_DTSEC1_3;
 775                         break;
 776                 case SGMII_FM1_DTSEC4:
 777                         serdes8_devdisr2 |= FSL_CORENET_DEVDISR2_FM1 |
 778                                             FSL_CORENET_DEVDISR2_DTSEC1_4;
 779                         break;
 780                 case SGMII_FM2_DTSEC1:
 781                         serdes8_devdisr2 |= FSL_CORENET_DEVDISR2_FM2 |
 782                                             FSL_CORENET_DEVDISR2_DTSEC2_1;
 783                         break;
 784                 case SGMII_FM2_DTSEC2:
 785                         serdes8_devdisr2 |= FSL_CORENET_DEVDISR2_FM2 |
 786                                             FSL_CORENET_DEVDISR2_DTSEC2_2;
 787                         break;
 788                 case SGMII_FM2_DTSEC3:
 789                         serdes8_devdisr2 |= FSL_CORENET_DEVDISR2_FM2 |
 790                                             FSL_CORENET_DEVDISR2_DTSEC2_3;
 791                         break;
 792                 case SGMII_FM2_DTSEC4:
 793                         serdes8_devdisr2 |= FSL_CORENET_DEVDISR2_FM2 |
 794                                             FSL_CORENET_DEVDISR2_DTSEC2_4;
 795                         break;
 796                 case SGMII_FM2_DTSEC5:
 797                         serdes8_devdisr2 |= FSL_CORENET_DEVDISR2_FM2 |
 798                                             FSL_CORENET_DEVDISR2_DTSEC2_5;
 799                         break;
 800                 case XAUI_FM1:
 801                         serdes8_devdisr2 |= FSL_CORENET_DEVDISR2_FM1    |
 802                                             FSL_CORENET_DEVDISR2_10GEC1;
 803                         break;
 804                 case XAUI_FM2:
 805                         serdes8_devdisr2 |= FSL_CORENET_DEVDISR2_FM2    |
 806                                             FSL_CORENET_DEVDISR2_10GEC2;
 807                         break;
 808                 case AURORA:
 809                         break;
 810                 default:
 811                         break;
 812                 }
 813
 814 #endif
 815         }
 816 #endif
 817
 818 #ifdef DEBUG
 819         puts("\n");
 820 #endif
 821
 822 #ifdef CONFIG_SYS_P4080_ERRATUM_SERDES_A005
 823         p4080_erratum_serdes_a005(srds_regs, cfg);
 824 #endif
 825
 826         for (idx = 0; idx < SRDS_MAX_BANK; idx++) {
 827                 bank = idx;
 828
 829 #ifdef CONFIG_SYS_P4080_ERRATUM_SERDES8
 830                 /*
 831                  * Change bank init order to 0, 2, 1, so that the third bank's
 832                  * PLL is established before we start the second bank.  The
 833                  * second bank uses the third bank's PLL.
 834                  */
 835
 836                 if (idx == 1)
 837                         bank = FSL_SRDS_BANK_3;
 838                 else if (idx == 2)
 839                         bank = FSL_SRDS_BANK_2;
 840 #endif
 841
 842                 /* Skip disabled banks */
 843                 if (!have_bank[bank])
 844                         continue;
 845
 846 #ifdef CONFIG_SYS_P4080_ERRATUM_SERDES8
 847                 if (idx == 1) {
 848                         /*
 849                          * Re-enable devices on banks two and three that were
 850                          * disabled by the RCW, and then enable bank three. The
 851                          * devices need to be enabled before either bank is
 852                          * powered up.
 853                          */
 854                         p4080_erratum_serdes8(srds_regs, gur, serdes8_devdisr,
 855                                               serdes8_devdisr2, cfg);
 856                 } else if (idx == 2) {
 857                         /* Enable bank two now that bank three is enabled. */
 858                         enable_bank(gur, FSL_SRDS_BANK_2);
 859                 }
 860 #endif
 861
 862                 wait_for_rstdone(bank);
 863         }
 864
 865 #ifdef CONFIG_SYS_P4080_ERRATUM_SERDES_A001
 866         if (need_serdes_a001) {
 867                 /* Bank 3 has been enabled, so now we can disable bank 2 */
 868                 setbits_be32(&srds_regs->bank[FSL_SRDS_BANK_2].rstctl,
 869                              SRDS_RSTCTL_SDPD);
 870         }
 871 #endif
 872 }