arch/powerpc/cpu/mpc85xx/release.S

   1 /*
   2  * Copyright 2008-2012 Freescale Semiconductor, Inc.
   3  * Kumar Gala <kumar.gala@freescale.com>
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  */
  23
  24 #include <asm-offsets.h>
  25 #include <config.h>
  26 #include <mpc85xx.h>
  27 #include <version.h>
  28
  29 #define _LINUX_CONFIG_H 1       /* avoid reading Linux autoconf.h file  */
  30
  31 #include <ppc_asm.tmpl>
  32 #include <ppc_defs.h>
  33
  34 #include <asm/cache.h>
  35 #include <asm/mmu.h>
  36
  37 /* To boot secondary cpus, we need a place for them to start up.
  38  * Normally, they start at 0xfffffffc, but that's usually the
  39  * firmware, and we don't want to have to run the firmware again.
  40  * Instead, the primary cpu will set the BPTR to point here to
  41  * this page.  We then set up the core, and head to
  42  * start_secondary.  Note that this means that the code below
  43  * must never exceed 1023 instructions (the branch at the end
  44  * would then be the 1024th).
  45  */
  46         .globl  __secondary_start_page
  47         .align  12
  48 __secondary_start_page:
  49 /* First do some preliminary setup */
  50         lis     r3, HID0_EMCP@h         /* enable machine check */
  51 #ifndef CONFIG_E500MC
  52         ori     r3,r3,HID0_TBEN@l       /* enable Timebase */
  53 #endif
  54 #ifdef CONFIG_PHYS_64BIT
  55         ori     r3,r3,HID0_ENMAS7@l     /* enable MAS7 updates */
  56 #endif
  57         mtspr   SPRN_HID0,r3
  58
  59 #ifndef CONFIG_E500MC
  60         li      r3,(HID1_ASTME|HID1_ABE)@l      /* Addr streaming & broadcast */
  61         mfspr   r0,PVR
  62         andi.   r0,r0,0xff
  63         cmpwi   r0,0x50@l       /* if we are rev 5.0 or greater set MBDD */
  64         blt 1f
  65         /* Set MBDD bit also */
  66         ori r3, r3, HID1_MBDD@l
  67 1:
  68         mtspr   SPRN_HID1,r3
  69 #endif
  70
  71 #ifdef CONFIG_SYS_FSL_ERRATUM_CPU_A003999
  72         mfspr   r3,977
  73         oris    r3,r3,0x0100
  74         mtspr   977,r3
  75 #endif
  76
  77 #ifdef CONFIG_SYS_FSL_ERRATUM_A004510
  78         mfspr   r3,SPRN_SVR
  79         rlwinm  r3,r3,0,0xff
  80         li      r4,CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV
  81         cmpw    r3,r4
  82         beq     1f
  83
  84 #ifdef CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV2
  85         li      r4,CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV2
  86         cmpw    r3,r4
  87         beq     1f
  88 #endif
  89
  90         /* Not a supported revision affected by erratum */
  91         b       2f
  92
  93 1:      /* Erratum says set bits 55:60 to 001001 */
  94         msync
  95         isync
  96         mfspr   r3,976
  97         li      r4,0x48
  98         rlwimi  r3,r4,0,0x1f8
  99         mtspr   976,r3
 100         isync
 101 2:
 102 #endif
 103
 104         /* Enable branch prediction */
 105         lis     r3,BUCSR_ENABLE@h
 106         ori     r3,r3,BUCSR_ENABLE@l
 107         mtspr   SPRN_BUCSR,r3
 108
 109         /* Ensure TB is 0 */
 110         li      r3,0
 111         mttbl   r3
 112         mttbu   r3
 113
 114         /* Enable/invalidate the I-Cache */
 115         lis     r2,(L1CSR1_ICFI|L1CSR1_ICLFR)@h
 116         ori     r2,r2,(L1CSR1_ICFI|L1CSR1_ICLFR)@l
 117         mtspr   SPRN_L1CSR1,r2
 118 1:
 119         mfspr   r3,SPRN_L1CSR1
 120         and.    r1,r3,r2
 121         bne     1b
 122
 123         lis     r3,(L1CSR1_CPE|L1CSR1_ICE)@h
 124         ori     r3,r3,(L1CSR1_CPE|L1CSR1_ICE)@l
 125         mtspr   SPRN_L1CSR1,r3
 126         isync
 127 2:
 128         mfspr   r3,SPRN_L1CSR1
 129         andi.   r1,r3,L1CSR1_ICE@l
 130         beq     2b
 131
 132         /* Enable/invalidate the D-Cache */
 133         lis     r2,(L1CSR0_DCFI|L1CSR0_DCLFR)@h
 134         ori     r2,r2,(L1CSR0_DCFI|L1CSR0_DCLFR)@l
 135         mtspr   SPRN_L1CSR0,r2
 136 1:
 137         mfspr   r3,SPRN_L1CSR0
 138         and.    r1,r3,r2
 139         bne     1b
 140
 141         lis     r3,(L1CSR0_CPE|L1CSR0_DCE)@h
 142         ori     r3,r3,(L1CSR0_CPE|L1CSR0_DCE)@l
 143         mtspr   SPRN_L1CSR0,r3
 144         isync
 145 2:
 146         mfspr   r3,SPRN_L1CSR0
 147         andi.   r1,r3,L1CSR0_DCE@l
 148         beq     2b
 149
 150 #define toreset(x) (x - __secondary_start_page + 0xfffff000)
 151
 152         /* get our PIR to figure out our table entry */
 153         lis     r3,toreset(__spin_table_addr)@h
 154         ori     r3,r3,toreset(__spin_table_addr)@l
 155         lwz     r3,0(r3)
 156
 157         /*
 158          * r10 has the base address for the entry.
 159          * we cannot access it yet before setting up a new TLB
 160          */
 161         mfspr   r0,SPRN_PIR
 162 #if     defined(CONFIG_E6500)
 163 /*
 164  * PIR definition for E6500
 165  * 0-17 Reserved (logic 0s)
 166  * 8-19 CHIP_ID,    2'b00      - SoC 1
 167  *                  all others - reserved
 168  * 20-24 CLUSTER_ID 5'b00000   - CCM 1
 169  *                  all others - reserved
 170  * 25-26 CORE_CLUSTER_ID 2'b00 - cluster 1
 171  *                       2'b01 - cluster 2
 172  *                       2'b10 - cluster 3
 173  *                       2'b11 - cluster 4
 174  * 27-28 CORE_ID         2'b00 - core 0
 175  *                       2'b01 - core 1
 176  *                       2'b10 - core 2
 177  *                       2'b11 - core 3
 178  * 29-31 THREAD_ID       3'b000 - thread 0
 179  *                       3'b001 - thread 1
 180  */
 181         rlwinm  r4,r0,29,25,31
 182 #elif   defined(CONFIG_E500MC)
 183         rlwinm  r4,r0,27,27,31
 184 #else
 185         mr      r4,r0
 186 #endif
 187         slwi    r8,r4,6 /* spin table is padded to 64 byte */
 188         add     r10,r3,r8
 189
 190 #ifdef CONFIG_E6500
 191         mfspr   r0,SPRN_PIR
 192         /*
 193          * core 0 thread 0: pir reset value 0x00, new pir 0
 194          * core 0 thread 1: pir reset value 0x01, new pir 1
 195          * core 1 thread 0: pir reset value 0x08, new pir 2
 196          * core 1 thread 1: pir reset value 0x09, new pir 3
 197          * core 2 thread 0: pir reset value 0x10, new pir 4
 198          * core 2 thread 1: pir reset value 0x11, new pir 5
 199          * etc.
 200          *
 201          * Only thread 0 of each core will be running, updating PIR doesn't
 202          * need to deal with the thread bits.
 203          */
 204         rlwinm  r4,r0,30,24,30
 205 #endif
 206
 207         mtspr   SPRN_PIR,r4     /* write to PIR register */
 208
 209 #ifdef CONFIG_SYS_CACHE_STASHING
 210         /* set stash id to (coreID) * 2 + 32 + L1 CT (0) */
 211         slwi    r8,r4,1
 212         addi    r8,r8,32
 213         mtspr   L1CSR2,r8
 214 #endif
 215
 216 #if defined(CONFIG_SYS_P4080_ERRATUM_CPU22) || \
 217         defined(CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011)
 218         /*
 219          * CPU22 applies to P4080 rev 1.0, 2.0, fixed in 3.0
 220          * NMG_CPU_A011 applies to P4080 rev 1.0, 2.0, fixed in 3.0
 221          * also appleis to P3041 rev 1.0, 1.1, P2041 rev 1.0, 1.1
 222          */
 223         mfspr   r3,SPRN_SVR
 224         rlwinm  r6,r3,24,~0x800         /* clear E bit */
 225
 226         lis     r5,SVR_P4080@h
 227         ori     r5,r5,SVR_P4080@l
 228         cmpw    r6,r5
 229         bne     1f
 230
 231         rlwinm  r3,r3,0,0xf0
 232         li      r5,0x30
 233         cmpw    r3,r5
 234         bge     2f
 235 1:
 236 #ifdef  CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011
 237         lis     r3,toreset(enable_cpu_a011_workaround)@ha
 238         lwz     r3,toreset(enable_cpu_a011_workaround)@l(r3)
 239         cmpwi   r3,0
 240         beq     2f
 241 #endif
 242         mfspr   r3,L1CSR2
 243         oris    r3,r3,(L1CSR2_DCWS)@h
 244         mtspr   L1CSR2,r3
 245 2:
 246 #endif
 247
 248 #ifdef CONFIG_BACKSIDE_L2_CACHE
 249         /* skip L2 setup on P2040/P2040E as they have no L2 */
 250         mfspr   r3,SPRN_SVR
 251         rlwinm  r6,r3,24,~0x800         /* clear E bit of SVR */
 252
 253         lis     r3,SVR_P2040@h
 254         ori     r3,r3,SVR_P2040@l
 255         cmpw    r6,r3
 256         beq 3f
 257
 258         /* Enable/invalidate the L2 cache */
 259         msync
 260         lis     r2,(L2CSR0_L2FI|L2CSR0_L2LFC)@h
 261         ori     r2,r2,(L2CSR0_L2FI|L2CSR0_L2LFC)@l
 262         mtspr   SPRN_L2CSR0,r2
 263 1:
 264         mfspr   r3,SPRN_L2CSR0
 265         and.    r1,r3,r2
 266         bne     1b
 267
 268 #ifdef CONFIG_SYS_CACHE_STASHING
 269         /* set stash id to (coreID) * 2 + 32 + L2 (1) */
 270         addi    r3,r8,1
 271         mtspr   SPRN_L2CSR1,r3
 272 #endif
 273
 274         lis     r3,CONFIG_SYS_INIT_L2CSR0@h
 275         ori     r3,r3,CONFIG_SYS_INIT_L2CSR0@l
 276         mtspr   SPRN_L2CSR0,r3
 277         isync
 278 2:
 279         mfspr   r3,SPRN_L2CSR0
 280         andis.  r1,r3,L2CSR0_L2E@h
 281         beq     2b
 282 #endif
 283 3:
 284         /* setup mapping for the spin table, WIMGE=0b00100 */
 285         lis     r13,toreset(__spin_table_addr)@h
 286         ori     r13,r13,toreset(__spin_table_addr)@l
 287         lwz     r13,0(r13)
 288         /* mask by 4K */
 289         rlwinm  r13,r13,0,0,19
 290
 291         lis     r11,(MAS0_TLBSEL(1)|MAS0_ESEL(1))@h
 292         mtspr   SPRN_MAS0,r11
 293         lis     r11,(MAS1_VALID|MAS1_IPROT)@h
 294         ori     r11,r11,(MAS1_TS|MAS1_TSIZE(BOOKE_PAGESZ_4K))@l
 295         mtspr   SPRN_MAS1,r11
 296         oris    r11,r13,(MAS2_M|MAS2_G)@h
 297         ori     r11,r13,(MAS2_M|MAS2_G)@l
 298         mtspr   SPRN_MAS2,r11
 299         oris    r11,r13,(MAS3_SX|MAS3_SW|MAS3_SR)@h
 300         ori     r11,r13,(MAS3_SX|MAS3_SW|MAS3_SR)@l
 301         mtspr   SPRN_MAS3,r11
 302         li      r11,0
 303         mtspr   SPRN_MAS7,r11
 304         tlbwe
 305
 306         /*
 307          * __bootpg_addr has the address of __second_half_boot_page
 308          * jump there in AS=1 space with cache enabled
 309          */
 310         lis     r13,toreset(__bootpg_addr)@h
 311         ori     r13,r13,toreset(__bootpg_addr)@l
 312         lwz     r11,0(r13)
 313         mtspr   SPRN_SRR0,r11
 314         mfmsr   r13
 315         ori     r12,r13,MSR_IS|MSR_DS@l
 316         mtspr   SPRN_SRR1,r12
 317         rfi
 318
 319         /*
 320          * Allocate some space for the SDRAM address of the bootpg.
 321          * This variable has to be in the boot page so that it can
 322          * be accessed by secondary cores when they come out of reset.
 323          */
 324         .align L1_CACHE_SHIFT
 325         .globl __bootpg_addr
 326 __bootpg_addr:
 327         .long   0
 328
 329         .global __spin_table_addr
 330 __spin_table_addr:
 331         .long   0
 332
 333         /*
 334          * This variable is set by cpu_init_r() after parsing hwconfig
 335          * to enable workaround for erratum NMG_CPU_A011.
 336          */
 337         .align L1_CACHE_SHIFT
 338         .global enable_cpu_a011_workaround
 339 enable_cpu_a011_workaround:
 340         .long   1
 341
 342         /* Fill in the empty space.  The actual reset vector is
 343          * the last word of the page */
 344 __secondary_start_code_end:
 345         .space 4092 - (__secondary_start_code_end - __secondary_start_page)
 346 __secondary_reset_vector:
 347         b       __secondary_start_page
 348
 349
 350 /* this is a separated page for the spin table and cacheable boot code */
 351         .align L1_CACHE_SHIFT
 352         .global __second_half_boot_page
 353 __second_half_boot_page:
 354 #define EPAPR_MAGIC             0x45504150
 355 #define ENTRY_ADDR_UPPER        0
 356 #define ENTRY_ADDR_LOWER        4
 357 #define ENTRY_R3_UPPER          8
 358 #define ENTRY_R3_LOWER          12
 359 #define ENTRY_RESV              16
 360 #define ENTRY_PIR               20
 361 #define ENTRY_SIZE              64
 362         /*
 363          * setup the entry
 364          * r10 has the base address of the spin table.
 365          * spin table is defined as
 366          * struct {
 367          *      uint64_t entry_addr;
 368          *      uint64_t r3;
 369          *      uint32_t rsvd1;
 370          *      uint32_t pir;
 371          * };
 372          * we pad this struct to 64 bytes so each entry is in its own cacheline
 373          */
 374         li      r3,0
 375         li      r8,1
 376         mfspr   r4,SPRN_PIR
 377         stw     r3,ENTRY_ADDR_UPPER(r10)
 378         stw     r3,ENTRY_R3_UPPER(r10)
 379         stw     r4,ENTRY_R3_LOWER(r10)
 380         stw     r3,ENTRY_RESV(r10)
 381         stw     r4,ENTRY_PIR(r10)
 382         msync
 383         stw     r8,ENTRY_ADDR_LOWER(r10)
 384
 385         /* spin waiting for addr */
 386 3:      lwz     r4,ENTRY_ADDR_LOWER(r10)
 387         andi.   r11,r4,1
 388         bne     3b
 389         isync
 390
 391         /* setup IVORs to match fixed offsets */
 392 #include "fixed_ivor.S"
 393
 394         /* get the upper bits of the addr */
 395         lwz     r11,ENTRY_ADDR_UPPER(r10)
 396
 397         /* setup branch addr */
 398         mtspr   SPRN_SRR0,r4
 399
 400         /* mark the entry as released */
 401         li      r8,3
 402         stw     r8,ENTRY_ADDR_LOWER(r10)
 403
 404         /* mask by ~64M to setup our tlb we will jump to */
 405         rlwinm  r12,r4,0,0,5
 406
 407         /*
 408          * setup r3, r4, r5, r6, r7, r8, r9
 409          * r3 contains the value to put in the r3 register at secondary cpu
 410          * entry. The high 32-bits are ignored on 32-bit chip implementations.
 411          * 64-bit chip implementations however shall load all 64-bits
 412          */
 413 #ifdef CONFIG_SYS_PPC64
 414         ld      r3,ENTRY_R3_UPPER(r10)
 415 #else
 416         lwz     r3,ENTRY_R3_LOWER(r10)
 417 #endif
 418         li      r4,0
 419         li      r5,0
 420         li      r6,0
 421         lis     r7,(64*1024*1024)@h
 422         li      r8,0
 423         li      r9,0
 424
 425         /* load up the pir */
 426         lwz     r0,ENTRY_PIR(r10)
 427         mtspr   SPRN_PIR,r0
 428         mfspr   r0,SPRN_PIR
 429         stw     r0,ENTRY_PIR(r10)
 430
 431         mtspr   IVPR,r12
 432 /*
 433  * Coming here, we know the cpu has one TLB mapping in TLB1[0]
 434  * which maps 0xfffff000-0xffffffff one-to-one.  We set up a
 435  * second mapping that maps addr 1:1 for 64M, and then we jump to
 436  * addr
 437  */
 438         lis     r10,(MAS0_TLBSEL(1)|MAS0_ESEL(0))@h
 439         mtspr   SPRN_MAS0,r10
 440         lis     r10,(MAS1_VALID|MAS1_IPROT)@h
 441         ori     r10,r10,(MAS1_TSIZE(BOOKE_PAGESZ_64M))@l
 442         mtspr   SPRN_MAS1,r10
 443         /* WIMGE = 0b00000 for now */
 444         mtspr   SPRN_MAS2,r12
 445         ori     r12,r12,(MAS3_SX|MAS3_SW|MAS3_SR)
 446         mtspr   SPRN_MAS3,r12
 447 #ifdef CONFIG_ENABLE_36BIT_PHYS
 448         mtspr   SPRN_MAS7,r11
 449 #endif
 450         tlbwe
 451
 452 /* Now we have another mapping for this page, so we jump to that
 453  * mapping
 454  */
 455         mtspr   SPRN_SRR1,r13
 456         rfi
 457
 458
 459         .align 6
 460         .globl __spin_table
 461 __spin_table:
 462         .space CONFIG_MAX_CPUS*ENTRY_SIZE
 463 __spin_table_end:
 464         .space 4096 - (__spin_table_end - __spin_table)