arch/powerpc/cpu/mpc85xx/u-boot-spl.lds

   1 /*
   2  * (C) Copyright 2006
   3  * Wolfgang Denk, DENX Software Engineering, wd@denx.de
   4  *
   5  * Copyright 2009 Freescale Semiconductor, Inc.
   6  *
   7  * SPDX-License-Identifier:     GPL-2.0+
   8  */
   9
  10 #include "config.h"     /* CONFIG_BOARDDIR */
  11
  12 OUTPUT_ARCH(powerpc)
  13 #ifdef CONFIG_SYS_MPC85XX_NO_RESETVEC
  14 PHDRS
  15 {
  16         text PT_LOAD;
  17         bss PT_LOAD;
  18 }
  19 #endif
  20 SECTIONS
  21 {
  22         . = CONFIG_SPL_TEXT_BASE;
  23         .text : {
  24                 *(.text*)
  25         }
  26         _etext = .;
  27
  28         .reloc : {
  29                 _GOT2_TABLE_ = .;
  30                 KEEP(*(.got2))
  31                 KEEP(*(.got))
  32                 PROVIDE(_GLOBAL_OFFSET_TABLE_ = . + 4);
  33                 _FIXUP_TABLE_ = .;
  34                 KEEP(*(.fixup))
  35         }
  36         __got2_entries = ((_GLOBAL_OFFSET_TABLE_ - _GOT2_TABLE_) >> 2) - 1;
  37         __fixup_entries = (. - _FIXUP_TABLE_) >> 2;
  38
  39         . = ALIGN(8);
  40         .data : {
  41                 *(.rodata*)
  42                 *(.data*)
  43                 *(.sdata*)
  44         }
  45         _edata  =  .;
  46
  47         . = ALIGN(8);
  48         __init_begin = .;
  49         __init_end = .;
  50 /* FIXME for non-NAND SPL */
  51 #if defined(CONFIG_FSL_IFC) /* Restrict bootpg at 4K boundry for IFC */
  52         .bootpg ADDR(.text) + 0x1000 :
  53         {
  54                 arch/powerpc/cpu/mpc85xx/start.o (.bootpg)
  55         }
  56 #define RESET_VECTOR_OFFSET 0x1ffc /* IFC has 8K sram */
  57 #elif defined(CONFIG_FSL_ELBC)
  58 #define RESET_VECTOR_OFFSET 0xffc /* LBC has 4k sram */
  59 #else
  60 #error unknown NAND controller
  61 #endif
  62 #ifdef CONFIG_SYS_MPC85XX_NO_RESETVEC
  63         .bootpg ADDR(.text) - 0x1000 :
  64         {
  65                 KEEP(*(.bootpg))
  66         } :text = 0xffff
  67 #else
  68         .resetvec ADDR(.text) + RESET_VECTOR_OFFSET : {
  69                 KEEP(*(.resetvec))
  70         } = 0xffff
  71 #endif
  72
  73         /*
  74          * Make sure that the bss segment isn't linked at 0x0, otherwise its
  75          * address won't be updated during relocation fixups.
  76          */
  77         . |= 0x10;
  78
  79         . = ALIGN(4);
  80         __bss_start = .;
  81         .bss : {
  82                 *(.sbss*)
  83                 *(.bss*)
  84         }
  85         . = ALIGN(4);
  86         __bss_end = .;
  87 }