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git.ipfire.org Git - people/ms/u-boot.git/blob - arch/powerpc/cpu/mpc86xx/interrupts.c
2 * (C) Copyright 2000-2002
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * (C) Copyright 2002 (440 port)
6 * Scott McNutt, Artesyn Communication Producs, smcnutt@artsyncp.com
8 * (C) Copyright 2003 Motorola Inc. (MPC85xx port)
9 * Xianghua Xiao (X.Xiao@motorola.com)
11 * (C) Copyright 2004, 2007 Freescale Semiconductor. (MPC86xx Port)
13 * Srikanth Srinivasan (srikanth.srinivasan@freescale.com)
15 * See file CREDITS for list of people who contributed to this
18 * This program is free software; you can redistribute it and/or
19 * modify it under the terms of the GNU General Public License as
20 * published by the Free Software Foundation; either version 2 of
21 * the License, or (at your option) any later version.
23 * This program is distributed in the hope that it will be useful,
24 * but WITHOUT ANY WARRANTY; without even the implied warranty of
25 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
26 * GNU General Public License for more details.
28 * You should have received a copy of the GNU General Public License
29 * along with this program; if not, write to the Free Software
30 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
37 #include <asm/processor.h>
42 int interrupt_init_cpu(unsigned long *decrementer_count
)
44 volatile immap_t
*immr
= (immap_t
*)CONFIG_SYS_IMMR
;
45 volatile ccsr_pic_t
*pic
= &immr
->im_pic
;
49 * The POST word is stored in the PIC's TFRR register which gets
50 * cleared when the PIC is reset. Save it off so we can restore it
53 ulong post_word
= post_word_load();
56 pic
->gcr
= MPC86xx_PICGCR_RST
;
57 while (pic
->gcr
& MPC86xx_PICGCR_RST
)
59 pic
->gcr
= MPC86xx_PICGCR_MODE
;
61 *decrementer_count
= get_tbclk() / CONFIG_SYS_HZ
;
62 debug("interrupt init: tbclk() = %ld MHz, decrementer_count = %ld\n",
63 (get_tbclk() / 1000000),
66 #ifdef CONFIG_INTERRUPTS
68 pic
->iivpr1
= 0x810001; /* 50220 enable mcm interrupts */
69 debug("iivpr1@%p = %x\n", &pic
->iivpr1
, pic
->iivpr1
);
71 pic
->iivpr2
= 0x810002; /* 50240 enable ddr interrupts */
72 debug("iivpr2@%p = %x\n", &pic
->iivpr2
, pic
->iivpr2
);
74 pic
->iivpr3
= 0x810003; /* 50260 enable lbc interrupts */
75 debug("iivpr3@%p = %x\n", &pic
->iivpr3
, pic
->iivpr3
);
77 #if defined(CONFIG_PCI1) || defined(CONFIG_PCIE1)
78 pic
->iivpr8
= 0x810008; /* enable pcie1 interrupts */
79 debug("iivpr8@%p = %x\n", &pic
->iivpr8
, pic
->iivpr8
);
81 #if defined(CONFIG_PCI2) || defined(CONFIG_PCIE2)
82 pic
->iivpr9
= 0x810009; /* enable pcie2 interrupts */
83 debug("iivpr9@%p = %x\n", &pic
->iivpr9
, pic
->iivpr9
);
86 pic
->ctpr
= 0; /* 40080 clear current task priority register */
90 post_word_store(post_word
);
97 * timer_interrupt - gets called when the decrementer overflows,
98 * with interrupts disabled.
99 * Trivial implementation - no need to be really accurate.
101 void timer_interrupt_cpu(struct pt_regs
*regs
)
103 /* nothing to do here */
107 * Install and free a interrupt handler. Not implemented yet.
109 void irq_install_handler(int vec
, interrupt_handler_t
*handler
, void *arg
)
113 void irq_free_handler(int vec
)
118 * irqinfo - print information about PCI devices,not implemented.
120 int do_irqinfo(cmd_tbl_t
*cmdtp
, int flag
, int argc
, char * const argv
[])
126 * Handle external interrupts
128 void external_interrupt(struct pt_regs
*regs
)
130 puts("external_interrupt (oops!)\n");