arch/powerpc/cpu/mpc8xx/interrupts.c

   1 /*
   2  * (C) Copyright 2000-2002
   3  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0+
   6  */
   7
   8 #include <common.h>
   9 #include <mpc8xx.h>
  10 #include <mpc8xx_irq.h>
  11 #include <asm/processor.h>
  12 #include <commproc.h>
  13
  14 /************************************************************************/
  15
  16 /*
  17  * CPM interrupt vector functions.
  18  */
  19 struct interrupt_action {
  20         interrupt_handler_t *handler;
  21         void *arg;
  22 };
  23
  24 static struct interrupt_action cpm_vecs[CPMVEC_NR];
  25 static struct interrupt_action irq_vecs[NR_IRQS];
  26
  27 static void cpm_interrupt_init (void);
  28 static void cpm_interrupt (void *regs);
  29
  30 /************************************************************************/
  31
  32 int interrupt_init_cpu (unsigned *decrementer_count)
  33 {
  34         volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
  35
  36         *decrementer_count = get_tbclk () / CONFIG_SYS_HZ;
  37
  38         /* disable all interrupts */
  39         immr->im_siu_conf.sc_simask = 0;
  40
  41         /* Configure CPM interrupts */
  42         cpm_interrupt_init ();
  43
  44         return (0);
  45 }
  46
  47 /************************************************************************/
  48
  49 /*
  50  * Handle external interrupts
  51  */
  52 void external_interrupt (struct pt_regs *regs)
  53 {
  54         volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
  55         int irq;
  56         ulong simask, newmask;
  57         ulong vec, v_bit;
  58
  59         /*
  60          * read the SIVEC register and shift the bits down
  61          * to get the irq number
  62          */
  63         vec = immr->im_siu_conf.sc_sivec;
  64         irq = vec >> 26;
  65         v_bit = 0x80000000UL >> irq;
  66
  67         /*
  68          * Read Interrupt Mask Register and Mask Interrupts
  69          */
  70         simask = immr->im_siu_conf.sc_simask;
  71         newmask = simask & (~(0xFFFF0000 >> irq));
  72         immr->im_siu_conf.sc_simask = newmask;
  73
  74         if (!(irq & 0x1)) {             /* External Interrupt ?     */
  75                 ulong siel;
  76
  77                 /*
  78                  * Read Interrupt Edge/Level Register
  79                  */
  80                 siel = immr->im_siu_conf.sc_siel;
  81
  82                 if (siel & v_bit) {     /* edge triggered interrupt ?   */
  83                         /*
  84                          * Rewrite SIPEND Register to clear interrupt
  85                          */
  86                         immr->im_siu_conf.sc_sipend = v_bit;
  87                 }
  88         }
  89
  90         if (irq_vecs[irq].handler != NULL) {
  91                 irq_vecs[irq].handler (irq_vecs[irq].arg);
  92         } else {
  93                 printf ("\nBogus External Interrupt IRQ %d Vector %ld\n",
  94                                 irq, vec);
  95                 /* turn off the bogus interrupt to avoid it from now */
  96                 simask &= ~v_bit;
  97         }
  98         /*
  99          * Re-Enable old Interrupt Mask
 100          */
 101         immr->im_siu_conf.sc_simask = simask;
 102 }
 103
 104 /************************************************************************/
 105
 106 /*
 107  * CPM interrupt handler
 108  */
 109 static void cpm_interrupt (void *regs)
 110 {
 111         volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
 112         uint vec;
 113
 114         /*
 115          * Get the vector by setting the ACK bit
 116          * and then reading the register.
 117          */
 118         immr->im_cpic.cpic_civr = 1;
 119         vec = immr->im_cpic.cpic_civr;
 120         vec >>= 11;
 121
 122         if (cpm_vecs[vec].handler != NULL) {
 123                 (*cpm_vecs[vec].handler) (cpm_vecs[vec].arg);
 124         } else {
 125                 immr->im_cpic.cpic_cimr &= ~(1 << vec);
 126                 printf ("Masking bogus CPM interrupt vector 0x%x\n", vec);
 127         }
 128         /*
 129          * After servicing the interrupt,
 130          * we have to remove the status indicator.
 131          */
 132         immr->im_cpic.cpic_cisr |= (1 << vec);
 133 }
 134
 135 /*
 136  * The CPM can generate the error interrupt when there is a race
 137  * condition between generating and masking interrupts. All we have
 138  * to do is ACK it and return. This is a no-op function so we don't
 139  * need any special tests in the interrupt handler.
 140  */
 141 static void cpm_error_interrupt (void *dummy)
 142 {
 143 }
 144
 145 /************************************************************************/
 146 /*
 147  * Install and free an interrupt handler
 148  */
 149 void irq_install_handler (int vec, interrupt_handler_t * handler,
 150                                                   void *arg)
 151 {
 152         volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
 153
 154         if ((vec & CPMVEC_OFFSET) != 0) {
 155                 /* CPM interrupt */
 156                 vec &= 0xffff;
 157                 if (cpm_vecs[vec].handler != NULL) {
 158                         printf ("CPM interrupt 0x%x replacing 0x%x\n",
 159                                 (uint) handler,
 160                                 (uint) cpm_vecs[vec].handler);
 161                 }
 162                 cpm_vecs[vec].handler = handler;
 163                 cpm_vecs[vec].arg = arg;
 164                 immr->im_cpic.cpic_cimr |= (1 << vec);
 165         } else {
 166                 /* SIU interrupt */
 167                 if (irq_vecs[vec].handler != NULL) {
 168                         printf ("SIU interrupt %d 0x%x replacing 0x%x\n",
 169                                 vec,
 170                                 (uint) handler,
 171                                 (uint) cpm_vecs[vec].handler);
 172                 }
 173                 irq_vecs[vec].handler = handler;
 174                 irq_vecs[vec].arg = arg;
 175                 immr->im_siu_conf.sc_simask |= 1 << (31 - vec);
 176         }
 177 }
 178
 179 void irq_free_handler (int vec)
 180 {
 181         volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
 182
 183         if ((vec & CPMVEC_OFFSET) != 0) {
 184                 /* CPM interrupt */
 185                 vec &= 0xffff;
 186                 immr->im_cpic.cpic_cimr &= ~(1 << vec);
 187                 cpm_vecs[vec].handler = NULL;
 188                 cpm_vecs[vec].arg = NULL;
 189         } else {
 190                 /* SIU interrupt */
 191                 immr->im_siu_conf.sc_simask &= ~(1 << (31 - vec));
 192                 irq_vecs[vec].handler = NULL;
 193                 irq_vecs[vec].arg = NULL;
 194         }
 195 }
 196
 197 /************************************************************************/
 198
 199 static void cpm_interrupt_init (void)
 200 {
 201         volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
 202
 203         /*
 204          * Initialize the CPM interrupt controller.
 205          */
 206
 207         immr->im_cpic.cpic_cicr =
 208                 (CICR_SCD_SCC4 |
 209                  CICR_SCC_SCC3 |
 210                  CICR_SCB_SCC2 |
 211                  CICR_SCA_SCC1) | ((CPM_INTERRUPT / 2) << 13) | CICR_HP_MASK;
 212
 213         immr->im_cpic.cpic_cimr = 0;
 214
 215         /*
 216          * Install the error handler.
 217          */
 218         irq_install_handler (CPMVEC_ERROR, cpm_error_interrupt, NULL);
 219
 220         immr->im_cpic.cpic_cicr |= CICR_IEN;
 221
 222         /*
 223          * Install the cpm interrupt handler
 224          */
 225         irq_install_handler (CPM_INTERRUPT, cpm_interrupt, NULL);
 226 }
 227
 228 /************************************************************************/
 229
 230 /*
 231  * timer_interrupt - gets called when the decrementer overflows,
 232  * with interrupts disabled.
 233  * Trivial implementation - no need to be really accurate.
 234  */
 235 void timer_interrupt_cpu (struct pt_regs *regs)
 236 {
 237         volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
 238
 239         /* Reset Timer Expired and Timers Interrupt Status */
 240         immr->im_clkrstk.cark_plprcrk = KAPWR_KEY;
 241         __asm__ ("nop");
 242         /*
 243           Clear TEXPS (and TMIST on older chips). SPLSS (on older
 244           chips) is cleared too.
 245
 246           Bitwise OR is a read-modify-write operation so ALL bits
 247           which are cleared by writing `1' would be cleared by
 248           operations like
 249
 250           immr->im_clkrst.car_plprcr |= PLPRCR_TEXPS;
 251
 252           The same can be achieved by simple writing of the PLPRCR
 253           to itself. If a bit value should be preserved, read the
 254           register, ZERO the bit and write, not OR, the result back.
 255         */
 256         immr->im_clkrst.car_plprcr = immr->im_clkrst.car_plprcr;
 257 }
 258
 259 /************************************************************************/