arch/powerpc/cpu/mpc8xx/serial.c

   1 /*
   2  * (C) Copyright 2000
   3  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0+
   6  */
   7
   8 #include <common.h>
   9 #include <commproc.h>
  10 #include <command.h>
  11 #include <serial.h>
  12 #include <watchdog.h>
  13 #include <linux/compiler.h>
  14
  15 DECLARE_GLOBAL_DATA_PTR;
  16
  17 #if !defined(CONFIG_8xx_CONS_NONE)      /* No Console at all */
  18
  19 #if defined(CONFIG_8xx_CONS_SMC1)       /* Console on SMC1 */
  20 #define SMC_INDEX       0
  21 #define PROFF_SMC       PROFF_SMC1
  22 #define CPM_CR_CH_SMC   CPM_CR_CH_SMC1
  23
  24 #elif defined(CONFIG_8xx_CONS_SMC2)     /* Console on SMC2 */
  25 #define SMC_INDEX       1
  26 #define PROFF_SMC       PROFF_SMC2
  27 #define CPM_CR_CH_SMC   CPM_CR_CH_SMC2
  28
  29 #endif /* CONFIG_8xx_CONS_SMCx */
  30
  31 #if defined(CONFIG_8xx_CONS_SCC1)       /* Console on SCC1 */
  32 #define SCC_INDEX       0
  33 #define PROFF_SCC       PROFF_SCC1
  34 #define CPM_CR_CH_SCC   CPM_CR_CH_SCC1
  35
  36 #elif defined(CONFIG_8xx_CONS_SCC2)     /* Console on SCC2 */
  37 #define SCC_INDEX       1
  38 #define PROFF_SCC       PROFF_SCC2
  39 #define CPM_CR_CH_SCC   CPM_CR_CH_SCC2
  40
  41 #elif defined(CONFIG_8xx_CONS_SCC3)     /* Console on SCC3 */
  42 #define SCC_INDEX       2
  43 #define PROFF_SCC       PROFF_SCC3
  44 #define CPM_CR_CH_SCC   CPM_CR_CH_SCC3
  45
  46 #elif defined(CONFIG_8xx_CONS_SCC4)     /* Console on SCC4 */
  47 #define SCC_INDEX       3
  48 #define PROFF_SCC       PROFF_SCC4
  49 #define CPM_CR_CH_SCC   CPM_CR_CH_SCC4
  50
  51 #endif /* CONFIG_8xx_CONS_SCCx */
  52
  53 #if !defined(CONFIG_SYS_SMC_RXBUFLEN)
  54 #define CONFIG_SYS_SMC_RXBUFLEN 1
  55 #define CONFIG_SYS_MAXIDLE      0
  56 #else
  57 #if !defined(CONFIG_SYS_MAXIDLE)
  58 #error "you must define CONFIG_SYS_MAXIDLE"
  59 #endif
  60 #endif
  61
  62 typedef volatile struct serialbuffer {
  63         cbd_t   rxbd;           /* Rx BD */
  64         cbd_t   txbd;           /* Tx BD */
  65         uint    rxindex;        /* index for next character to read */
  66         volatile uchar  rxbuf[CONFIG_SYS_SMC_RXBUFLEN];/* rx buffers */
  67         volatile uchar  txbuf;  /* tx buffers */
  68 } serialbuffer_t;
  69
  70 static void serial_setdivisor(volatile cpm8xx_t *cp)
  71 {
  72         int divisor=(gd->cpu_clk + 8*gd->baudrate)/16/gd->baudrate;
  73
  74         if(divisor/16>0x1000) {
  75                 /* bad divisor, assume 50MHz clock and 9600 baud */
  76                 divisor=(50*1000*1000 + 8*9600)/16/9600;
  77         }
  78
  79 #ifdef CONFIG_SYS_BRGCLK_PRESCALE
  80         divisor /= CONFIG_SYS_BRGCLK_PRESCALE;
  81 #endif
  82
  83         if(divisor<=0x1000) {
  84                 cp->cp_brgc1=((divisor-1)<<1) | CPM_BRG_EN;
  85         } else {
  86                 cp->cp_brgc1=((divisor/16-1)<<1) | CPM_BRG_EN | CPM_BRG_DIV16;
  87         }
  88 }
  89
  90 #if (defined (CONFIG_8xx_CONS_SMC1) || defined (CONFIG_8xx_CONS_SMC2))
  91
  92 /*
  93  * Minimal serial functions needed to use one of the SMC ports
  94  * as serial console interface.
  95  */
  96
  97 static void smc_setbrg (void)
  98 {
  99         volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
 100         volatile cpm8xx_t *cp = &(im->im_cpm);
 101
 102         /* Set up the baud rate generator.
 103          * See 8xx_io/commproc.c for details.
 104          *
 105          * Wire BRG1 to SMCx
 106          */
 107
 108         cp->cp_simode = 0x00000000;
 109
 110         serial_setdivisor(cp);
 111 }
 112
 113 static int smc_init (void)
 114 {
 115         volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
 116         volatile smc_t *sp;
 117         volatile smc_uart_t *up;
 118         volatile cpm8xx_t *cp = &(im->im_cpm);
 119 #if (!defined(CONFIG_8xx_CONS_SMC1)) && (defined(CONFIG_MPC823) || defined(CONFIG_MPC850))
 120         volatile iop8xx_t *ip = (iop8xx_t *)&(im->im_ioport);
 121 #endif
 122         uint    dpaddr;
 123         volatile serialbuffer_t *rtx;
 124
 125         /* initialize pointers to SMC */
 126
 127         sp = (smc_t *) &(cp->cp_smc[SMC_INDEX]);
 128         up = (smc_uart_t *) &cp->cp_dparam[PROFF_SMC];
 129 #ifdef CONFIG_SYS_SMC_UCODE_PATCH
 130         up = (smc_uart_t *) &cp->cp_dpmem[up->smc_rpbase];
 131 #else
 132         /* Disable relocation */
 133         up->smc_rpbase = 0;
 134 #endif
 135
 136         /* Disable transmitter/receiver. */
 137         sp->smc_smcmr &= ~(SMCMR_REN | SMCMR_TEN);
 138
 139         /* Enable SDMA. */
 140         im->im_siu_conf.sc_sdcr = 1;
 141
 142         /* clear error conditions */
 143 #ifdef  CONFIG_SYS_SDSR
 144         im->im_sdma.sdma_sdsr = CONFIG_SYS_SDSR;
 145 #else
 146         im->im_sdma.sdma_sdsr = 0x83;
 147 #endif
 148
 149         /* clear SDMA interrupt mask */
 150 #ifdef  CONFIG_SYS_SDMR
 151         im->im_sdma.sdma_sdmr = CONFIG_SYS_SDMR;
 152 #else
 153         im->im_sdma.sdma_sdmr = 0x00;
 154 #endif
 155
 156 #if defined(CONFIG_8xx_CONS_SMC1)
 157         /* Use Port B for SMC1 instead of other functions. */
 158         cp->cp_pbpar |=  0x000000c0;
 159         cp->cp_pbdir &= ~0x000000c0;
 160         cp->cp_pbodr &= ~0x000000c0;
 161 #else   /* CONFIG_8xx_CONS_SMC2 */
 162 # if defined(CONFIG_MPC823) || defined(CONFIG_MPC850)
 163         /* Use Port A for SMC2 instead of other functions. */
 164         ip->iop_papar |=  0x00c0;
 165         ip->iop_padir &= ~0x00c0;
 166         ip->iop_paodr &= ~0x00c0;
 167 # else  /* must be a 860 then */
 168         /* Use Port B for SMC2 instead of other functions.
 169          */
 170         cp->cp_pbpar |=  0x00000c00;
 171         cp->cp_pbdir &= ~0x00000c00;
 172         cp->cp_pbodr &= ~0x00000c00;
 173 # endif
 174 #endif
 175
 176         /* Set the physical address of the host memory buffers in
 177          * the buffer descriptors.
 178          */
 179         dpaddr = CPM_SERIAL_BASE;
 180
 181         rtx = (serialbuffer_t *)&cp->cp_dpmem[dpaddr];
 182         /* Allocate space for two buffer descriptors in the DP ram.
 183          * For now, this address seems OK, but it may have to
 184          * change with newer versions of the firmware.
 185          * damm: allocating space after the two buffers for rx/tx data
 186          */
 187
 188         rtx->rxbd.cbd_bufaddr = (uint) &rtx->rxbuf;
 189         rtx->rxbd.cbd_sc      = 0;
 190
 191         rtx->txbd.cbd_bufaddr = (uint) &rtx->txbuf;
 192         rtx->txbd.cbd_sc      = 0;
 193
 194         /* Set up the uart parameters in the parameter ram. */
 195         up->smc_rbase = dpaddr;
 196         up->smc_tbase = dpaddr+sizeof(cbd_t);
 197         up->smc_rfcr = SMC_EB;
 198         up->smc_tfcr = SMC_EB;
 199 #if defined (CONFIG_SYS_SMC_UCODE_PATCH)
 200         up->smc_rbptr = up->smc_rbase;
 201         up->smc_tbptr = up->smc_tbase;
 202         up->smc_rstate = 0;
 203         up->smc_tstate = 0;
 204 #endif
 205
 206         /* Set UART mode, 8 bit, no parity, one stop.
 207          * Enable receive and transmit.
 208          */
 209         sp->smc_smcmr = smcr_mk_clen(9) |  SMCMR_SM_UART;
 210
 211         /* Mask all interrupts and remove anything pending.
 212         */
 213         sp->smc_smcm = 0;
 214         sp->smc_smce = 0xff;
 215
 216 #ifdef CONFIG_SYS_SPC1920_SMC1_CLK4
 217         /* clock source is PLD */
 218
 219         /* set freq to 19200 Baud */
 220         *((volatile uchar *) CONFIG_SYS_SPC1920_PLD_BASE+6) = 0x3;
 221         /* configure clk4 as input */
 222         im->im_ioport.iop_pdpar |= 0x800;
 223         im->im_ioport.iop_pddir &= ~0x800;
 224
 225         cp->cp_simode = ((cp->cp_simode & ~0xf000) | 0x7000);
 226 #else
 227         /* Set up the baud rate generator */
 228         smc_setbrg ();
 229 #endif
 230
 231         /* Make the first buffer the only buffer. */
 232         rtx->txbd.cbd_sc |= BD_SC_WRAP;
 233         rtx->rxbd.cbd_sc |= BD_SC_EMPTY | BD_SC_WRAP;
 234
 235         /* single/multi character receive. */
 236         up->smc_mrblr = CONFIG_SYS_SMC_RXBUFLEN;
 237         up->smc_maxidl = CONFIG_SYS_MAXIDLE;
 238         rtx->rxindex = 0;
 239
 240         /* Initialize Tx/Rx parameters. */
 241         while (cp->cp_cpcr & CPM_CR_FLG)  /* wait if cp is busy */
 242           ;
 243
 244         cp->cp_cpcr = mk_cr_cmd(CPM_CR_CH_SMC, CPM_CR_INIT_TRX) | CPM_CR_FLG;
 245
 246         while (cp->cp_cpcr & CPM_CR_FLG)  /* wait if cp is busy */
 247           ;
 248
 249         /* Enable transmitter/receiver. */
 250         sp->smc_smcmr |= SMCMR_REN | SMCMR_TEN;
 251
 252         return (0);
 253 }
 254
 255 static void
 256 smc_putc(const char c)
 257 {
 258         volatile smc_uart_t     *up;
 259         volatile immap_t        *im = (immap_t *)CONFIG_SYS_IMMR;
 260         volatile cpm8xx_t       *cpmp = &(im->im_cpm);
 261         volatile serialbuffer_t *rtx;
 262
 263         if (c == '\n')
 264                 smc_putc ('\r');
 265
 266         up = (smc_uart_t *)&cpmp->cp_dparam[PROFF_SMC];
 267 #ifdef CONFIG_SYS_SMC_UCODE_PATCH
 268         up = (smc_uart_t *) &cpmp->cp_dpmem[up->smc_rpbase];
 269 #endif
 270
 271         rtx = (serialbuffer_t *)&cpmp->cp_dpmem[up->smc_rbase];
 272
 273         /* Wait for last character to go. */
 274         rtx->txbuf = c;
 275         rtx->txbd.cbd_datlen = 1;
 276         rtx->txbd.cbd_sc |= BD_SC_READY;
 277         __asm__("eieio");
 278
 279         while (rtx->txbd.cbd_sc & BD_SC_READY) {
 280                 WATCHDOG_RESET ();
 281                 __asm__("eieio");
 282         }
 283 }
 284
 285 static void
 286 smc_puts (const char *s)
 287 {
 288         while (*s) {
 289                 smc_putc (*s++);
 290         }
 291 }
 292
 293 static int
 294 smc_getc(void)
 295 {
 296         volatile smc_uart_t     *up;
 297         volatile immap_t        *im = (immap_t *)CONFIG_SYS_IMMR;
 298         volatile cpm8xx_t       *cpmp = &(im->im_cpm);
 299         volatile serialbuffer_t *rtx;
 300         unsigned char  c;
 301
 302         up = (smc_uart_t *)&cpmp->cp_dparam[PROFF_SMC];
 303 #ifdef CONFIG_SYS_SMC_UCODE_PATCH
 304         up = (smc_uart_t *) &cpmp->cp_dpmem[up->smc_rpbase];
 305 #endif
 306         rtx = (serialbuffer_t *)&cpmp->cp_dpmem[up->smc_rbase];
 307
 308         /* Wait for character to show up. */
 309         while (rtx->rxbd.cbd_sc & BD_SC_EMPTY)
 310                 WATCHDOG_RESET ();
 311
 312         /* the characters are read one by one,
 313          * use the rxindex to know the next char to deliver
 314          */
 315         c = *(unsigned char *) (rtx->rxbd.cbd_bufaddr+rtx->rxindex);
 316         rtx->rxindex++;
 317
 318         /* check if all char are readout, then make prepare for next receive */
 319         if (rtx->rxindex >= rtx->rxbd.cbd_datlen) {
 320                 rtx->rxindex = 0;
 321                 rtx->rxbd.cbd_sc |= BD_SC_EMPTY;
 322         }
 323         return(c);
 324 }
 325
 326 static int
 327 smc_tstc(void)
 328 {
 329         volatile smc_uart_t     *up;
 330         volatile immap_t        *im = (immap_t *)CONFIG_SYS_IMMR;
 331         volatile cpm8xx_t       *cpmp = &(im->im_cpm);
 332         volatile serialbuffer_t *rtx;
 333
 334         up = (smc_uart_t *)&cpmp->cp_dparam[PROFF_SMC];
 335 #ifdef CONFIG_SYS_SMC_UCODE_PATCH
 336         up = (smc_uart_t *) &cpmp->cp_dpmem[up->smc_rpbase];
 337 #endif
 338
 339         rtx = (serialbuffer_t *)&cpmp->cp_dpmem[up->smc_rbase];
 340
 341         return !(rtx->rxbd.cbd_sc & BD_SC_EMPTY);
 342 }
 343
 344 struct serial_device serial_smc_device =
 345 {
 346         .name   = "serial_smc",
 347         .start  = smc_init,
 348         .stop   = NULL,
 349         .setbrg = smc_setbrg,
 350         .getc   = smc_getc,
 351         .tstc   = smc_tstc,
 352         .putc   = smc_putc,
 353         .puts   = smc_puts,
 354 };
 355
 356 #endif /* CONFIG_8xx_CONS_SMC1 || CONFIG_8xx_CONS_SMC2 */
 357
 358 #if defined(CONFIG_8xx_CONS_SCC1) || defined(CONFIG_8xx_CONS_SCC2) || \
 359     defined(CONFIG_8xx_CONS_SCC3) || defined(CONFIG_8xx_CONS_SCC4)
 360
 361 static void
 362 scc_setbrg (void)
 363 {
 364         volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
 365         volatile cpm8xx_t *cp = &(im->im_cpm);
 366
 367         /* Set up the baud rate generator.
 368          * See 8xx_io/commproc.c for details.
 369          *
 370          * Wire BRG1 to SCCx
 371          */
 372
 373         cp->cp_sicr &= ~(0x000000FF << (8 * SCC_INDEX));
 374
 375         serial_setdivisor(cp);
 376 }
 377
 378 static int scc_init (void)
 379 {
 380         volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
 381         volatile scc_t *sp;
 382         volatile scc_uart_t *up;
 383         volatile cbd_t *tbdf, *rbdf;
 384         volatile cpm8xx_t *cp = &(im->im_cpm);
 385         uint     dpaddr;
 386 #if (SCC_INDEX != 2) || !defined(CONFIG_MPC850)
 387         volatile iop8xx_t *ip = (iop8xx_t *)&(im->im_ioport);
 388 #endif
 389
 390         /* initialize pointers to SCC */
 391
 392         sp = (scc_t *) &(cp->cp_scc[SCC_INDEX]);
 393         up = (scc_uart_t *) &cp->cp_dparam[PROFF_SCC];
 394
 395         /* Disable transmitter/receiver. */
 396         sp->scc_gsmrl &= ~(SCC_GSMRL_ENR | SCC_GSMRL_ENT);
 397
 398 #if (SCC_INDEX == 2) && defined(CONFIG_MPC850)
 399         /*
 400          * The MPC850 has SCC3 on Port B
 401          */
 402         cp->cp_pbpar |=  0x06;
 403         cp->cp_pbdir &= ~0x06;
 404         cp->cp_pbodr &= ~0x06;
 405
 406 #elif (SCC_INDEX < 2)
 407         /*
 408          * Standard configuration for SCC's is on Part A
 409          */
 410         ip->iop_papar |=  ((3 << (2 * SCC_INDEX)));
 411         ip->iop_padir &= ~((3 << (2 * SCC_INDEX)));
 412         ip->iop_paodr &= ~((3 << (2 * SCC_INDEX)));
 413 #endif
 414
 415         /* Allocate space for two buffer descriptors in the DP ram. */
 416         dpaddr = dpram_alloc_align(sizeof(cbd_t)*2 + 2, 8);
 417
 418         /* Enable SDMA. */
 419         im->im_siu_conf.sc_sdcr = 0x0001;
 420
 421         /* Set the physical address of the host memory buffers in
 422          * the buffer descriptors.
 423          */
 424
 425         rbdf = (cbd_t *)&cp->cp_dpmem[dpaddr];
 426         rbdf->cbd_bufaddr = (uint) (rbdf+2);
 427         rbdf->cbd_sc = 0;
 428         tbdf = rbdf + 1;
 429         tbdf->cbd_bufaddr = ((uint) (rbdf+2)) + 1;
 430         tbdf->cbd_sc = 0;
 431
 432         /* Set up the baud rate generator. */
 433         scc_setbrg ();
 434
 435         /* Set up the uart parameters in the parameter ram. */
 436         up->scc_genscc.scc_rbase = dpaddr;
 437         up->scc_genscc.scc_tbase = dpaddr+sizeof(cbd_t);
 438
 439         /* Initialize Tx/Rx parameters. */
 440         while (cp->cp_cpcr & CPM_CR_FLG)  /* wait if cp is busy */
 441                 ;
 442         cp->cp_cpcr = mk_cr_cmd(CPM_CR_CH_SCC, CPM_CR_INIT_TRX) | CPM_CR_FLG;
 443
 444         while (cp->cp_cpcr & CPM_CR_FLG)  /* wait if cp is busy */
 445                 ;
 446
 447         up->scc_genscc.scc_rfcr  = SCC_EB | 0x05;
 448         up->scc_genscc.scc_tfcr  = SCC_EB | 0x05;
 449
 450         up->scc_genscc.scc_mrblr = 1;   /* Single character receive */
 451         up->scc_maxidl = 0;             /* disable max idle */
 452         up->scc_brkcr  = 1;             /* send one break character on stop TX */
 453         up->scc_parec  = 0;
 454         up->scc_frmec  = 0;
 455         up->scc_nosec  = 0;
 456         up->scc_brkec  = 0;
 457         up->scc_uaddr1 = 0;
 458         up->scc_uaddr2 = 0;
 459         up->scc_toseq  = 0;
 460         up->scc_char1  = 0x8000;
 461         up->scc_char2  = 0x8000;
 462         up->scc_char3  = 0x8000;
 463         up->scc_char4  = 0x8000;
 464         up->scc_char5  = 0x8000;
 465         up->scc_char6  = 0x8000;
 466         up->scc_char7  = 0x8000;
 467         up->scc_char8  = 0x8000;
 468         up->scc_rccm   = 0xc0ff;
 469
 470         /* Set low latency / small fifo. */
 471         sp->scc_gsmrh = SCC_GSMRH_RFW;
 472
 473         /* Set SCC(x) clock mode to 16x
 474          * See 8xx_io/commproc.c for details.
 475          *
 476          * Wire BRG1 to SCCn
 477          */
 478
 479         /* Set UART mode, clock divider 16 on Tx and Rx */
 480         sp->scc_gsmrl &= ~0xF;
 481         sp->scc_gsmrl |=
 482                 (SCC_GSMRL_MODE_UART | SCC_GSMRL_TDCR_16 | SCC_GSMRL_RDCR_16);
 483
 484         sp->scc_psmr  = 0;
 485         sp->scc_psmr  |= SCU_PSMR_CL;
 486
 487         /* Mask all interrupts and remove anything pending. */
 488         sp->scc_sccm = 0;
 489         sp->scc_scce = 0xffff;
 490         sp->scc_dsr  = 0x7e7e;
 491         sp->scc_psmr = 0x3000;
 492
 493         /* Make the first buffer the only buffer. */
 494         tbdf->cbd_sc |= BD_SC_WRAP;
 495         rbdf->cbd_sc |= BD_SC_EMPTY | BD_SC_WRAP;
 496
 497         /* Enable transmitter/receiver. */
 498         sp->scc_gsmrl |= (SCC_GSMRL_ENR | SCC_GSMRL_ENT);
 499
 500         return (0);
 501 }
 502
 503 static void
 504 scc_putc(const char c)
 505 {
 506         volatile cbd_t          *tbdf;
 507         volatile char           *buf;
 508         volatile scc_uart_t     *up;
 509         volatile immap_t        *im = (immap_t *)CONFIG_SYS_IMMR;
 510         volatile cpm8xx_t       *cpmp = &(im->im_cpm);
 511
 512         if (c == '\n')
 513                 scc_putc ('\r');
 514
 515         up = (scc_uart_t *)&cpmp->cp_dparam[PROFF_SCC];
 516
 517         tbdf = (cbd_t *)&cpmp->cp_dpmem[up->scc_genscc.scc_tbase];
 518
 519         /* Wait for last character to go. */
 520
 521         buf = (char *)tbdf->cbd_bufaddr;
 522
 523         *buf = c;
 524         tbdf->cbd_datlen = 1;
 525         tbdf->cbd_sc |= BD_SC_READY;
 526         __asm__("eieio");
 527
 528         while (tbdf->cbd_sc & BD_SC_READY) {
 529                 __asm__("eieio");
 530                 WATCHDOG_RESET ();
 531         }
 532 }
 533
 534 static void
 535 scc_puts (const char *s)
 536 {
 537         while (*s) {
 538                 scc_putc (*s++);
 539         }
 540 }
 541
 542 static int
 543 scc_getc(void)
 544 {
 545         volatile cbd_t          *rbdf;
 546         volatile unsigned char  *buf;
 547         volatile scc_uart_t     *up;
 548         volatile immap_t        *im = (immap_t *)CONFIG_SYS_IMMR;
 549         volatile cpm8xx_t       *cpmp = &(im->im_cpm);
 550         unsigned char           c;
 551
 552         up = (scc_uart_t *)&cpmp->cp_dparam[PROFF_SCC];
 553
 554         rbdf = (cbd_t *)&cpmp->cp_dpmem[up->scc_genscc.scc_rbase];
 555
 556         /* Wait for character to show up. */
 557         buf = (unsigned char *)rbdf->cbd_bufaddr;
 558
 559         while (rbdf->cbd_sc & BD_SC_EMPTY)
 560                 WATCHDOG_RESET ();
 561
 562         c = *buf;
 563         rbdf->cbd_sc |= BD_SC_EMPTY;
 564
 565         return(c);
 566 }
 567
 568 static int
 569 scc_tstc(void)
 570 {
 571         volatile cbd_t          *rbdf;
 572         volatile scc_uart_t     *up;
 573         volatile immap_t        *im = (immap_t *)CONFIG_SYS_IMMR;
 574         volatile cpm8xx_t       *cpmp = &(im->im_cpm);
 575
 576         up = (scc_uart_t *)&cpmp->cp_dparam[PROFF_SCC];
 577
 578         rbdf = (cbd_t *)&cpmp->cp_dpmem[up->scc_genscc.scc_rbase];
 579
 580         return(!(rbdf->cbd_sc & BD_SC_EMPTY));
 581 }
 582
 583 struct serial_device serial_scc_device =
 584 {
 585         .name   = "serial_scc",
 586         .start  = scc_init,
 587         .stop   = NULL,
 588         .setbrg = scc_setbrg,
 589         .getc   = scc_getc,
 590         .tstc   = scc_tstc,
 591         .putc   = scc_putc,
 592         .puts   = scc_puts,
 593 };
 594
 595 #endif  /* CONFIG_8xx_CONS_SCCx */
 596
 597 __weak struct serial_device *default_serial_console(void)
 598 {
 599 #if defined(CONFIG_8xx_CONS_SMC1) || defined(CONFIG_8xx_CONS_SMC2)
 600         return &serial_smc_device;
 601 #else
 602         return &serial_scc_device;
 603 #endif
 604 }
 605
 606 void mpc8xx_serial_initialize(void)
 607 {
 608 #if defined(CONFIG_8xx_CONS_SMC1) || defined(CONFIG_8xx_CONS_SMC2)
 609         serial_register(&serial_smc_device);
 610 #endif
 611 #if     defined(CONFIG_8xx_CONS_SCC1) || defined(CONFIG_8xx_CONS_SCC2) || \
 612         defined(CONFIG_8xx_CONS_SCC3) || defined(CONFIG_8xx_CONS_SCC4)
 613         serial_register(&serial_scc_device);
 614 #endif
 615 }
 616
 617 #if defined(CONFIG_CMD_KGDB)
 618
 619 void
 620 kgdb_serial_init(void)
 621 {
 622         int i = -1;
 623
 624         if (strcmp(default_serial_console()->name, "serial_smc") == 0)
 625         {
 626 #if defined(CONFIG_8xx_CONS_SMC1)
 627                 i = 1;
 628 #elif defined(CONFIG_8xx_CONS_SMC2)
 629                 i = 2;
 630 #endif
 631         }
 632         else if (strcmp(default_serial_console()->name, "serial_scc") == 0)
 633         {
 634 #if defined(CONFIG_8xx_CONS_SCC1)
 635                 i = 1;
 636 #elif defined(CONFIG_8xx_CONS_SCC2)
 637                 i = 2;
 638 #elif defined(CONFIG_8xx_CONS_SCC3)
 639                 i = 3;
 640 #elif defined(CONFIG_8xx_CONS_SCC4)
 641                 i = 4;
 642 #endif
 643         }
 644
 645         if (i >= 0)
 646         {
 647                 serial_printf("[on %s%d] ", default_serial_console()->name, i);
 648         }
 649 }
 650
 651 void
 652 putDebugChar (int c)
 653 {
 654         serial_putc (c);
 655 }
 656
 657 void
 658 putDebugStr (const char *str)
 659 {
 660         serial_puts (str);
 661 }
 662
 663 int
 664 getDebugChar (void)
 665 {
 666         return serial_getc();
 667 }
 668
 669 void
 670 kgdb_interruptible (int yes)
 671 {
 672         return;
 673 }
 674 #endif
 675
 676 #endif  /* CONFIG_8xx_CONS_NONE */