arch/powerpc/cpu/mpc8xx/speed.c

   1 /*
   2  * (C) Copyright 2000-2004
   3  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0+
   6  */
   7
   8 #include <common.h>
   9 #include <mpc8xx.h>
  10 #include <asm/processor.h>
  11
  12 DECLARE_GLOBAL_DATA_PTR;
  13
  14 void get_brgclk(uint sccr)
  15 {
  16         uint divider = 0;
  17
  18         switch((sccr&SCCR_DFBRG11)>>11){
  19                 case 0:
  20                         divider = 1;
  21                         break;
  22                 case 1:
  23                         divider = 4;
  24                         break;
  25                 case 2:
  26                         divider = 16;
  27                         break;
  28                 case 3:
  29                         divider = 64;
  30                         break;
  31         }
  32         gd->arch.brg_clk = gd->cpu_clk/divider;
  33 }
  34
  35 /*
  36  * get_clocks() fills in gd->cpu_clock depending on CONFIG_8xx_GCLK_FREQ
  37  */
  38 int get_clocks (void)
  39 {
  40         uint immr = get_immr (0);       /* Return full IMMR contents */
  41         volatile immap_t *immap = (immap_t *) (immr & 0xFFFF0000);
  42         uint sccr = immap->im_clkrst.car_sccr;
  43         /*
  44          * If for some reason measuring the gclk frequency won't
  45          * work, we return the hardwired value.
  46          * (For example, the cogent CMA286-60 CPU module has no
  47          * separate oscillator for PITRTCLK)
  48          */
  49         gd->cpu_clk = CONFIG_8xx_GCLK_FREQ;
  50
  51         if ((sccr & SCCR_EBDF11) == 0) {
  52                 /* No Bus Divider active */
  53                 gd->bus_clk = gd->cpu_clk;
  54         } else {
  55                 /* The MPC8xx has only one BDF: half clock speed */
  56                 gd->bus_clk = gd->cpu_clk / 2;
  57         }
  58
  59         get_brgclk(sccr);
  60
  61         return (0);
  62 }