2 * Copyright 2011 Freescale Semiconductor, Inc.
4 * SPDX-License-Identifier: GPL-2.0+
9 #include <asm/fsl_law.h>
10 #include <asm/fsl_serdes.h>
11 #include <asm/fsl_srio.h>
12 #include <linux/errno.h>
14 #ifdef CONFIG_SRIO_PCIE_BOOT_MASTER
15 #define SRIO_PORT_ACCEPT_ALL 0x10000001
16 #define SRIO_IB_ATMU_AR 0x80f55000
17 #define SRIO_OB_ATMU_AR_MAINT 0x80077000
18 #define SRIO_OB_ATMU_AR_RW 0x80045000
19 #define SRIO_LCSBA1CSR_OFFSET 0x5c
20 #define SRIO_MAINT_WIN_SIZE 0x1000000 /* 16M */
21 #define SRIO_RW_WIN_SIZE 0x100000 /* 1M */
22 #define SRIO_LCSBA1CSR 0x60000000
25 #if defined(CONFIG_FSL_CORENET)
26 #ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
27 #define _DEVDISR_SRIO1 FSL_CORENET_DEVDISR3_SRIO1
28 #define _DEVDISR_SRIO2 FSL_CORENET_DEVDISR3_SRIO2
30 #define _DEVDISR_SRIO1 FSL_CORENET_DEVDISR_SRIO1
31 #define _DEVDISR_SRIO2 FSL_CORENET_DEVDISR_SRIO2
33 #define _DEVDISR_RMU FSL_CORENET_DEVDISR_RMU
34 #define CONFIG_SYS_MPC8xxx_GUTS_ADDR CONFIG_SYS_MPC85xx_GUTS_ADDR
35 #elif defined(CONFIG_MPC85xx)
36 #define _DEVDISR_SRIO1 MPC85xx_DEVDISR_SRIO
37 #define _DEVDISR_SRIO2 MPC85xx_DEVDISR_SRIO
38 #define _DEVDISR_RMU MPC85xx_DEVDISR_RMSG
39 #define CONFIG_SYS_MPC8xxx_GUTS_ADDR CONFIG_SYS_MPC85xx_GUTS_ADDR
40 #elif defined(CONFIG_MPC86xx)
41 #define _DEVDISR_SRIO1 MPC86xx_DEVDISR_SRIO
42 #define _DEVDISR_SRIO2 MPC86xx_DEVDISR_SRIO
43 #define _DEVDISR_RMU MPC86xx_DEVDISR_RMSG
44 #define CONFIG_SYS_MPC8xxx_GUTS_ADDR \
45 (&((immap_t *)CONFIG_SYS_IMMR)->im_gur)
47 #error "No defines for DEVDISR_SRIO"
50 #ifdef CONFIG_SYS_FSL_ERRATUM_SRIO_A004034
54 * Description: During port initialization, the SRIO port performs
55 * lane synchronization (detecting valid symbols on a lane) and
56 * lane alignment (coordinating multiple lanes to receive valid data
57 * across lanes). Internal errors in lane synchronization and lane
58 * alignment may cause failure to achieve link initialization at
59 * the configured port width.
60 * An SRIO port configured as a 4x port may see one of these scenarios:
61 * 1. One or more lanes fails to achieve lane synchronization. Depending
62 * on which lanes fail, this may result in downtraining from 4x to 1x
63 * on lane 0, 4x to 1x on lane R (redundant lane).
64 * 2. The link may fail to achieve lane alignment as a 4x, even though
65 * all 4 lanes achieve lane synchronization, and downtrain to a 1x.
66 * An SRIO port configured as a 1x port may fail to complete port
67 * initialization (PnESCSR[PU] never deasserts) because of scenario 1.
68 * Impact: SRIO port may downtrain to 1x, or may fail to complete
69 * link initialization. Once a port completes link initialization
70 * successfully, it will operate normally.
72 static int srio_erratum_a004034(u8 port
)
74 serdes_corenet_t
*srds_regs
;
79 unsigned long long end_tick
;
80 struct ccsr_rio
*srio_regs
= (void *)CONFIG_SYS_FSL_SRIO_ADDR
;
82 srds_regs
= (void *)(CONFIG_SYS_FSL_CORENET_SERDES_ADDR
);
83 conf_lane
= (in_be32((void *)&srds_regs
->srdspccr0
)
84 >> (12 - port
* 4)) & 0x3;
85 init_lane
= (in_be32((void *)&srio_regs
->lp_serial
86 .port
[port
].pccsr
) >> 27) & 0x7;
89 * Start a counter set to ~2 ms after the SERDES reset is
90 * complete (SERDES SRDSBnRSTCTL[RST_DONE]=1 for n
91 * corresponding to the SERDES bank/PLL for the SRIO port).
93 if (in_be32((void *)&srds_regs
->bank
[0].rstctl
)
94 & SRDS_RSTCTL_RSTDONE
) {
96 * Poll the port uninitialized status (SRIO PnESCSR[PO]) until
97 * PO=1 or the counter expires. If the counter expires, the
98 * port has failed initialization: go to recover steps. If PO=1
99 * and the desired port width is 1x, go to normal steps. If
100 * PO = 1 and the desired port width is 4x, go to recover steps.
102 end_tick
= usec2ticks(2000) + get_ticks();
104 if (in_be32((void *)&srio_regs
->lp_serial
105 .port
[port
].pescsr
) & 0x2) {
106 if (conf_lane
== 0x1)
109 if (init_lane
== 0x2)
115 } while (end_tick
> get_ticks());
117 /* recover at most 3 times */
118 for (i
= 0; i
< 3; i
++) {
119 /* Set SRIO PnCCSR[PD]=1 */
120 setbits_be32((void *)&srio_regs
->lp_serial
124 * Set SRIO PnPCR[OBDEN] on the host to
125 * enable the discarding of any pending packets.
127 setbits_be32((void *)&srio_regs
->impl
.port
[port
].pcr
,
131 /* Run sync command */
135 first
= serdes_get_first_lane(SRIO2
);
137 first
= serdes_get_first_lane(SRIO1
);
138 if (unlikely(first
< 0))
140 if (conf_lane
== 0x1)
145 * Set SERDES BnGCRm0[RRST]=0 for each SRIO
148 for (idx
= first
; idx
<= last
; idx
++)
149 clrbits_be32(&srds_regs
->lane
[idx
].gcr0
,
152 * Read SERDES BnGCRm0 for each SRIO
155 for (idx
= first
; idx
<= last
; idx
++)
156 in_be32(&srds_regs
->lane
[idx
].gcr0
);
157 /* Run sync command */
162 * Set SERDES BnGCRm0[RRST]=1 for each SRIO
165 for (idx
= first
; idx
<= last
; idx
++)
166 setbits_be32(&srds_regs
->lane
[idx
].gcr0
,
169 * Read SERDES BnGCRm0 for each SRIO
172 for (idx
= first
; idx
<= last
; idx
++)
173 in_be32(&srds_regs
->lane
[idx
].gcr0
);
174 /* Run sync command */
179 /* Write 1 to clear all bits in SRIO PnSLCSR */
180 out_be32((void *)&srio_regs
->impl
.port
[port
].slcsr
,
182 /* Clear SRIO PnPCR[OBDEN] on the host */
183 clrbits_be32((void *)&srio_regs
->impl
.port
[port
].pcr
,
185 /* Set SRIO PnCCSR[PD]=0 */
186 clrbits_be32((void *)&srio_regs
->lp_serial
191 /* Poll the state of the port again */
193 (in_be32((void *)&srio_regs
->lp_serial
194 .port
[port
].pccsr
) >> 27) & 0x7;
195 if (in_be32((void *)&srio_regs
->lp_serial
196 .port
[port
].pescsr
) & 0x2) {
197 if (conf_lane
== 0x1)
200 if (init_lane
== 0x2)
211 /* Poll PnESCSR[OES] on the host until it is clear */
212 end_tick
= usec2ticks(1000000) + get_ticks();
214 if (!(in_be32((void *)&srio_regs
->lp_serial
.port
[port
].pescsr
)
216 out_be32(((void *)&srio_regs
->lp_serial
217 .port
[port
].pescsr
), 0xffffffff);
218 out_be32(((void *)&srio_regs
->phys_err
219 .port
[port
].edcsr
), 0);
220 out_be32(((void *)&srio_regs
->logical_err
.ltledcsr
), 0);
223 } while (end_tick
> get_ticks());
231 ccsr_gur_t
*gur
= (void *)CONFIG_SYS_MPC8xxx_GUTS_ADDR
;
232 int srio1_used
= 0, srio2_used
= 0;
235 #ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
236 devdisr
= &gur
->devdisr3
;
238 devdisr
= &gur
->devdisr
;
240 if (is_serdes_configured(SRIO1
)) {
241 set_next_law(CONFIG_SYS_SRIO1_MEM_PHYS
,
242 law_size_bits(CONFIG_SYS_SRIO1_MEM_SIZE
),
245 #ifdef CONFIG_SYS_FSL_ERRATUM_SRIO_A004034
246 if (srio_erratum_a004034(0) < 0)
247 printf("SRIO1: enabled but port error\n");
250 printf("SRIO1: enabled\n");
252 printf("SRIO1: disabled\n");
256 if (is_serdes_configured(SRIO2
)) {
257 set_next_law(CONFIG_SYS_SRIO2_MEM_PHYS
,
258 law_size_bits(CONFIG_SYS_SRIO2_MEM_SIZE
),
261 #ifdef CONFIG_SYS_FSL_ERRATUM_SRIO_A004034
262 if (srio_erratum_a004034(1) < 0)
263 printf("SRIO2: enabled but port error\n");
266 printf("SRIO2: enabled\n");
269 printf("SRIO2: disabled\n");
273 #ifdef CONFIG_FSL_CORENET
274 /* On FSL_CORENET devices we can disable individual ports */
276 setbits_be32(devdisr
, _DEVDISR_SRIO1
);
278 setbits_be32(devdisr
, _DEVDISR_SRIO2
);
281 /* neither port is used - disable everything */
282 if (!srio1_used
&& !srio2_used
) {
283 setbits_be32(devdisr
, _DEVDISR_SRIO1
);
284 setbits_be32(devdisr
, _DEVDISR_SRIO2
);
285 setbits_be32(devdisr
, _DEVDISR_RMU
);
289 #ifdef CONFIG_SRIO_PCIE_BOOT_MASTER
290 void srio_boot_master(int port
)
292 struct ccsr_rio
*srio
= (void *)CONFIG_SYS_FSL_SRIO_ADDR
;
294 /* set port accept-all */
295 out_be32((void *)&srio
->impl
.port
[port
- 1].ptaacr
,
296 SRIO_PORT_ACCEPT_ALL
);
298 debug("SRIOBOOT - MASTER: Master port [ %d ] for srio boot.\n", port
);
299 /* configure inbound window for slave's u-boot image */
300 debug("SRIOBOOT - MASTER: Inbound window for slave's image; "
301 "Local = 0x%llx, Srio = 0x%llx, Size = 0x%x\n",
302 (u64
)CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS
,
303 (u64
)CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1
,
304 CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE
);
305 out_be32((void *)&srio
->atmu
.port
[port
- 1].inbw
[0].riwtar
,
306 CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS
>> 12);
307 out_be32((void *)&srio
->atmu
.port
[port
- 1].inbw
[0].riwbar
,
308 CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1
>> 12);
309 out_be32((void *)&srio
->atmu
.port
[port
- 1].inbw
[0].riwar
,
311 | atmu_size_mask(CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE
));
313 /* configure inbound window for slave's u-boot image */
314 debug("SRIOBOOT - MASTER: Inbound window for slave's image; "
315 "Local = 0x%llx, Srio = 0x%llx, Size = 0x%x\n",
316 (u64
)CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS
,
317 (u64
)CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2
,
318 CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE
);
319 out_be32((void *)&srio
->atmu
.port
[port
- 1].inbw
[1].riwtar
,
320 CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS
>> 12);
321 out_be32((void *)&srio
->atmu
.port
[port
- 1].inbw
[1].riwbar
,
322 CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2
>> 12);
323 out_be32((void *)&srio
->atmu
.port
[port
- 1].inbw
[1].riwar
,
325 | atmu_size_mask(CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE
));
327 /* configure inbound window for slave's ucode and ENV */
328 debug("SRIOBOOT - MASTER: Inbound window for slave's ucode and ENV; "
329 "Local = 0x%llx, Srio = 0x%llx, Size = 0x%x\n",
330 (u64
)CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS
,
331 (u64
)CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS
,
332 CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE
);
333 out_be32((void *)&srio
->atmu
.port
[port
- 1].inbw
[2].riwtar
,
334 CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS
>> 12);
335 out_be32((void *)&srio
->atmu
.port
[port
- 1].inbw
[2].riwbar
,
336 CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS
>> 12);
337 out_be32((void *)&srio
->atmu
.port
[port
- 1].inbw
[2].riwar
,
339 | atmu_size_mask(CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE
));
342 void srio_boot_master_release_slave(int port
)
344 struct ccsr_rio
*srio
= (void *)CONFIG_SYS_FSL_SRIO_ADDR
;
346 debug("SRIOBOOT - MASTER: "
347 "Check the port status and release slave core ...\n");
349 escsr
= in_be32((void *)&srio
->lp_serial
.port
[port
- 1].pescsr
);
351 if (escsr
& 0x10100) {
352 debug("SRIOBOOT - MASTER: Port [ %d ] is error.\n",
355 debug("SRIOBOOT - MASTER: "
356 "Port [ %d ] is ready, now release slave's core ...\n",
359 * configure outbound window
360 * with maintenance attribute to set slave's LCSBA1CSR
362 out_be32((void *)&srio
->atmu
.port
[port
- 1]
363 .outbw
[1].rowtar
, 0);
364 out_be32((void *)&srio
->atmu
.port
[port
- 1]
365 .outbw
[1].rowtear
, 0);
367 out_be32((void *)&srio
->atmu
.port
[port
- 1]
369 CONFIG_SYS_SRIO2_MEM_PHYS
>> 12);
371 out_be32((void *)&srio
->atmu
.port
[port
- 1]
373 CONFIG_SYS_SRIO1_MEM_PHYS
>> 12);
374 out_be32((void *)&srio
->atmu
.port
[port
- 1]
376 SRIO_OB_ATMU_AR_MAINT
377 | atmu_size_mask(SRIO_MAINT_WIN_SIZE
));
380 * configure outbound window
381 * with R/W attribute to set slave's BRR
383 out_be32((void *)&srio
->atmu
.port
[port
- 1]
385 SRIO_LCSBA1CSR
>> 9);
386 out_be32((void *)&srio
->atmu
.port
[port
- 1]
387 .outbw
[2].rowtear
, 0);
389 out_be32((void *)&srio
->atmu
.port
[port
- 1]
391 (CONFIG_SYS_SRIO2_MEM_PHYS
392 + SRIO_MAINT_WIN_SIZE
) >> 12);
394 out_be32((void *)&srio
->atmu
.port
[port
- 1]
396 (CONFIG_SYS_SRIO1_MEM_PHYS
397 + SRIO_MAINT_WIN_SIZE
) >> 12);
398 out_be32((void *)&srio
->atmu
.port
[port
- 1]
401 | atmu_size_mask(SRIO_RW_WIN_SIZE
));
404 * Set the LCSBA1CSR register in slave
405 * by the maint-outbound window
408 out_be32((void *)CONFIG_SYS_SRIO2_MEM_VIRT
409 + SRIO_LCSBA1CSR_OFFSET
,
411 while (in_be32((void *)CONFIG_SYS_SRIO2_MEM_VIRT
412 + SRIO_LCSBA1CSR_OFFSET
)
416 * And then set the BRR register
417 * to release slave core
419 out_be32((void *)CONFIG_SYS_SRIO2_MEM_VIRT
420 + SRIO_MAINT_WIN_SIZE
421 + CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET
,
422 CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK
);
424 out_be32((void *)CONFIG_SYS_SRIO1_MEM_VIRT
425 + SRIO_LCSBA1CSR_OFFSET
,
427 while (in_be32((void *)CONFIG_SYS_SRIO1_MEM_VIRT
428 + SRIO_LCSBA1CSR_OFFSET
)
432 * And then set the BRR register
433 * to release slave core
435 out_be32((void *)CONFIG_SYS_SRIO1_MEM_VIRT
436 + SRIO_MAINT_WIN_SIZE
437 + CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET
,
438 CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK
);
440 debug("SRIOBOOT - MASTER: "
441 "Release slave successfully! Now the slave should start up!\n");
444 debug("SRIOBOOT - MASTER: Port [ %d ] is not ready.\n", port
);