arch/powerpc/cpu/ppc4xx/40x_spd_sdram.c

   1 /*
   2  * arch/powerpc/cpu/ppc4xx/40x_spd_sdram.c
   3  * This SPD SDRAM detection code supports IBM/AMCC PPC44x cpu with a
   4  * SDRAM controller. Those are all current 405 PPC's.
   5  *
   6  * (C) Copyright 2001
   7  * Bill Hunter, Wave 7 Optics, williamhunter@attbi.com
   8  *
   9  * Based on code by:
  10  *
  11  * Kenneth Johansson ,Ericsson AB.
  12  * kenneth.johansson@etx.ericsson.se
  13  *
  14  * hacked up by bill hunter. fixed so we could run before
  15  * serial_init and console_init. previous version avoided this by
  16  * running out of cache memory during serial/console init, then running
  17  * this code later.
  18  *
  19  * (C) Copyright 2002
  20  * Jun Gu, Artesyn Technology, jung@artesyncp.com
  21  * Support for AMCC 440 based on OpenBIOS draminit.c from IBM.
  22  *
  23  * (C) Copyright 2005
  24  * Stefan Roese, DENX Software Engineering, sr@denx.de.
  25  *
  26  * SPDX-License-Identifier:     GPL-2.0+
  27  */
  28
  29 #include <common.h>
  30 #include <asm/processor.h>
  31 #include <i2c.h>
  32 #include <asm/ppc4xx.h>
  33
  34 #if defined(CONFIG_SPD_EEPROM) && !defined(CONFIG_440)
  35
  36 /*
  37  * Set default values
  38  */
  39 #define ONE_BILLION     1000000000
  40
  41 #define  SDRAM0_CFG_DCE         0x80000000
  42 #define  SDRAM0_CFG_SRE         0x40000000
  43 #define  SDRAM0_CFG_PME         0x20000000
  44 #define  SDRAM0_CFG_MEMCHK      0x10000000
  45 #define  SDRAM0_CFG_REGEN       0x08000000
  46 #define  SDRAM0_CFG_ECCDD       0x00400000
  47 #define  SDRAM0_CFG_EMDULR      0x00200000
  48 #define  SDRAM0_CFG_DRW_SHIFT   (31-6)
  49 #define  SDRAM0_CFG_BRPF_SHIFT  (31-8)
  50
  51 #define  SDRAM0_TR_CASL_SHIFT   (31-8)
  52 #define  SDRAM0_TR_PTA_SHIFT    (31-13)
  53 #define  SDRAM0_TR_CTP_SHIFT    (31-15)
  54 #define  SDRAM0_TR_LDF_SHIFT    (31-17)
  55 #define  SDRAM0_TR_RFTA_SHIFT   (31-29)
  56 #define  SDRAM0_TR_RCD_SHIFT    (31-31)
  57
  58 #define  SDRAM0_RTR_SHIFT       (31-15)
  59 #define  SDRAM0_ECCCFG_SHIFT    (31-11)
  60
  61 /* SDRAM0_CFG enable macro  */
  62 #define SDRAM0_CFG_BRPF(x) ( ( x & 0x3)<< SDRAM0_CFG_BRPF_SHIFT )
  63
  64 #define SDRAM0_BXCR_SZ_MASK     0x000e0000
  65 #define SDRAM0_BXCR_AM_MASK     0x0000e000
  66
  67 #define SDRAM0_BXCR_SZ_SHIFT    (31-14)
  68 #define SDRAM0_BXCR_AM_SHIFT    (31-18)
  69
  70 #define SDRAM0_BXCR_SZ(x)       ( (( x << SDRAM0_BXCR_SZ_SHIFT) & SDRAM0_BXCR_SZ_MASK) )
  71 #define SDRAM0_BXCR_AM(x)       ( (( x << SDRAM0_BXCR_AM_SHIFT) & SDRAM0_BXCR_AM_MASK) )
  72
  73 #ifdef CONFIG_SPDDRAM_SILENT
  74 # define SPD_ERR(x) do { return 0; } while (0)
  75 #else
  76 # define SPD_ERR(x) do { printf(x); return(0); } while (0)
  77 #endif
  78
  79 #define sdram_HZ_to_ns(hertz) (1000000000/(hertz))
  80
  81 /* function prototypes */
  82 int spd_read(uint addr);
  83
  84
  85 /*
  86  * This function is reading data from the DIMM module EEPROM over the SPD bus
  87  * and uses that to program the sdram controller.
  88  *
  89  * This works on boards that has the same schematics that the AMCC walnut has.
  90  *
  91  * Input: null for default I2C spd functions or a pointer to a custom function
  92  * returning spd_data.
  93  */
  94
  95 long int spd_sdram(int(read_spd)(uint addr))
  96 {
  97         int tmp,row,col;
  98         int total_size,bank_size,bank_code;
  99         int mode;
 100         int bank_cnt;
 101
 102         int sdram0_pmit=0x07c00000;
 103         int sdram0_b0cr;
 104         int sdram0_b1cr = 0;
 105 #ifndef CONFIG_405EP /* not on PPC405EP */
 106         int sdram0_b2cr = 0;
 107         int sdram0_b3cr = 0;
 108         int sdram0_besr0 = -1;
 109         int sdram0_besr1 = -1;
 110         int sdram0_eccesr = -1;
 111         int sdram0_ecccfg;
 112         int ecc_on;
 113 #endif
 114
 115         int sdram0_rtr=0;
 116         int sdram0_tr=0;
 117
 118         int sdram0_cfg=0;
 119
 120         int t_rp;
 121         int t_rcd;
 122         int t_ras;
 123         int t_rc;
 124         int min_cas;
 125
 126         PPC4xx_SYS_INFO sys_info;
 127         unsigned long bus_period_x_10;
 128
 129         /*
 130          * get the board info
 131          */
 132         get_sys_info(&sys_info);
 133         bus_period_x_10 = ONE_BILLION / (sys_info.freqPLB / 10);
 134
 135         if (read_spd == 0){
 136                 read_spd=spd_read;
 137                 /*
 138                  * Make sure I2C controller is initialized
 139                  * before continuing.
 140                  */
 141                 i2c_set_bus_num(CONFIG_SYS_SPD_BUS_NUM);
 142         }
 143
 144         /* Make shure we are using SDRAM */
 145         if (read_spd(2) != 0x04) {
 146                 SPD_ERR("SDRAM - non SDRAM memory module found\n");
 147         }
 148
 149         /* ------------------------------------------------------------------
 150          * configure memory timing register
 151          *
 152          * data from DIMM:
 153          * 27   IN Row Precharge Time ( t RP)
 154          * 29   MIN RAS to CAS Delay ( t RCD)
 155          * 127   Component and Clock Detail ,clk0-clk3, junction temp, CAS
 156          * -------------------------------------------------------------------*/
 157
 158         /*
 159          * first figure out which cas latency mode to use
 160          * use the min supported mode
 161          */
 162
 163         tmp = read_spd(127) & 0x6;
 164         if (tmp == 0x02) {              /* only cas = 2 supported */
 165                 min_cas = 2;
 166 /*              t_ck = read_spd(9); */
 167 /*              t_ac = read_spd(10); */
 168         } else if (tmp == 0x04) {       /* only cas = 3 supported */
 169                 min_cas = 3;
 170 /*              t_ck = read_spd(9); */
 171 /*              t_ac = read_spd(10); */
 172         } else if (tmp == 0x06) {       /* 2,3 supported, so use 2 */
 173                 min_cas = 2;
 174 /*              t_ck = read_spd(23); */
 175 /*              t_ac = read_spd(24); */
 176         } else {
 177                 SPD_ERR("SDRAM - unsupported CAS latency \n");
 178         }
 179
 180         /* get some timing values, t_rp,t_rcd,t_ras,t_rc
 181          */
 182         t_rp = read_spd(27);
 183         t_rcd = read_spd(29);
 184         t_ras = read_spd(30);
 185         t_rc = t_ras + t_rp;
 186
 187         /* The following timing calcs subtract 1 before deviding.
 188          * this has effect of using ceiling instead of floor rounding,
 189          * and also subtracting 1 to convert number to reg value
 190          */
 191         /* set up CASL */
 192         sdram0_tr = (min_cas - 1) << SDRAM0_TR_CASL_SHIFT;
 193         /* set up PTA */
 194         sdram0_tr |= ((((t_rp - 1) * 10)/bus_period_x_10) & 0x3) << SDRAM0_TR_PTA_SHIFT;
 195         /* set up CTP */
 196         tmp = (((t_rc - t_rcd - t_rp -1) * 10) / bus_period_x_10) & 0x3;
 197         if (tmp < 1)
 198                 tmp = 1;
 199         sdram0_tr |= tmp << SDRAM0_TR_CTP_SHIFT;
 200         /* set LDF      = 2 cycles, reg value = 1 */
 201         sdram0_tr |= 1 << SDRAM0_TR_LDF_SHIFT;
 202         /* set RFTA = t_rfc/bus_period, use t_rfc = t_rc */
 203         tmp = (((t_rc - 1) * 10) / bus_period_x_10) - 3;
 204         if (tmp < 0)
 205                 tmp = 0;
 206         if (tmp > 6)
 207                 tmp = 6;
 208         sdram0_tr |= tmp << SDRAM0_TR_RFTA_SHIFT;
 209         /* set RCD = t_rcd/bus_period*/
 210         sdram0_tr |= ((((t_rcd - 1) * 10) / bus_period_x_10) &0x3) << SDRAM0_TR_RCD_SHIFT ;
 211
 212
 213         /*------------------------------------------------------------------
 214          * configure RTR register
 215          * -------------------------------------------------------------------*/
 216         row = read_spd(3);
 217         col = read_spd(4);
 218         tmp = read_spd(12) & 0x7f ; /* refresh type less self refresh bit */
 219         switch (tmp) {
 220         case 0x00:
 221                 tmp = 15625;
 222                 break;
 223         case 0x01:
 224                 tmp = 15625 / 4;
 225                 break;
 226         case 0x02:
 227                 tmp = 15625 / 2;
 228                 break;
 229         case 0x03:
 230                 tmp = 15625 * 2;
 231                 break;
 232         case 0x04:
 233                 tmp = 15625 * 4;
 234                 break;
 235         case 0x05:
 236                 tmp = 15625 * 8;
 237                 break;
 238         default:
 239                 SPD_ERR("SDRAM - Bad refresh period \n");
 240         }
 241         /* convert from nsec to bus cycles */
 242         tmp = (tmp * 10) / bus_period_x_10;
 243         sdram0_rtr = (tmp & 0x3ff8) <<  SDRAM0_RTR_SHIFT;
 244
 245         /*------------------------------------------------------------------
 246          * determine the number of banks used
 247          * -------------------------------------------------------------------*/
 248         /* byte 7:6 is module data width */
 249         if (read_spd(7) != 0)
 250                 SPD_ERR("SDRAM - unsupported module width\n");
 251         tmp = read_spd(6);
 252         if (tmp < 32)
 253                 SPD_ERR("SDRAM - unsupported module width\n");
 254         else if (tmp < 64)
 255                 bank_cnt = 1;           /* one bank per sdram side */
 256         else if (tmp < 73)
 257                 bank_cnt = 2;   /* need two banks per side */
 258         else if (tmp < 161)
 259                 bank_cnt = 4;   /* need four banks per side */
 260         else
 261                 SPD_ERR("SDRAM - unsupported module width\n");
 262
 263         /* byte 5 is the module row count (refered to as dimm "sides") */
 264         tmp = read_spd(5);
 265         if (tmp == 1)
 266                 ;
 267         else if (tmp==2)
 268                 bank_cnt *= 2;
 269         else if (tmp==4)
 270                 bank_cnt *= 4;
 271         else
 272                 bank_cnt = 8;           /* 8 is an error code */
 273
 274         if (bank_cnt > 4)       /* we only have 4 banks to work with */
 275                 SPD_ERR("SDRAM - unsupported module rows for this width\n");
 276
 277 #ifndef CONFIG_405EP /* not on PPC405EP */
 278         /* now check for ECC ability of module. We only support ECC
 279          *   on 32 bit wide devices with 8 bit ECC.
 280          */
 281         if ((read_spd(11)==2) && (read_spd(6)==40) && (read_spd(14)==8)) {
 282                 sdram0_ecccfg = 0xf << SDRAM0_ECCCFG_SHIFT;
 283                 ecc_on = 1;
 284         } else {
 285                 sdram0_ecccfg = 0;
 286                 ecc_on = 0;
 287         }
 288 #endif
 289
 290         /*------------------------------------------------------------------
 291          * calculate total size
 292          * -------------------------------------------------------------------*/
 293         /* calculate total size and do sanity check */
 294         tmp = read_spd(31);
 295         total_size = 1 << 22;   /* total_size = 4MB */
 296         /* now multiply 4M by the smallest device row density */
 297         /* note that we don't support asymetric rows */
 298         while (((tmp & 0x0001) == 0) && (tmp != 0)) {
 299                 total_size = total_size << 1;
 300                 tmp = tmp >> 1;
 301         }
 302         total_size *= read_spd(5);      /* mult by module rows (dimm sides) */
 303
 304         /*------------------------------------------------------------------
 305          * map  rows * cols * banks to a mode
 306          * -------------------------------------------------------------------*/
 307
 308         switch (row) {
 309         case 11:
 310                 switch (col) {
 311                 case 8:
 312                         mode=4; /* mode 5 */
 313                         break;
 314                 case 9:
 315                 case 10:
 316                         mode=0; /* mode 1 */
 317                         break;
 318                 default:
 319                         SPD_ERR("SDRAM - unsupported mode\n");
 320                 }
 321                 break;
 322         case 12:
 323                 switch (col) {
 324                 case 8:
 325                         mode=3; /* mode 4 */
 326                         break;
 327                 case 9:
 328                 case 10:
 329                         mode=1; /* mode 2 */
 330                         break;
 331                 default:
 332                         SPD_ERR("SDRAM - unsupported mode\n");
 333                 }
 334                 break;
 335         case 13:
 336                 switch (col) {
 337                 case 8:
 338                         mode=5; /* mode 6 */
 339                         break;
 340                 case 9:
 341                 case 10:
 342                         if (read_spd(17) == 2)
 343                                 mode = 6; /* mode 7 */
 344                         else
 345                                 mode = 2; /* mode 3 */
 346                         break;
 347                 case 11:
 348                         mode = 2; /* mode 3 */
 349                         break;
 350                 default:
 351                         SPD_ERR("SDRAM - unsupported mode\n");
 352                 }
 353                 break;
 354         default:
 355                 SPD_ERR("SDRAM - unsupported mode\n");
 356         }
 357
 358         /*------------------------------------------------------------------
 359          * using the calculated values, compute the bank
 360          * config register values.
 361          * -------------------------------------------------------------------*/
 362
 363         /* compute the size of each bank */
 364         bank_size = total_size / bank_cnt;
 365         /* convert bank size to bank size code for ppc4xx
 366            by takeing log2(bank_size) - 22 */
 367         tmp = bank_size;                /* start with tmp = bank_size */
 368         bank_code = 0;                  /* and bank_code = 0 */
 369         while (tmp > 1) {               /* this takes log2 of tmp */
 370                 bank_code++;            /* and stores result in bank_code */
 371                 tmp = tmp >> 1;
 372         }                               /* bank_code is now log2(bank_size) */
 373         bank_code -= 22;                /* subtract 22 to get the code */
 374
 375         tmp = SDRAM0_BXCR_SZ(bank_code) | SDRAM0_BXCR_AM(mode) | 1;
 376         sdram0_b0cr = (bank_size * 0) | tmp;
 377 #ifndef CONFIG_405EP /* not on PPC405EP */
 378         if (bank_cnt > 1)
 379                 sdram0_b2cr = (bank_size * 1) | tmp;
 380         if (bank_cnt > 2)
 381                 sdram0_b1cr = (bank_size * 2) | tmp;
 382         if (bank_cnt > 3)
 383                 sdram0_b3cr = (bank_size * 3) | tmp;
 384 #else
 385         /* PPC405EP chip only supports two SDRAM banks */
 386         if (bank_cnt > 1)
 387                 sdram0_b1cr = (bank_size * 1) | tmp;
 388         if (bank_cnt > 2)
 389                 total_size = 2 * bank_size;
 390 #endif
 391
 392         /*
 393          *   enable sdram controller DCE=1
 394          *  enable burst read prefetch to 32 bytes BRPF=2
 395          *  leave other functions off
 396          */
 397
 398         /*------------------------------------------------------------------
 399          * now that we've done our calculations, we are ready to
 400          * program all the registers.
 401          * -------------------------------------------------------------------*/
 402
 403         /* disable memcontroller so updates work */
 404         mtsdram(SDRAM0_CFG, 0);
 405
 406 #ifndef CONFIG_405EP /* not on PPC405EP */
 407         mtsdram(SDRAM0_BESR0, sdram0_besr0);
 408         mtsdram(SDRAM0_BESR1, sdram0_besr1);
 409         mtsdram(SDRAM0_ECCCFG, sdram0_ecccfg);
 410         mtsdram(SDRAM0_ECCESR, sdram0_eccesr);
 411 #endif
 412         mtsdram(SDRAM0_RTR, sdram0_rtr);
 413         mtsdram(SDRAM0_PMIT, sdram0_pmit);
 414         mtsdram(SDRAM0_B0CR, sdram0_b0cr);
 415         mtsdram(SDRAM0_B1CR, sdram0_b1cr);
 416 #ifndef CONFIG_405EP /* not on PPC405EP */
 417         mtsdram(SDRAM0_B2CR, sdram0_b2cr);
 418         mtsdram(SDRAM0_B3CR, sdram0_b3cr);
 419 #endif
 420         mtsdram(SDRAM0_TR, sdram0_tr);
 421
 422         /* SDRAM have a power on delay,  500 micro should do */
 423         udelay(500);
 424         sdram0_cfg = SDRAM0_CFG_DCE | SDRAM0_CFG_BRPF(1) | SDRAM0_CFG_ECCDD | SDRAM0_CFG_EMDULR;
 425 #ifndef CONFIG_405EP /* not on PPC405EP */
 426         if (ecc_on)
 427                 sdram0_cfg |= SDRAM0_CFG_MEMCHK;
 428 #endif
 429         mtsdram(SDRAM0_CFG, sdram0_cfg);
 430
 431         return (total_size);
 432 }
 433
 434 int spd_read(uint addr)
 435 {
 436         uchar data[2];
 437
 438         if (i2c_read(SPD_EEPROM_ADDRESS, addr, 1, data, 1) == 0)
 439                 return (int)data[0];
 440         else
 441                 return 0;
 442 }
 443
 444 #endif /* CONFIG_SPD_EEPROM */