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[people/ms/u-boot.git] / arch / powerpc / cpu / ppc4xx / 44x_spd_ddr.c
1 /*
2 * arch/powerpc/cpu/ppc4xx/44x_spd_ddr.c
3 * This SPD DDR detection code supports IBM/AMCC PPC44x cpu with a
4 * DDR controller. Those are 440GP/GX/EP/GR.
5 *
6 * (C) Copyright 2001
7 * Bill Hunter, Wave 7 Optics, williamhunter@attbi.com
8 *
9 * Based on code by:
10 *
11 * Kenneth Johansson ,Ericsson AB.
12 * kenneth.johansson@etx.ericsson.se
13 *
14 * hacked up by bill hunter. fixed so we could run before
15 * serial_init and console_init. previous version avoided this by
16 * running out of cache memory during serial/console init, then running
17 * this code later.
18 *
19 * (C) Copyright 2002
20 * Jun Gu, Artesyn Technology, jung@artesyncp.com
21 * Support for AMCC 440 based on OpenBIOS draminit.c from IBM.
22 *
23 * (C) Copyright 2005-2007
24 * Stefan Roese, DENX Software Engineering, sr@denx.de.
25 *
26 * SPDX-License-Identifier: GPL-2.0+
27 */
28
29 /* define DEBUG for debugging output (obviously ;-)) */
30 #if 0
31 #define DEBUG
32 #endif
33
34 #include <common.h>
35 #include <asm/processor.h>
36 #include <i2c.h>
37 #include <asm/ppc4xx.h>
38 #include <asm/mmu.h>
39
40 #include "ecc.h"
41
42 #if defined(CONFIG_SPD_EEPROM) && \
43 (defined(CONFIG_440GP) || defined(CONFIG_440GX) || \
44 defined(CONFIG_440EP) || defined(CONFIG_440GR))
45
46 /*
47 * Set default values
48 */
49 #ifndef CONFIG_SYS_I2C_SPEED
50 #define CONFIG_SYS_I2C_SPEED 50000
51 #endif
52
53 #define ONE_BILLION 1000000000
54
55 /*
56 * Board-specific Platform code can reimplement spd_ddr_init_hang () if needed
57 */
58 void __spd_ddr_init_hang (void)
59 {
60 hang ();
61 }
62 void spd_ddr_init_hang (void) __attribute__((weak, alias("__spd_ddr_init_hang")));
63
64 /*-----------------------------------------------------------------------------+
65 | General Definition
66 +-----------------------------------------------------------------------------*/
67 #define DEFAULT_SPD_ADDR1 0x53
68 #define DEFAULT_SPD_ADDR2 0x52
69 #define MAXBANKS 4 /* at most 4 dimm banks */
70 #define MAX_SPD_BYTES 256
71 #define NUMHALFCYCLES 4
72 #define NUMMEMTESTS 8
73 #define NUMMEMWORDS 8
74 #define MAXBXCR 4
75
76 /*
77 * This DDR2 setup code can dynamically setup the TLB entries for the DDR2 memory
78 * region. Right now the cache should still be disabled in U-Boot because of the
79 * EMAC driver, that need it's buffer descriptor to be located in non cached
80 * memory.
81 *
82 * If at some time this restriction doesn't apply anymore, just define
83 * CONFIG_4xx_DCACHE in the board config file and this code should setup
84 * everything correctly.
85 */
86 #ifdef CONFIG_4xx_DCACHE
87 #define MY_TLB_WORD2_I_ENABLE 0 /* enable caching on SDRAM */
88 #else
89 #define MY_TLB_WORD2_I_ENABLE TLB_WORD2_I_ENABLE /* disable caching on SDRAM */
90 #endif
91
92 /* bank_parms is used to sort the bank sizes by descending order */
93 struct bank_param {
94 unsigned long cr;
95 unsigned long bank_size_bytes;
96 };
97
98 typedef struct bank_param BANKPARMS;
99
100 #ifdef CONFIG_SYS_SIMULATE_SPD_EEPROM
101 extern const unsigned char cfg_simulate_spd_eeprom[128];
102 #endif
103
104 static unsigned char spd_read(uchar chip, uint addr);
105 static void get_spd_info(unsigned long *dimm_populated,
106 unsigned char *iic0_dimm_addr,
107 unsigned long num_dimm_banks);
108 static void check_mem_type(unsigned long *dimm_populated,
109 unsigned char *iic0_dimm_addr,
110 unsigned long num_dimm_banks);
111 static void check_volt_type(unsigned long *dimm_populated,
112 unsigned char *iic0_dimm_addr,
113 unsigned long num_dimm_banks);
114 static void program_cfg0(unsigned long *dimm_populated,
115 unsigned char *iic0_dimm_addr,
116 unsigned long num_dimm_banks);
117 static void program_cfg1(unsigned long *dimm_populated,
118 unsigned char *iic0_dimm_addr,
119 unsigned long num_dimm_banks);
120 static void program_rtr(unsigned long *dimm_populated,
121 unsigned char *iic0_dimm_addr,
122 unsigned long num_dimm_banks);
123 static void program_tr0(unsigned long *dimm_populated,
124 unsigned char *iic0_dimm_addr,
125 unsigned long num_dimm_banks);
126 static void program_tr1(void);
127
128 static unsigned long program_bxcr(unsigned long *dimm_populated,
129 unsigned char *iic0_dimm_addr,
130 unsigned long num_dimm_banks);
131
132 /*
133 * This function is reading data from the DIMM module EEPROM over the SPD bus
134 * and uses that to program the sdram controller.
135 *
136 * This works on boards that has the same schematics that the AMCC walnut has.
137 *
138 * BUG: Don't handle ECC memory
139 * BUG: A few values in the TR register is currently hardcoded
140 */
141 long int spd_sdram(void) {
142 unsigned char iic0_dimm_addr[] = SPD_EEPROM_ADDRESS;
143 unsigned long dimm_populated[sizeof(iic0_dimm_addr)];
144 unsigned long total_size;
145 unsigned long cfg0;
146 unsigned long mcsts;
147 unsigned long num_dimm_banks; /* on board dimm banks */
148
149 num_dimm_banks = sizeof(iic0_dimm_addr);
150
151 /*
152 * Make sure I2C controller is initialized
153 * before continuing.
154 */
155 i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
156
157 /*
158 * Read the SPD information using I2C interface. Check to see if the
159 * DIMM slots are populated.
160 */
161 get_spd_info(dimm_populated, iic0_dimm_addr, num_dimm_banks);
162
163 /*
164 * Check the memory type for the dimms plugged.
165 */
166 check_mem_type(dimm_populated, iic0_dimm_addr, num_dimm_banks);
167
168 /*
169 * Check the voltage type for the dimms plugged.
170 */
171 check_volt_type(dimm_populated, iic0_dimm_addr, num_dimm_banks);
172
173 #if defined(CONFIG_440GX) || defined(CONFIG_440EP) || defined(CONFIG_440GR)
174 /*
175 * Soft-reset SDRAM controller.
176 */
177 mtsdr(SDR0_SRST, SDR0_SRST_DMC);
178 mtsdr(SDR0_SRST, 0x00000000);
179 #endif
180
181 /*
182 * program 440GP SDRAM controller options (SDRAM0_CFG0)
183 */
184 program_cfg0(dimm_populated, iic0_dimm_addr, num_dimm_banks);
185
186 /*
187 * program 440GP SDRAM controller options (SDRAM0_CFG1)
188 */
189 program_cfg1(dimm_populated, iic0_dimm_addr, num_dimm_banks);
190
191 /*
192 * program SDRAM refresh register (SDRAM0_RTR)
193 */
194 program_rtr(dimm_populated, iic0_dimm_addr, num_dimm_banks);
195
196 /*
197 * program SDRAM Timing Register 0 (SDRAM0_TR0)
198 */
199 program_tr0(dimm_populated, iic0_dimm_addr, num_dimm_banks);
200
201 /*
202 * program the BxCR registers to find out total sdram installed
203 */
204 total_size = program_bxcr(dimm_populated, iic0_dimm_addr,
205 num_dimm_banks);
206
207 #ifdef CONFIG_PROG_SDRAM_TLB /* this define should eventually be removed */
208 /* and program tlb entries for this size (dynamic) */
209 program_tlb(0, 0, total_size, MY_TLB_WORD2_I_ENABLE);
210 #endif
211
212 /*
213 * program SDRAM Clock Timing Register (SDRAM0_CLKTR)
214 */
215 mtsdram(SDRAM0_CLKTR, 0x40000000);
216
217 /*
218 * delay to ensure 200 usec has elapsed
219 */
220 udelay(400);
221
222 /*
223 * enable the memory controller
224 */
225 mfsdram(SDRAM0_CFG0, cfg0);
226 mtsdram(SDRAM0_CFG0, cfg0 | SDRAM_CFG0_DCEN);
227
228 /*
229 * wait for SDRAM_CFG0_DC_EN to complete
230 */
231 while (1) {
232 mfsdram(SDRAM0_MCSTS, mcsts);
233 if ((mcsts & SDRAM_MCSTS_MRSC) != 0)
234 break;
235 }
236
237 /*
238 * program SDRAM Timing Register 1, adding some delays
239 */
240 program_tr1();
241
242 #ifdef CONFIG_DDR_ECC
243 /*
244 * If ecc is enabled, initialize the parity bits.
245 */
246 ecc_init(CONFIG_SYS_SDRAM_BASE, total_size);
247 #endif
248
249 return total_size;
250 }
251
252 static unsigned char spd_read(uchar chip, uint addr)
253 {
254 unsigned char data[2];
255
256 #ifdef CONFIG_SYS_SIMULATE_SPD_EEPROM
257 if (chip == CONFIG_SYS_SIMULATE_SPD_EEPROM) {
258 /*
259 * Onboard spd eeprom requested -> simulate values
260 */
261 return cfg_simulate_spd_eeprom[addr];
262 }
263 #endif /* CONFIG_SYS_SIMULATE_SPD_EEPROM */
264
265 if (i2c_probe(chip) == 0) {
266 if (i2c_read(chip, addr, 1, data, 1) == 0) {
267 return data[0];
268 }
269 }
270
271 return 0;
272 }
273
274 static void get_spd_info(unsigned long *dimm_populated,
275 unsigned char *iic0_dimm_addr,
276 unsigned long num_dimm_banks)
277 {
278 unsigned long dimm_num;
279 unsigned long dimm_found;
280 unsigned char num_of_bytes;
281 unsigned char total_size;
282
283 dimm_found = false;
284 for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
285 num_of_bytes = 0;
286 total_size = 0;
287
288 num_of_bytes = spd_read(iic0_dimm_addr[dimm_num], 0);
289 total_size = spd_read(iic0_dimm_addr[dimm_num], 1);
290
291 if ((num_of_bytes != 0) && (total_size != 0)) {
292 dimm_populated[dimm_num] = true;
293 dimm_found = true;
294 debug("DIMM slot %lu: populated\n", dimm_num);
295 } else {
296 dimm_populated[dimm_num] = false;
297 debug("DIMM slot %lu: Not populated\n", dimm_num);
298 }
299 }
300
301 if (dimm_found == false) {
302 printf("ERROR - No memory installed. Install a DDR-SDRAM DIMM.\n\n");
303 spd_ddr_init_hang ();
304 }
305 }
306
307 static void check_mem_type(unsigned long *dimm_populated,
308 unsigned char *iic0_dimm_addr,
309 unsigned long num_dimm_banks)
310 {
311 unsigned long dimm_num;
312 unsigned char dimm_type;
313
314 for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
315 if (dimm_populated[dimm_num] == true) {
316 dimm_type = spd_read(iic0_dimm_addr[dimm_num], 2);
317 switch (dimm_type) {
318 case 7:
319 debug("DIMM slot %lu: DDR SDRAM detected\n", dimm_num);
320 break;
321 default:
322 printf("ERROR: Unsupported DIMM detected in slot %lu.\n",
323 dimm_num);
324 printf("Only DDR SDRAM DIMMs are supported.\n");
325 printf("Replace the DIMM module with a supported DIMM.\n\n");
326 spd_ddr_init_hang ();
327 break;
328 }
329 }
330 }
331 }
332
333 static void check_volt_type(unsigned long *dimm_populated,
334 unsigned char *iic0_dimm_addr,
335 unsigned long num_dimm_banks)
336 {
337 unsigned long dimm_num;
338 unsigned long voltage_type;
339
340 for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
341 if (dimm_populated[dimm_num] == true) {
342 voltage_type = spd_read(iic0_dimm_addr[dimm_num], 8);
343 if (voltage_type != 0x04) {
344 printf("ERROR: DIMM %lu with unsupported voltage level.\n",
345 dimm_num);
346 spd_ddr_init_hang ();
347 } else {
348 debug("DIMM %lu voltage level supported.\n", dimm_num);
349 }
350 break;
351 }
352 }
353 }
354
355 static void program_cfg0(unsigned long *dimm_populated,
356 unsigned char *iic0_dimm_addr,
357 unsigned long num_dimm_banks)
358 {
359 unsigned long dimm_num;
360 unsigned long cfg0;
361 unsigned long ecc_enabled;
362 unsigned char ecc;
363 unsigned char attributes;
364 unsigned long data_width;
365
366 /*
367 * get Memory Controller Options 0 data
368 */
369 mfsdram(SDRAM0_CFG0, cfg0);
370
371 /*
372 * clear bits
373 */
374 cfg0 &= ~(SDRAM_CFG0_DCEN | SDRAM_CFG0_MCHK_MASK |
375 SDRAM_CFG0_RDEN | SDRAM_CFG0_PMUD |
376 SDRAM_CFG0_DMWD_MASK |
377 SDRAM_CFG0_UIOS_MASK | SDRAM_CFG0_PDP);
378
379
380 /*
381 * FIXME: assume the DDR SDRAMs in both banks are the same
382 */
383 ecc_enabled = true;
384 for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
385 if (dimm_populated[dimm_num] == true) {
386 ecc = spd_read(iic0_dimm_addr[dimm_num], 11);
387 if (ecc != 0x02) {
388 ecc_enabled = false;
389 }
390
391 /*
392 * program Registered DIMM Enable
393 */
394 attributes = spd_read(iic0_dimm_addr[dimm_num], 21);
395 if ((attributes & 0x02) != 0x00) {
396 cfg0 |= SDRAM_CFG0_RDEN;
397 }
398
399 /*
400 * program DDR SDRAM Data Width
401 */
402 data_width =
403 (unsigned long)spd_read(iic0_dimm_addr[dimm_num],6) +
404 (((unsigned long)spd_read(iic0_dimm_addr[dimm_num],7)) << 8);
405 if (data_width == 64 || data_width == 72) {
406 cfg0 |= SDRAM_CFG0_DMWD_64;
407 } else if (data_width == 32 || data_width == 40) {
408 cfg0 |= SDRAM_CFG0_DMWD_32;
409 } else {
410 printf("WARNING: DIMM with datawidth of %lu bits.\n",
411 data_width);
412 printf("Only DIMMs with 32 or 64 bit datawidths supported.\n");
413 spd_ddr_init_hang ();
414 }
415 break;
416 }
417 }
418
419 /*
420 * program Memory Data Error Checking
421 */
422 if (ecc_enabled == true) {
423 cfg0 |= SDRAM_CFG0_MCHK_GEN;
424 } else {
425 cfg0 |= SDRAM_CFG0_MCHK_NON;
426 }
427
428 /*
429 * program Page Management Unit (0 == enabled)
430 */
431 cfg0 &= ~SDRAM_CFG0_PMUD;
432
433 /*
434 * program Memory Controller Options 0
435 * Note: DCEN must be enabled after all DDR SDRAM controller
436 * configuration registers get initialized.
437 */
438 mtsdram(SDRAM0_CFG0, cfg0);
439 }
440
441 static void program_cfg1(unsigned long *dimm_populated,
442 unsigned char *iic0_dimm_addr,
443 unsigned long num_dimm_banks)
444 {
445 unsigned long cfg1;
446 mfsdram(SDRAM0_CFG1, cfg1);
447
448 /*
449 * Self-refresh exit, disable PM
450 */
451 cfg1 &= ~(SDRAM_CFG1_SRE | SDRAM_CFG1_PMEN);
452
453 /*
454 * program Memory Controller Options 1
455 */
456 mtsdram(SDRAM0_CFG1, cfg1);
457 }
458
459 static void program_rtr(unsigned long *dimm_populated,
460 unsigned char *iic0_dimm_addr,
461 unsigned long num_dimm_banks)
462 {
463 unsigned long dimm_num;
464 unsigned long bus_period_x_10;
465 unsigned long refresh_rate = 0;
466 unsigned char refresh_rate_type;
467 unsigned long refresh_interval;
468 unsigned long sdram_rtr;
469 PPC4xx_SYS_INFO sys_info;
470
471 /*
472 * get the board info
473 */
474 get_sys_info(&sys_info);
475 bus_period_x_10 = ONE_BILLION / (sys_info.freqPLB / 10);
476
477 for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
478 if (dimm_populated[dimm_num] == true) {
479 refresh_rate_type = 0x7F & spd_read(iic0_dimm_addr[dimm_num], 12);
480 switch (refresh_rate_type) {
481 case 0x00:
482 refresh_rate = 15625;
483 break;
484 case 0x01:
485 refresh_rate = 15625/4;
486 break;
487 case 0x02:
488 refresh_rate = 15625/2;
489 break;
490 case 0x03:
491 refresh_rate = 15626*2;
492 break;
493 case 0x04:
494 refresh_rate = 15625*4;
495 break;
496 case 0x05:
497 refresh_rate = 15625*8;
498 break;
499 default:
500 printf("ERROR: DIMM %lu, unsupported refresh rate/type.\n",
501 dimm_num);
502 printf("Replace the DIMM module with a supported DIMM.\n");
503 break;
504 }
505
506 break;
507 }
508 }
509
510 refresh_interval = refresh_rate * 10 / bus_period_x_10;
511 sdram_rtr = (refresh_interval & 0x3ff8) << 16;
512
513 /*
514 * program Refresh Timer Register (SDRAM0_RTR)
515 */
516 mtsdram(SDRAM0_RTR, sdram_rtr);
517 }
518
519 static void program_tr0(unsigned long *dimm_populated,
520 unsigned char *iic0_dimm_addr,
521 unsigned long num_dimm_banks)
522 {
523 unsigned long dimm_num;
524 unsigned long tr0;
525 unsigned char wcsbc;
526 unsigned char t_rp_ns;
527 unsigned char t_rcd_ns;
528 unsigned char t_ras_ns;
529 unsigned long t_rp_clk;
530 unsigned long t_ras_rcd_clk;
531 unsigned long t_rcd_clk;
532 unsigned long t_rfc_clk;
533 unsigned long plb_check;
534 unsigned char cas_bit;
535 unsigned long cas_index;
536 unsigned char cas_2_0_available;
537 unsigned char cas_2_5_available;
538 unsigned char cas_3_0_available;
539 unsigned long cycle_time_ns_x_10[3];
540 unsigned long tcyc_3_0_ns_x_10;
541 unsigned long tcyc_2_5_ns_x_10;
542 unsigned long tcyc_2_0_ns_x_10;
543 unsigned long tcyc_reg;
544 unsigned long bus_period_x_10;
545 PPC4xx_SYS_INFO sys_info;
546 unsigned long residue;
547
548 /*
549 * get the board info
550 */
551 get_sys_info(&sys_info);
552 bus_period_x_10 = ONE_BILLION / (sys_info.freqPLB / 10);
553
554 /*
555 * get SDRAM Timing Register 0 (SDRAM_TR0) and clear bits
556 */
557 mfsdram(SDRAM0_TR0, tr0);
558 tr0 &= ~(SDRAM_TR0_SDWR_MASK | SDRAM_TR0_SDWD_MASK |
559 SDRAM_TR0_SDCL_MASK | SDRAM_TR0_SDPA_MASK |
560 SDRAM_TR0_SDCP_MASK | SDRAM_TR0_SDLD_MASK |
561 SDRAM_TR0_SDRA_MASK | SDRAM_TR0_SDRD_MASK);
562
563 /*
564 * initialization
565 */
566 wcsbc = 0;
567 t_rp_ns = 0;
568 t_rcd_ns = 0;
569 t_ras_ns = 0;
570 cas_2_0_available = true;
571 cas_2_5_available = true;
572 cas_3_0_available = true;
573 tcyc_2_0_ns_x_10 = 0;
574 tcyc_2_5_ns_x_10 = 0;
575 tcyc_3_0_ns_x_10 = 0;
576
577 for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
578 if (dimm_populated[dimm_num] == true) {
579 wcsbc = spd_read(iic0_dimm_addr[dimm_num], 15);
580 t_rp_ns = spd_read(iic0_dimm_addr[dimm_num], 27) >> 2;
581 t_rcd_ns = spd_read(iic0_dimm_addr[dimm_num], 29) >> 2;
582 t_ras_ns = spd_read(iic0_dimm_addr[dimm_num], 30);
583 cas_bit = spd_read(iic0_dimm_addr[dimm_num], 18);
584
585 for (cas_index = 0; cas_index < 3; cas_index++) {
586 switch (cas_index) {
587 case 0:
588 tcyc_reg = spd_read(iic0_dimm_addr[dimm_num], 9);
589 break;
590 case 1:
591 tcyc_reg = spd_read(iic0_dimm_addr[dimm_num], 23);
592 break;
593 default:
594 tcyc_reg = spd_read(iic0_dimm_addr[dimm_num], 25);
595 break;
596 }
597
598 if ((tcyc_reg & 0x0F) >= 10) {
599 printf("ERROR: Tcyc incorrect for DIMM in slot %lu\n",
600 dimm_num);
601 spd_ddr_init_hang ();
602 }
603
604 cycle_time_ns_x_10[cas_index] =
605 (((tcyc_reg & 0xF0) >> 4) * 10) + (tcyc_reg & 0x0F);
606 }
607
608 cas_index = 0;
609
610 if ((cas_bit & 0x80) != 0) {
611 cas_index += 3;
612 } else if ((cas_bit & 0x40) != 0) {
613 cas_index += 2;
614 } else if ((cas_bit & 0x20) != 0) {
615 cas_index += 1;
616 }
617
618 if (((cas_bit & 0x10) != 0) && (cas_index < 3)) {
619 tcyc_3_0_ns_x_10 = cycle_time_ns_x_10[cas_index];
620 cas_index++;
621 } else {
622 if (cas_index != 0) {
623 cas_index++;
624 }
625 cas_3_0_available = false;
626 }
627
628 if (((cas_bit & 0x08) != 0) || (cas_index < 3)) {
629 tcyc_2_5_ns_x_10 = cycle_time_ns_x_10[cas_index];
630 cas_index++;
631 } else {
632 if (cas_index != 0) {
633 cas_index++;
634 }
635 cas_2_5_available = false;
636 }
637
638 if (((cas_bit & 0x04) != 0) || (cas_index < 3)) {
639 tcyc_2_0_ns_x_10 = cycle_time_ns_x_10[cas_index];
640 cas_index++;
641 } else {
642 if (cas_index != 0) {
643 cas_index++;
644 }
645 cas_2_0_available = false;
646 }
647
648 break;
649 }
650 }
651
652 /*
653 * Program SD_WR and SD_WCSBC fields
654 */
655 tr0 |= SDRAM_TR0_SDWR_2_CLK; /* Write Recovery: 2 CLK */
656 switch (wcsbc) {
657 case 0:
658 tr0 |= SDRAM_TR0_SDWD_0_CLK;
659 break;
660 default:
661 tr0 |= SDRAM_TR0_SDWD_1_CLK;
662 break;
663 }
664
665 /*
666 * Program SD_CASL field
667 */
668 if ((cas_2_0_available == true) &&
669 (bus_period_x_10 >= tcyc_2_0_ns_x_10)) {
670 tr0 |= SDRAM_TR0_SDCL_2_0_CLK;
671 } else if ((cas_2_5_available == true) &&
672 (bus_period_x_10 >= tcyc_2_5_ns_x_10)) {
673 tr0 |= SDRAM_TR0_SDCL_2_5_CLK;
674 } else if ((cas_3_0_available == true) &&
675 (bus_period_x_10 >= tcyc_3_0_ns_x_10)) {
676 tr0 |= SDRAM_TR0_SDCL_3_0_CLK;
677 } else {
678 printf("ERROR: No supported CAS latency with the installed DIMMs.\n");
679 printf("Only CAS latencies of 2.0, 2.5, and 3.0 are supported.\n");
680 printf("Make sure the PLB speed is within the supported range.\n");
681 spd_ddr_init_hang ();
682 }
683
684 /*
685 * Calculate Trp in clock cycles and round up if necessary
686 * Program SD_PTA field
687 */
688 t_rp_clk = sys_info.freqPLB * t_rp_ns / ONE_BILLION;
689 plb_check = ONE_BILLION * t_rp_clk / t_rp_ns;
690 if (sys_info.freqPLB != plb_check) {
691 t_rp_clk++;
692 }
693 switch ((unsigned long)t_rp_clk) {
694 case 0:
695 case 1:
696 case 2:
697 tr0 |= SDRAM_TR0_SDPA_2_CLK;
698 break;
699 case 3:
700 tr0 |= SDRAM_TR0_SDPA_3_CLK;
701 break;
702 default:
703 tr0 |= SDRAM_TR0_SDPA_4_CLK;
704 break;
705 }
706
707 /*
708 * Program SD_CTP field
709 */
710 t_ras_rcd_clk = sys_info.freqPLB * (t_ras_ns - t_rcd_ns) / ONE_BILLION;
711 plb_check = ONE_BILLION * t_ras_rcd_clk / (t_ras_ns - t_rcd_ns);
712 if (sys_info.freqPLB != plb_check) {
713 t_ras_rcd_clk++;
714 }
715 switch (t_ras_rcd_clk) {
716 case 0:
717 case 1:
718 case 2:
719 tr0 |= SDRAM_TR0_SDCP_2_CLK;
720 break;
721 case 3:
722 tr0 |= SDRAM_TR0_SDCP_3_CLK;
723 break;
724 case 4:
725 tr0 |= SDRAM_TR0_SDCP_4_CLK;
726 break;
727 default:
728 tr0 |= SDRAM_TR0_SDCP_5_CLK;
729 break;
730 }
731
732 /*
733 * Program SD_LDF field
734 */
735 tr0 |= SDRAM_TR0_SDLD_2_CLK;
736
737 /*
738 * Program SD_RFTA field
739 * FIXME tRFC hardcoded as 75 nanoseconds
740 */
741 t_rfc_clk = sys_info.freqPLB / (ONE_BILLION / 75);
742 residue = sys_info.freqPLB % (ONE_BILLION / 75);
743 if (residue >= (ONE_BILLION / 150)) {
744 t_rfc_clk++;
745 }
746 switch (t_rfc_clk) {
747 case 0:
748 case 1:
749 case 2:
750 case 3:
751 case 4:
752 case 5:
753 case 6:
754 tr0 |= SDRAM_TR0_SDRA_6_CLK;
755 break;
756 case 7:
757 tr0 |= SDRAM_TR0_SDRA_7_CLK;
758 break;
759 case 8:
760 tr0 |= SDRAM_TR0_SDRA_8_CLK;
761 break;
762 case 9:
763 tr0 |= SDRAM_TR0_SDRA_9_CLK;
764 break;
765 case 10:
766 tr0 |= SDRAM_TR0_SDRA_10_CLK;
767 break;
768 case 11:
769 tr0 |= SDRAM_TR0_SDRA_11_CLK;
770 break;
771 case 12:
772 tr0 |= SDRAM_TR0_SDRA_12_CLK;
773 break;
774 default:
775 tr0 |= SDRAM_TR0_SDRA_13_CLK;
776 break;
777 }
778
779 /*
780 * Program SD_RCD field
781 */
782 t_rcd_clk = sys_info.freqPLB * t_rcd_ns / ONE_BILLION;
783 plb_check = ONE_BILLION * t_rcd_clk / t_rcd_ns;
784 if (sys_info.freqPLB != plb_check) {
785 t_rcd_clk++;
786 }
787 switch (t_rcd_clk) {
788 case 0:
789 case 1:
790 case 2:
791 tr0 |= SDRAM_TR0_SDRD_2_CLK;
792 break;
793 case 3:
794 tr0 |= SDRAM_TR0_SDRD_3_CLK;
795 break;
796 default:
797 tr0 |= SDRAM_TR0_SDRD_4_CLK;
798 break;
799 }
800
801 debug("tr0: %lx\n", tr0);
802 mtsdram(SDRAM0_TR0, tr0);
803 }
804
805 static int short_mem_test(void)
806 {
807 unsigned long i, j;
808 unsigned long bxcr_num;
809 unsigned long *membase;
810 const unsigned long test[NUMMEMTESTS][NUMMEMWORDS] = {
811 {0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
812 0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF},
813 {0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000,
814 0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000},
815 {0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555,
816 0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555},
817 {0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA,
818 0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA},
819 {0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A,
820 0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A},
821 {0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5,
822 0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5},
823 {0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA,
824 0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA},
825 {0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55,
826 0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55}};
827
828 for (bxcr_num = 0; bxcr_num < MAXBXCR; bxcr_num++) {
829 mtdcr(SDRAM0_CFGADDR, SDRAM0_B0CR + (bxcr_num << 2));
830 if ((mfdcr(SDRAM0_CFGDATA) & SDRAM_BXCR_SDBE) == SDRAM_BXCR_SDBE) {
831 /* Bank is enabled */
832 membase = (unsigned long*)
833 (mfdcr(SDRAM0_CFGDATA) & SDRAM_BXCR_SDBA_MASK);
834
835 /*
836 * Run the short memory test
837 */
838 for (i = 0; i < NUMMEMTESTS; i++) {
839 for (j = 0; j < NUMMEMWORDS; j++) {
840 /* printf("bank enabled base:%x\n", &membase[j]); */
841 membase[j] = test[i][j];
842 ppcDcbf((unsigned long)&(membase[j]));
843 }
844
845 for (j = 0; j < NUMMEMWORDS; j++) {
846 if (membase[j] != test[i][j]) {
847 ppcDcbf((unsigned long)&(membase[j]));
848 return 0;
849 }
850 ppcDcbf((unsigned long)&(membase[j]));
851 }
852
853 if (j < NUMMEMWORDS)
854 return 0;
855 }
856
857 /*
858 * see if the rdclt value passed
859 */
860 if (i < NUMMEMTESTS)
861 return 0;
862 }
863 }
864
865 return 1;
866 }
867
868 static void program_tr1(void)
869 {
870 unsigned long tr0;
871 unsigned long tr1;
872 unsigned long cfg0;
873 unsigned long ecc_temp;
874 unsigned long dlycal;
875 unsigned long dly_val;
876 unsigned long k;
877 unsigned long max_pass_length;
878 unsigned long current_pass_length;
879 unsigned long current_fail_length;
880 unsigned long current_start;
881 unsigned long rdclt;
882 unsigned long rdclt_offset;
883 long max_start;
884 long max_end;
885 long rdclt_average;
886 unsigned char window_found;
887 unsigned char fail_found;
888 unsigned char pass_found;
889 PPC4xx_SYS_INFO sys_info;
890
891 /*
892 * get the board info
893 */
894 get_sys_info(&sys_info);
895
896 /*
897 * get SDRAM Timing Register 0 (SDRAM_TR0) and clear bits
898 */
899 mfsdram(SDRAM0_TR1, tr1);
900 tr1 &= ~(SDRAM_TR1_RDSS_MASK | SDRAM_TR1_RDSL_MASK |
901 SDRAM_TR1_RDCD_MASK | SDRAM_TR1_RDCT_MASK);
902
903 mfsdram(SDRAM0_TR0, tr0);
904 if (((tr0 & SDRAM_TR0_SDCL_MASK) == SDRAM_TR0_SDCL_2_5_CLK) &&
905 (sys_info.freqPLB > 100000000)) {
906 tr1 |= SDRAM_TR1_RDSS_TR2;
907 tr1 |= SDRAM_TR1_RDSL_STAGE3;
908 tr1 |= SDRAM_TR1_RDCD_RCD_1_2;
909 } else {
910 tr1 |= SDRAM_TR1_RDSS_TR1;
911 tr1 |= SDRAM_TR1_RDSL_STAGE2;
912 tr1 |= SDRAM_TR1_RDCD_RCD_0_0;
913 }
914
915 /*
916 * save CFG0 ECC setting to a temporary variable and turn ECC off
917 */
918 mfsdram(SDRAM0_CFG0, cfg0);
919 ecc_temp = cfg0 & SDRAM_CFG0_MCHK_MASK;
920 mtsdram(SDRAM0_CFG0, (cfg0 & ~SDRAM_CFG0_MCHK_MASK) | SDRAM_CFG0_MCHK_NON);
921
922 /*
923 * get the delay line calibration register value
924 */
925 mfsdram(SDRAM0_DLYCAL, dlycal);
926 dly_val = SDRAM_DLYCAL_DLCV_DECODE(dlycal) << 2;
927
928 max_pass_length = 0;
929 max_start = 0;
930 max_end = 0;
931 current_pass_length = 0;
932 current_fail_length = 0;
933 current_start = 0;
934 rdclt_offset = 0;
935 window_found = false;
936 fail_found = false;
937 pass_found = false;
938 debug("Starting memory test ");
939
940 for (k = 0; k < NUMHALFCYCLES; k++) {
941 for (rdclt = 0; rdclt < dly_val; rdclt++) {
942 /*
943 * Set the timing reg for the test.
944 */
945 mtsdram(SDRAM0_TR1, (tr1 | SDRAM_TR1_RDCT_ENCODE(rdclt)));
946
947 if (short_mem_test()) {
948 if (fail_found == true) {
949 pass_found = true;
950 if (current_pass_length == 0) {
951 current_start = rdclt_offset + rdclt;
952 }
953
954 current_fail_length = 0;
955 current_pass_length++;
956
957 if (current_pass_length > max_pass_length) {
958 max_pass_length = current_pass_length;
959 max_start = current_start;
960 max_end = rdclt_offset + rdclt;
961 }
962 }
963 } else {
964 current_pass_length = 0;
965 current_fail_length++;
966
967 if (current_fail_length >= (dly_val>>2)) {
968 if (fail_found == false) {
969 fail_found = true;
970 } else if (pass_found == true) {
971 window_found = true;
972 break;
973 }
974 }
975 }
976 }
977 debug(".");
978
979 if (window_found == true)
980 break;
981
982 tr1 = tr1 ^ SDRAM_TR1_RDCD_MASK;
983 rdclt_offset += dly_val;
984 }
985 debug("\n");
986
987 /*
988 * make sure we find the window
989 */
990 if (window_found == false) {
991 printf("ERROR: Cannot determine a common read delay.\n");
992 spd_ddr_init_hang ();
993 }
994
995 /*
996 * restore the orignal ECC setting
997 */
998 mtsdram(SDRAM0_CFG0, (cfg0 & ~SDRAM_CFG0_MCHK_MASK) | ecc_temp);
999
1000 /*
1001 * set the SDRAM TR1 RDCD value
1002 */
1003 tr1 &= ~SDRAM_TR1_RDCD_MASK;
1004 if ((tr0 & SDRAM_TR0_SDCL_MASK) == SDRAM_TR0_SDCL_2_5_CLK) {
1005 tr1 |= SDRAM_TR1_RDCD_RCD_1_2;
1006 } else {
1007 tr1 |= SDRAM_TR1_RDCD_RCD_0_0;
1008 }
1009
1010 /*
1011 * set the SDRAM TR1 RDCLT value
1012 */
1013 tr1 &= ~SDRAM_TR1_RDCT_MASK;
1014 while (max_end >= (dly_val << 1)) {
1015 max_end -= (dly_val << 1);
1016 max_start -= (dly_val << 1);
1017 }
1018
1019 rdclt_average = ((max_start + max_end) >> 1);
1020
1021 if (rdclt_average < 0) {
1022 rdclt_average = 0;
1023 }
1024
1025 if (rdclt_average >= dly_val) {
1026 rdclt_average -= dly_val;
1027 tr1 = tr1 ^ SDRAM_TR1_RDCD_MASK;
1028 }
1029 tr1 |= SDRAM_TR1_RDCT_ENCODE(rdclt_average);
1030
1031 debug("tr1: %lx\n", tr1);
1032
1033 /*
1034 * program SDRAM Timing Register 1 TR1
1035 */
1036 mtsdram(SDRAM0_TR1, tr1);
1037 }
1038
1039 static unsigned long program_bxcr(unsigned long *dimm_populated,
1040 unsigned char *iic0_dimm_addr,
1041 unsigned long num_dimm_banks)
1042 {
1043 unsigned long dimm_num;
1044 unsigned long bank_base_addr;
1045 unsigned long cr;
1046 unsigned long i;
1047 unsigned long j;
1048 unsigned long temp;
1049 unsigned char num_row_addr;
1050 unsigned char num_col_addr;
1051 unsigned char num_banks;
1052 unsigned char bank_size_id;
1053 unsigned long ctrl_bank_num[MAXBANKS];
1054 unsigned long bx_cr_num;
1055 unsigned long largest_size_index;
1056 unsigned long largest_size;
1057 unsigned long current_size_index;
1058 BANKPARMS bank_parms[MAXBXCR];
1059 unsigned long sorted_bank_num[MAXBXCR]; /* DDR Controller bank number table (sorted by size) */
1060 unsigned long sorted_bank_size[MAXBXCR]; /* DDR Controller bank size table (sorted by size)*/
1061
1062 /*
1063 * Set the BxCR regs. First, wipe out the bank config registers.
1064 */
1065 for (bx_cr_num = 0; bx_cr_num < MAXBXCR; bx_cr_num++) {
1066 mtdcr(SDRAM0_CFGADDR, SDRAM0_B0CR + (bx_cr_num << 2));
1067 mtdcr(SDRAM0_CFGDATA, 0x00000000);
1068 bank_parms[bx_cr_num].bank_size_bytes = 0;
1069 }
1070
1071 #ifdef CONFIG_BAMBOO
1072 /*
1073 * This next section is hardware dependent and must be programmed
1074 * to match the hardware. For bamboo, the following holds...
1075 * 1. SDRAM0_B0CR: Bank 0 of dimm 0 ctrl_bank_num : 0 (soldered onboard)
1076 * 2. SDRAM0_B1CR: Bank 0 of dimm 1 ctrl_bank_num : 1
1077 * 3. SDRAM0_B2CR: Bank 1 of dimm 1 ctrl_bank_num : 1
1078 * 4. SDRAM0_B3CR: Bank 0 of dimm 2 ctrl_bank_num : 3
1079 * ctrl_bank_num corresponds to the first usable DDR controller bank number by DIMM
1080 */
1081 ctrl_bank_num[0] = 0;
1082 ctrl_bank_num[1] = 1;
1083 ctrl_bank_num[2] = 3;
1084 #else
1085 /*
1086 * Ocotea, Ebony and the other IBM/AMCC eval boards have
1087 * 2 DIMM slots with each max 2 banks
1088 */
1089 ctrl_bank_num[0] = 0;
1090 ctrl_bank_num[1] = 2;
1091 #endif
1092
1093 /*
1094 * reset the bank_base address
1095 */
1096 bank_base_addr = CONFIG_SYS_SDRAM_BASE;
1097
1098 for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
1099 if (dimm_populated[dimm_num] == true) {
1100 num_row_addr = spd_read(iic0_dimm_addr[dimm_num], 3);
1101 num_col_addr = spd_read(iic0_dimm_addr[dimm_num], 4);
1102 num_banks = spd_read(iic0_dimm_addr[dimm_num], 5);
1103 bank_size_id = spd_read(iic0_dimm_addr[dimm_num], 31);
1104 debug("DIMM%ld: row=%d col=%d banks=%d\n", dimm_num,
1105 num_row_addr, num_col_addr, num_banks);
1106
1107 /*
1108 * Set the SDRAM0_BxCR regs
1109 */
1110 cr = 0;
1111 switch (bank_size_id) {
1112 case 0x02:
1113 cr |= SDRAM_BXCR_SDSZ_8;
1114 break;
1115 case 0x04:
1116 cr |= SDRAM_BXCR_SDSZ_16;
1117 break;
1118 case 0x08:
1119 cr |= SDRAM_BXCR_SDSZ_32;
1120 break;
1121 case 0x10:
1122 cr |= SDRAM_BXCR_SDSZ_64;
1123 break;
1124 case 0x20:
1125 cr |= SDRAM_BXCR_SDSZ_128;
1126 break;
1127 case 0x40:
1128 cr |= SDRAM_BXCR_SDSZ_256;
1129 break;
1130 case 0x80:
1131 cr |= SDRAM_BXCR_SDSZ_512;
1132 break;
1133 default:
1134 printf("DDR-SDRAM: DIMM %lu BxCR configuration.\n",
1135 dimm_num);
1136 printf("ERROR: Unsupported value for the banksize: %d.\n",
1137 bank_size_id);
1138 printf("Replace the DIMM module with a supported DIMM.\n\n");
1139 spd_ddr_init_hang ();
1140 }
1141
1142 switch (num_col_addr) {
1143 case 0x08:
1144 cr |= SDRAM_BXCR_SDAM_1;
1145 break;
1146 case 0x09:
1147 cr |= SDRAM_BXCR_SDAM_2;
1148 break;
1149 case 0x0A:
1150 cr |= SDRAM_BXCR_SDAM_3;
1151 break;
1152 case 0x0B:
1153 cr |= SDRAM_BXCR_SDAM_4;
1154 break;
1155 default:
1156 printf("DDR-SDRAM: DIMM %lu BxCR configuration.\n",
1157 dimm_num);
1158 printf("ERROR: Unsupported value for number of "
1159 "column addresses: %d.\n", num_col_addr);
1160 printf("Replace the DIMM module with a supported DIMM.\n\n");
1161 spd_ddr_init_hang ();
1162 }
1163
1164 /*
1165 * enable the bank
1166 */
1167 cr |= SDRAM_BXCR_SDBE;
1168
1169 for (i = 0; i < num_banks; i++) {
1170 bank_parms[ctrl_bank_num[dimm_num]+i].bank_size_bytes =
1171 (4 << 20) * bank_size_id;
1172 bank_parms[ctrl_bank_num[dimm_num]+i].cr = cr;
1173 debug("DIMM%ld-bank %ld (SDRAM0_B%ldCR): "
1174 "bank_size_bytes=%ld\n",
1175 dimm_num, i,
1176 ctrl_bank_num[dimm_num] + i,
1177 bank_parms[ctrl_bank_num[dimm_num] + i].bank_size_bytes);
1178 }
1179 }
1180 }
1181
1182 /* Initialize sort tables */
1183 for (i = 0; i < MAXBXCR; i++) {
1184 sorted_bank_num[i] = i;
1185 sorted_bank_size[i] = bank_parms[i].bank_size_bytes;
1186 }
1187
1188 for (i = 0; i < MAXBXCR-1; i++) {
1189 largest_size = sorted_bank_size[i];
1190 largest_size_index = 255;
1191
1192 /* Find the largest remaining value */
1193 for (j = i + 1; j < MAXBXCR; j++) {
1194 if (sorted_bank_size[j] > largest_size) {
1195 /* Save largest remaining value and its index */
1196 largest_size = sorted_bank_size[j];
1197 largest_size_index = j;
1198 }
1199 }
1200
1201 if (largest_size_index != 255) {
1202 /* Swap the current and largest values */
1203 current_size_index = sorted_bank_num[largest_size_index];
1204 sorted_bank_size[largest_size_index] = sorted_bank_size[i];
1205 sorted_bank_size[i] = largest_size;
1206 sorted_bank_num[largest_size_index] = sorted_bank_num[i];
1207 sorted_bank_num[i] = current_size_index;
1208 }
1209 }
1210
1211 /* Set the SDRAM0_BxCR regs thanks to sort tables */
1212 for (bx_cr_num = 0, bank_base_addr = 0; bx_cr_num < MAXBXCR; bx_cr_num++) {
1213 if (bank_parms[sorted_bank_num[bx_cr_num]].bank_size_bytes) {
1214 mtdcr(SDRAM0_CFGADDR, SDRAM0_B0CR + (sorted_bank_num[bx_cr_num] << 2));
1215 temp = mfdcr(SDRAM0_CFGDATA) & ~(SDRAM_BXCR_SDBA_MASK | SDRAM_BXCR_SDSZ_MASK |
1216 SDRAM_BXCR_SDAM_MASK | SDRAM_BXCR_SDBE);
1217 temp = temp | (bank_base_addr & SDRAM_BXCR_SDBA_MASK) |
1218 bank_parms[sorted_bank_num[bx_cr_num]].cr;
1219 mtdcr(SDRAM0_CFGDATA, temp);
1220 bank_base_addr += bank_parms[sorted_bank_num[bx_cr_num]].bank_size_bytes;
1221 debug("SDRAM0_B%ldCR=0x%08lx\n",
1222 sorted_bank_num[bx_cr_num], temp);
1223 }
1224 }
1225
1226 return(bank_base_addr);
1227 }
1228 #endif /* CONFIG_SPD_EEPROM */
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