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Merge branch 'master' of git://www.denx.de/git/u-boot-cfi-flash
[people/ms/u-boot.git] / arch / powerpc / cpu / ppc4xx / 4xx_ibm_ddr2_autocalib.c
1 /*
2 * arch/powerpc/cpu/ppc4xx/4xx_ibm_ddr2_autocalib.c
3 * This SPD SDRAM detection code supports AMCC PPC44x cpu's with a
4 * DDR2 controller (non Denali Core). Those currently are:
5 *
6 * 405: 405EX
7 * 440/460: 440SP/440SPe/460EX/460GT/460SX
8 *
9 * (C) Copyright 2008 Applied Micro Circuits Corporation
10 * Adam Graham <agraham@amcc.com>
11 *
12 * (C) Copyright 2007-2008
13 * Stefan Roese, DENX Software Engineering, sr@denx.de.
14 *
15 * COPYRIGHT AMCC CORPORATION 2004
16 *
17 * SPDX-License-Identifier: GPL-2.0+
18 */
19
20 /* define DEBUG for debugging output (obviously ;-)) */
21 #undef DEBUG
22
23 #include <common.h>
24 #include <asm/ppc4xx.h>
25 #include <asm/io.h>
26 #include <asm/processor.h>
27
28 #include "ecc.h"
29
30 /*
31 * Only compile the DDR auto-calibration code for NOR boot and
32 * not for NAND boot (NAND SPL and NAND U-Boot - NUB)
33 */
34 #if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
35
36 #define MAXBXCF 4
37 #define SDRAM_RXBAS_SHIFT_1M 20
38
39 #if defined(CONFIG_SYS_DECREMENT_PATTERNS)
40 #define NUMMEMTESTS 24
41 #else
42 #define NUMMEMTESTS 8
43 #endif /* CONFIG_SYS_DECREMENT_PATTERNS */
44 #define NUMLOOPS 1 /* configure as you deem approporiate */
45 #define NUMMEMWORDS 16
46
47 #define SDRAM_RDCC_RDSS_VAL(n) SDRAM_RDCC_RDSS_DECODE(ddr_rdss_opt(n))
48
49 /* Private Structure Definitions */
50
51 struct autocal_regs {
52 u32 rffd;
53 u32 rqfd;
54 };
55
56 struct ddrautocal {
57 u32 rffd;
58 u32 rffd_min;
59 u32 rffd_max;
60 u32 rffd_size;
61 u32 rqfd;
62 u32 rqfd_size;
63 u32 rdcc;
64 u32 flags;
65 };
66
67 struct sdram_timing_clks {
68 u32 wrdtr;
69 u32 clktr;
70 u32 rdcc;
71 u32 flags;
72 };
73
74 struct autocal_clks {
75 struct sdram_timing_clks clocks;
76 struct ddrautocal autocal;
77 };
78
79 /*--------------------------------------------------------------------------+
80 * Prototypes
81 *--------------------------------------------------------------------------*/
82 #if defined(CONFIG_PPC4xx_DDR_METHOD_A)
83 static u32 DQS_calibration_methodA(struct ddrautocal *);
84 static u32 program_DQS_calibration_methodA(struct ddrautocal *);
85 #else
86 static u32 DQS_calibration_methodB(struct ddrautocal *);
87 static u32 program_DQS_calibration_methodB(struct ddrautocal *);
88 #endif
89 static int short_mem_test(u32 *);
90
91 /*
92 * To provide an interface for board specific config values in this common
93 * DDR setup code, we implement he "weak" default functions here. They return
94 * the default value back to the caller.
95 *
96 * Please see include/configs/yucca.h for an example fora board specific
97 * implementation.
98 */
99
100 #if !defined(CONFIG_SPD_EEPROM)
101 u32 __ddr_wrdtr(u32 default_val)
102 {
103 return default_val;
104 }
105 u32 ddr_wrdtr(u32) __attribute__((weak, alias("__ddr_wrdtr")));
106
107 u32 __ddr_clktr(u32 default_val)
108 {
109 return default_val;
110 }
111 u32 ddr_clktr(u32) __attribute__((weak, alias("__ddr_clktr")));
112
113 /*
114 * Board-specific Platform code can reimplement spd_ddr_init_hang () if needed
115 */
116 void __spd_ddr_init_hang(void)
117 {
118 hang();
119 }
120 void
121 spd_ddr_init_hang(void) __attribute__((weak, alias("__spd_ddr_init_hang")));
122 #endif /* defined(CONFIG_SPD_EEPROM) */
123
124 struct sdram_timing *__ddr_scan_option(struct sdram_timing *default_val)
125 {
126 return default_val;
127 }
128 struct sdram_timing *ddr_scan_option(struct sdram_timing *)
129 __attribute__((weak, alias("__ddr_scan_option")));
130
131 u32 __ddr_rdss_opt(u32 default_val)
132 {
133 return default_val;
134 }
135 u32 ddr_rdss_opt(ulong) __attribute__((weak, alias("__ddr_rdss_opt")));
136
137
138 static u32 *get_membase(int bxcr_num)
139 {
140 u32 *membase;
141
142 #if defined(SDRAM_R0BAS)
143 /* BAS from Memory Queue rank reg. */
144 membase =
145 (u32 *)(SDRAM_RXBAS_SDBA_DECODE(mfdcr_any(SDRAM_R0BAS+bxcr_num)));
146 #else
147 {
148 ulong bxcf;
149
150 /* BAS from SDRAM_MBxCF mem rank reg. */
151 mfsdram(SDRAM_MB0CF + (bxcr_num<<2), bxcf);
152 membase = (u32 *)((bxcf & 0xfff80000) << 3);
153 }
154 #endif
155
156 return membase;
157 }
158
159 static inline void ecc_clear_status_reg(void)
160 {
161 mtsdram(SDRAM_ECCES, 0xffffffff);
162 #if defined(SDRAM_R0BAS)
163 mtdcr(SDRAM_ERRSTATLL, 0xffffffff);
164 #endif
165 }
166
167 /*
168 * Reset and relock memory DLL after SDRAM_CLKTR change
169 */
170 static inline void relock_memory_DLL(void)
171 {
172 u32 reg;
173
174 mtsdram(SDRAM_MCOPT2, SDRAM_MCOPT2_IPTR_EXECUTE);
175
176 do {
177 mfsdram(SDRAM_MCSTAT, reg);
178 } while (!(reg & SDRAM_MCSTAT_MIC_COMP));
179
180 mfsdram(SDRAM_MCOPT2, reg);
181 mtsdram(SDRAM_MCOPT2, reg | SDRAM_MCOPT2_DCEN_ENABLE);
182 }
183
184 static int ecc_check_status_reg(void)
185 {
186 u32 ecc_status;
187
188 /*
189 * Compare suceeded, now check
190 * if got ecc error. If got an
191 * ecc error, then don't count
192 * this as a passing value
193 */
194 mfsdram(SDRAM_ECCES, ecc_status);
195 if (ecc_status != 0x00000000) {
196 /* clear on error */
197 ecc_clear_status_reg();
198 /* ecc check failure */
199 return 0;
200 }
201 ecc_clear_status_reg();
202 sync();
203
204 return 1;
205 }
206
207 /* return 1 if passes, 0 if fail */
208 static int short_mem_test(u32 *base_address)
209 {
210 int i, j, l;
211 u32 ecc_mode = 0;
212
213 ulong test[NUMMEMTESTS][NUMMEMWORDS] = {
214 /* 0 */ {0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
215 0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
216 0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
217 0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF},
218 /* 1 */ {0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000,
219 0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000,
220 0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000,
221 0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000},
222 /* 2 */ {0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555,
223 0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555,
224 0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555,
225 0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555},
226 /* 3 */ {0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA,
227 0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA,
228 0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA,
229 0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA},
230 /* 4 */ {0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A,
231 0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A,
232 0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A,
233 0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A},
234 /* 5 */ {0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5,
235 0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5,
236 0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5,
237 0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5},
238 /* 6 */ {0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA,
239 0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA,
240 0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA,
241 0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA},
242 /* 7 */ {0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55,
243 0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55,
244 0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55,
245 0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55},
246
247 #if defined(CONFIG_SYS_DECREMENT_PATTERNS)
248 /* 8 */ {0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
249 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
250 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
251 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff},
252 /* 9 */ {0xfffefffe, 0xfffefffe, 0xfffefffe, 0xfffefffe,
253 0xfffefffe, 0xfffefffe, 0xfffefffe, 0xfffefffe,
254 0xfffefffe, 0xfffefffe, 0xfffefffe, 0xfffefffe,
255 0xfffefffe, 0xfffefffe, 0xfffefffe, 0xfffefffe},
256 /* 10 */{0xfffdfffd, 0xfffdfffd, 0xfffdffff, 0xfffdfffd,
257 0xfffdfffd, 0xfffdfffd, 0xfffdffff, 0xfffdfffd,
258 0xfffdfffd, 0xfffdfffd, 0xfffdffff, 0xfffdfffd,
259 0xfffdfffd, 0xfffdfffd, 0xfffdffff, 0xfffdfffd},
260 /* 11 */{0xfffcfffc, 0xfffcfffc, 0xfffcfffc, 0xfffcfffc,
261 0xfffcfffc, 0xfffcfffc, 0xfffcfffc, 0xfffcfffc,
262 0xfffcfffc, 0xfffcfffc, 0xfffcfffc, 0xfffcfffc,
263 0xfffcfffc, 0xfffcfffc, 0xfffcfffc, 0xfffcfffc},
264 /* 12 */{0xfffbfffb, 0xfffffffb, 0xfffffffb, 0xfffffffb,
265 0xfffbfffb, 0xfffffffb, 0xfffffffb, 0xfffffffb,
266 0xfffbfffb, 0xfffffffb, 0xfffffffb, 0xfffffffb,
267 0xfffbfffb, 0xfffffffb, 0xfffffffb, 0xfffffffb},
268 /* 13 */{0xfffafffa, 0xfffafffa, 0xfffffffa, 0xfffafffa,
269 0xfffafffa, 0xfffafffa, 0xfffafffa, 0xfffafffa,
270 0xfffafffa, 0xfffafffa, 0xfffafffa, 0xfffafffa,
271 0xfffafffa, 0xfffafffa, 0xfffafffa, 0xfffafffa},
272 /* 14 */{0xfff9fff9, 0xfff9fff9, 0xfff9fff9, 0xfff9fff9,
273 0xfff9fff9, 0xfff9fff9, 0xfff9fff9, 0xfff9fff9,
274 0xfff9fff9, 0xfff9fff9, 0xfff9fff9, 0xfff9fff9,
275 0xfff9fff9, 0xfff9fff9, 0xfff9fff9, 0xfff9fff9},
276 /* 15 */{0xfff8fff8, 0xfff8fff8, 0xfff8fff8, 0xfff8fff8,
277 0xfff8fff8, 0xfff8fff8, 0xfff8fff8, 0xfff8fff8,
278 0xfff8fff8, 0xfff8fff8, 0xfff8fff8, 0xfff8fff8,
279 0xfff8fff8, 0xfff8fff8, 0xfff8fff8, 0xfff8fff8},
280 /* 16 */{0xfff7fff7, 0xfff7ffff, 0xfff7fff7, 0xfff7fff7,
281 0xfff7fff7, 0xfff7ffff, 0xfff7fff7, 0xfff7fff7,
282 0xfff7fff7, 0xfff7ffff, 0xfff7fff7, 0xfff7fff7,
283 0xfff7ffff, 0xfff7ffff, 0xfff7fff7, 0xfff7fff7},
284 /* 17 */{0xfff6fff5, 0xfff6ffff, 0xfff6fff6, 0xfff6fff7,
285 0xfff6fff5, 0xfff6ffff, 0xfff6fff6, 0xfff6fff7,
286 0xfff6fff5, 0xfff6ffff, 0xfff6fff6, 0xfff6fff7,
287 0xfff6fff5, 0xfff6ffff, 0xfff6fff6, 0xfff6fff7},
288 /* 18 */{0xfff5fff4, 0xfff5ffff, 0xfff5fff5, 0xfff5fff5,
289 0xfff5fff4, 0xfff5ffff, 0xfff5fff5, 0xfff5fff5,
290 0xfff5fff4, 0xfff5ffff, 0xfff5fff5, 0xfff5fff5,
291 0xfff5fff4, 0xfff5ffff, 0xfff5fff5, 0xfff5fff5},
292 /* 19 */{0xfff4fff3, 0xfff4ffff, 0xfff4fff4, 0xfff4fff4,
293 0xfff4fff3, 0xfff4ffff, 0xfff4fff4, 0xfff4fff4,
294 0xfff4fff3, 0xfff4ffff, 0xfff4fff4, 0xfff4fff4,
295 0xfff4fff3, 0xfff4ffff, 0xfff4fff4, 0xfff4fff4},
296 /* 20 */{0xfff3fff2, 0xfff3ffff, 0xfff3fff3, 0xfff3fff3,
297 0xfff3fff2, 0xfff3ffff, 0xfff3fff3, 0xfff3fff3,
298 0xfff3fff2, 0xfff3ffff, 0xfff3fff3, 0xfff3fff3,
299 0xfff3fff2, 0xfff3ffff, 0xfff3fff3, 0xfff3fff3},
300 /* 21 */{0xfff2ffff, 0xfff2ffff, 0xfff2fff2, 0xfff2fff2,
301 0xfff2ffff, 0xfff2ffff, 0xfff2fff2, 0xfff2fff2,
302 0xfff2ffff, 0xfff2ffff, 0xfff2fff2, 0xfff2fff2,
303 0xfff2ffff, 0xfff2ffff, 0xfff2fff2, 0xfff2fff2},
304 /* 22 */{0xfff1ffff, 0xfff1ffff, 0xfff1fff1, 0xfff1fff1,
305 0xfff1ffff, 0xfff1ffff, 0xfff1fff1, 0xfff1fff1,
306 0xfff1ffff, 0xfff1ffff, 0xfff1fff1, 0xfff1fff1,
307 0xfff1ffff, 0xfff1ffff, 0xfff1fff1, 0xfff1fff1},
308 /* 23 */{0xfff0fff0, 0xfff0fff0, 0xfff0fff0, 0xfff0fff0,
309 0xfff0fff0, 0xfff0fff0, 0xfff0fff0, 0xfff0fff0,
310 0xfff0fff0, 0xfff0fff0, 0xfff0fff0, 0xfff0fff0,
311 0xfff0fff0, 0xfff0fffe, 0xfff0fff0, 0xfff0fff0},
312 #endif /* CONFIG_SYS_DECREMENT_PATTERNS */
313 };
314
315 mfsdram(SDRAM_MCOPT1, ecc_mode);
316 if ((ecc_mode & SDRAM_MCOPT1_MCHK_CHK_REP) ==
317 SDRAM_MCOPT1_MCHK_CHK_REP) {
318 ecc_clear_status_reg();
319 sync();
320 ecc_mode = 1;
321 } else {
322 ecc_mode = 0;
323 }
324
325 /*
326 * Run the short memory test.
327 */
328 for (i = 0; i < NUMMEMTESTS; i++) {
329 for (j = 0; j < NUMMEMWORDS; j++) {
330 base_address[j] = test[i][j];
331 ppcDcbf((ulong)&(base_address[j]));
332 }
333 sync();
334 iobarrier_rw();
335 for (l = 0; l < NUMLOOPS; l++) {
336 for (j = 0; j < NUMMEMWORDS; j++) {
337 if (base_address[j] != test[i][j]) {
338 ppcDcbf((u32)&(base_address[j]));
339 return 0;
340 } else {
341 if (ecc_mode) {
342 if (!ecc_check_status_reg())
343 return 0;
344 }
345 }
346 ppcDcbf((u32)&(base_address[j]));
347 } /* for (j = 0; j < NUMMEMWORDS; j++) */
348 sync();
349 iobarrier_rw();
350 } /* for (l=0; l<NUMLOOPS; l++) */
351 }
352
353 return 1;
354 }
355
356 #if defined(CONFIG_PPC4xx_DDR_METHOD_A)
357 /*-----------------------------------------------------------------------------+
358 | program_DQS_calibration_methodA.
359 +-----------------------------------------------------------------------------*/
360 static u32 program_DQS_calibration_methodA(struct ddrautocal *ddrcal)
361 {
362 u32 pass_result = 0;
363
364 #ifdef DEBUG
365 ulong temp;
366
367 mfsdram(SDRAM_RDCC, temp);
368 debug("<%s>SDRAM_RDCC=0x%08x\n", __func__, temp);
369 #endif
370
371 pass_result = DQS_calibration_methodA(ddrcal);
372
373 return pass_result;
374 }
375
376 /*
377 * DQS_calibration_methodA()
378 *
379 * Autocalibration Method A
380 *
381 * ARRAY [Entire DQS Range] DQS_Valid_Window ; initialized to all zeros
382 * ARRAY [Entire FDBK Range] FDBK_Valid_Window; initialized to all zeros
383 * MEMWRITE(addr, expected_data);
384 * for (i = 0; i < Entire DQS Range; i++) { RQDC.RQFD
385 * for (j = 0; j < Entire FDBK Range; j++) { RFDC.RFFD
386 * MEMREAD(addr, actual_data);
387 * if (actual_data == expected_data) {
388 * DQS_Valid_Window[i] = 1; RQDC.RQFD
389 * FDBK_Valid_Window[i][j] = 1; RFDC.RFFD
390 * }
391 * }
392 * }
393 */
394 static u32 DQS_calibration_methodA(struct ddrautocal *cal)
395 {
396 ulong rfdc_reg;
397 ulong rffd;
398
399 ulong rqdc_reg;
400 ulong rqfd;
401
402 u32 *membase;
403 ulong bxcf;
404 int rqfd_average;
405 int bxcr_num;
406 int rffd_average;
407 int pass;
408 u32 passed = 0;
409
410 int in_window;
411 struct autocal_regs curr_win_min;
412 struct autocal_regs curr_win_max;
413 struct autocal_regs best_win_min;
414 struct autocal_regs best_win_max;
415 struct autocal_regs loop_win_min;
416 struct autocal_regs loop_win_max;
417
418 #ifdef DEBUG
419 ulong temp;
420 #endif
421 ulong rdcc;
422
423 char slash[] = "\\|/-\\|/-";
424 int loopi = 0;
425
426 /* start */
427 in_window = 0;
428
429 memset(&curr_win_min, 0, sizeof(curr_win_min));
430 memset(&curr_win_max, 0, sizeof(curr_win_max));
431 memset(&best_win_min, 0, sizeof(best_win_min));
432 memset(&best_win_max, 0, sizeof(best_win_max));
433 memset(&loop_win_min, 0, sizeof(loop_win_min));
434 memset(&loop_win_max, 0, sizeof(loop_win_max));
435
436 rdcc = 0;
437
438 /*
439 * Program RDCC register
440 * Read sample cycle auto-update enable
441 */
442 mtsdram(SDRAM_RDCC,
443 ddr_rdss_opt(SDRAM_RDCC_RDSS_T2) | SDRAM_RDCC_RSAE_ENABLE);
444
445 #ifdef DEBUG
446 mfsdram(SDRAM_RDCC, temp);
447 debug("<%s>SDRAM_RDCC=0x%x\n", __func__, temp);
448 mfsdram(SDRAM_RTSR, temp);
449 debug("<%s>SDRAM_RTSR=0x%x\n", __func__, temp);
450 mfsdram(SDRAM_FCSR, temp);
451 debug("<%s>SDRAM_FCSR=0x%x\n", __func__, temp);
452 #endif
453
454 /*
455 * Program RQDC register
456 * Internal DQS delay mechanism enable
457 */
458 mtsdram(SDRAM_RQDC,
459 SDRAM_RQDC_RQDE_ENABLE | SDRAM_RQDC_RQFD_ENCODE(0x00));
460
461 #ifdef DEBUG
462 mfsdram(SDRAM_RQDC, temp);
463 debug("<%s>SDRAM_RQDC=0x%x\n", __func__, temp);
464 #endif
465
466 /*
467 * Program RFDC register
468 * Set Feedback Fractional Oversample
469 * Auto-detect read sample cycle enable
470 */
471 mtsdram(SDRAM_RFDC, SDRAM_RFDC_ARSE_ENABLE |
472 SDRAM_RFDC_RFOS_ENCODE(0) | SDRAM_RFDC_RFFD_ENCODE(0));
473
474 #ifdef DEBUG
475 mfsdram(SDRAM_RFDC, temp);
476 debug("<%s>SDRAM_RFDC=0x%x\n", __func__, temp);
477 #endif
478
479 putc(' ');
480 for (rqfd = 0; rqfd <= SDRAM_RQDC_RQFD_MAX; rqfd++) {
481
482 mfsdram(SDRAM_RQDC, rqdc_reg);
483 rqdc_reg &= ~(SDRAM_RQDC_RQFD_MASK);
484 mtsdram(SDRAM_RQDC, rqdc_reg | SDRAM_RQDC_RQFD_ENCODE(rqfd));
485
486 putc('\b');
487 putc(slash[loopi++ % 8]);
488
489 curr_win_min.rffd = 0;
490 curr_win_max.rffd = 0;
491 in_window = 0;
492
493 for (rffd = 0, pass = 0; rffd <= SDRAM_RFDC_RFFD_MAX; rffd++) {
494 mfsdram(SDRAM_RFDC, rfdc_reg);
495 rfdc_reg &= ~(SDRAM_RFDC_RFFD_MASK);
496 mtsdram(SDRAM_RFDC,
497 rfdc_reg | SDRAM_RFDC_RFFD_ENCODE(rffd));
498
499 for (bxcr_num = 0; bxcr_num < MAXBXCF; bxcr_num++) {
500 mfsdram(SDRAM_MB0CF + (bxcr_num<<2), bxcf);
501
502 /* Banks enabled */
503 if (bxcf & SDRAM_BXCF_M_BE_MASK) {
504 /* Bank is enabled */
505 membase = get_membase(bxcr_num);
506 pass = short_mem_test(membase);
507 } /* if bank enabled */
508 } /* for bxcr_num */
509
510 /* If this value passed update RFFD windows */
511 if (pass && !in_window) { /* at the start of window */
512 in_window = 1;
513 curr_win_min.rffd = curr_win_max.rffd = rffd;
514 curr_win_min.rqfd = curr_win_max.rqfd = rqfd;
515 mfsdram(SDRAM_RDCC, rdcc); /*record this value*/
516 } else if (!pass && in_window) { /* at end of window */
517 in_window = 0;
518 } else if (pass && in_window) { /* within the window */
519 curr_win_max.rffd = rffd;
520 curr_win_max.rqfd = rqfd;
521 }
522 /* else if (!pass && !in_window)
523 skip - no pass, not currently in a window */
524
525 if (in_window) {
526 if ((curr_win_max.rffd - curr_win_min.rffd) >
527 (best_win_max.rffd - best_win_min.rffd)) {
528 best_win_min.rffd = curr_win_min.rffd;
529 best_win_max.rffd = curr_win_max.rffd;
530
531 best_win_min.rqfd = curr_win_min.rqfd;
532 best_win_max.rqfd = curr_win_max.rqfd;
533 cal->rdcc = rdcc;
534 }
535 passed = 1;
536 }
537 } /* RFDC.RFFD */
538
539 /*
540 * save-off the best window results of the RFDC.RFFD
541 * for this RQDC.RQFD setting
542 */
543 /*
544 * if (just ended RFDC.RFDC loop pass window) >
545 * (prior RFDC.RFFD loop pass window)
546 */
547 if ((best_win_max.rffd - best_win_min.rffd) >
548 (loop_win_max.rffd - loop_win_min.rffd)) {
549 loop_win_min.rffd = best_win_min.rffd;
550 loop_win_max.rffd = best_win_max.rffd;
551 loop_win_min.rqfd = rqfd;
552 loop_win_max.rqfd = rqfd;
553 debug("RQFD.min 0x%08x, RQFD.max 0x%08x, "
554 "RFFD.min 0x%08x, RFFD.max 0x%08x\n",
555 loop_win_min.rqfd, loop_win_max.rqfd,
556 loop_win_min.rffd, loop_win_max.rffd);
557 }
558 } /* RQDC.RQFD */
559
560 putc('\b');
561
562 debug("\n");
563
564 if ((loop_win_min.rffd == 0) && (loop_win_max.rffd == 0) &&
565 (best_win_min.rffd == 0) && (best_win_max.rffd == 0) &&
566 (best_win_min.rqfd == 0) && (best_win_max.rqfd == 0)) {
567 passed = 0;
568 }
569
570 /*
571 * Need to program RQDC before RFDC.
572 */
573 debug("<%s> RQFD Min: 0x%x\n", __func__, loop_win_min.rqfd);
574 debug("<%s> RQFD Max: 0x%x\n", __func__, loop_win_max.rqfd);
575 rqfd_average = loop_win_max.rqfd;
576
577 if (rqfd_average < 0)
578 rqfd_average = 0;
579
580 if (rqfd_average > SDRAM_RQDC_RQFD_MAX)
581 rqfd_average = SDRAM_RQDC_RQFD_MAX;
582
583 debug("<%s> RFFD average: 0x%08x\n", __func__, rqfd_average);
584 mtsdram(SDRAM_RQDC, (rqdc_reg & ~SDRAM_RQDC_RQFD_MASK) |
585 SDRAM_RQDC_RQFD_ENCODE(rqfd_average));
586
587 debug("<%s> RFFD Min: 0x%08x\n", __func__, loop_win_min.rffd);
588 debug("<%s> RFFD Max: 0x%08x\n", __func__, loop_win_max.rffd);
589 rffd_average = ((loop_win_min.rffd + loop_win_max.rffd) / 2);
590
591 if (rffd_average < 0)
592 rffd_average = 0;
593
594 if (rffd_average > SDRAM_RFDC_RFFD_MAX)
595 rffd_average = SDRAM_RFDC_RFFD_MAX;
596
597 debug("<%s> RFFD average: 0x%08x\n", __func__, rffd_average);
598 mtsdram(SDRAM_RFDC, rfdc_reg | SDRAM_RFDC_RFFD_ENCODE(rffd_average));
599
600 /* if something passed, then return the size of the largest window */
601 if (passed != 0) {
602 passed = loop_win_max.rffd - loop_win_min.rffd;
603 cal->rqfd = rqfd_average;
604 cal->rffd = rffd_average;
605 cal->rffd_min = loop_win_min.rffd;
606 cal->rffd_max = loop_win_max.rffd;
607 }
608
609 return (u32)passed;
610 }
611
612 #else /* !defined(CONFIG_PPC4xx_DDR_METHOD_A) */
613
614 /*-----------------------------------------------------------------------------+
615 | program_DQS_calibration_methodB.
616 +-----------------------------------------------------------------------------*/
617 static u32 program_DQS_calibration_methodB(struct ddrautocal *ddrcal)
618 {
619 u32 pass_result = 0;
620
621 #ifdef DEBUG
622 ulong temp;
623 #endif
624
625 /*
626 * Program RDCC register
627 * Read sample cycle auto-update enable
628 */
629 mtsdram(SDRAM_RDCC,
630 ddr_rdss_opt(SDRAM_RDCC_RDSS_T2) | SDRAM_RDCC_RSAE_ENABLE);
631
632 #ifdef DEBUG
633 mfsdram(SDRAM_RDCC, temp);
634 debug("<%s>SDRAM_RDCC=0x%08x\n", __func__, temp);
635 #endif
636
637 /*
638 * Program RQDC register
639 * Internal DQS delay mechanism enable
640 */
641 mtsdram(SDRAM_RQDC,
642 #if defined(CONFIG_DDR_RQDC_START_VAL)
643 SDRAM_RQDC_RQDE_ENABLE |
644 SDRAM_RQDC_RQFD_ENCODE(CONFIG_DDR_RQDC_START_VAL));
645 #else
646 SDRAM_RQDC_RQDE_ENABLE | SDRAM_RQDC_RQFD_ENCODE(0x38));
647 #endif
648
649 #ifdef DEBUG
650 mfsdram(SDRAM_RQDC, temp);
651 debug("<%s>SDRAM_RQDC=0x%08x\n", __func__, temp);
652 #endif
653
654 /*
655 * Program RFDC register
656 * Set Feedback Fractional Oversample
657 * Auto-detect read sample cycle enable
658 */
659 mtsdram(SDRAM_RFDC, SDRAM_RFDC_ARSE_ENABLE |
660 SDRAM_RFDC_RFOS_ENCODE(0) |
661 SDRAM_RFDC_RFFD_ENCODE(0));
662
663 #ifdef DEBUG
664 mfsdram(SDRAM_RFDC, temp);
665 debug("<%s>SDRAM_RFDC=0x%08x\n", __func__, temp);
666 #endif
667
668 pass_result = DQS_calibration_methodB(ddrcal);
669
670 return pass_result;
671 }
672
673 /*
674 * DQS_calibration_methodB()
675 *
676 * Autocalibration Method B
677 *
678 * ARRAY [Entire DQS Range] DQS_Valid_Window ; initialized to all zeros
679 * ARRAY [Entire Feedback Range] FDBK_Valid_Window; initialized to all zeros
680 * MEMWRITE(addr, expected_data);
681 * Initialialize the DQS delay to 80 degrees (MCIF0_RRQDC[RQFD]=0x38).
682 *
683 * for (j = 0; j < Entire Feedback Range; j++) {
684 * MEMREAD(addr, actual_data);
685 * if (actual_data == expected_data) {
686 * FDBK_Valid_Window[j] = 1;
687 * }
688 * }
689 *
690 * Set MCIF0_RFDC[RFFD] to the middle of the FDBK_Valid_Window.
691 *
692 * for (i = 0; i < Entire DQS Range; i++) {
693 * MEMREAD(addr, actual_data);
694 * if (actual_data == expected_data) {
695 * DQS_Valid_Window[i] = 1;
696 * }
697 * }
698 *
699 * Set MCIF0_RRQDC[RQFD] to the middle of the DQS_Valid_Window.
700 */
701 /*-----------------------------------------------------------------------------+
702 | DQS_calibration_methodB.
703 +-----------------------------------------------------------------------------*/
704 static u32 DQS_calibration_methodB(struct ddrautocal *cal)
705 {
706 ulong rfdc_reg;
707 #ifndef CONFIG_DDR_RFDC_FIXED
708 ulong rffd;
709 #endif
710
711 ulong rqdc_reg;
712 ulong rqfd;
713
714 ulong rdcc;
715
716 u32 *membase;
717 ulong bxcf;
718 int rqfd_average;
719 int bxcr_num;
720 int rffd_average;
721 int pass;
722 uint passed = 0;
723
724 int in_window;
725 u32 curr_win_min, curr_win_max;
726 u32 best_win_min, best_win_max;
727 u32 size = 0;
728
729 /*------------------------------------------------------------------
730 | Test to determine the best read clock delay tuning bits.
731 |
732 | Before the DDR controller can be used, the read clock delay needs to
733 | be set. This is SDRAM_RQDC[RQFD] and SDRAM_RFDC[RFFD].
734 | This value cannot be hardcoded into the program because it changes
735 | depending on the board's setup and environment.
736 | To do this, all delay values are tested to see if they
737 | work or not. By doing this, you get groups of fails with groups of
738 | passing values. The idea is to find the start and end of a passing
739 | window and take the center of it to use as the read clock delay.
740 |
741 | A failure has to be seen first so that when we hit a pass, we know
742 | that it is truely the start of the window. If we get passing values
743 | to start off with, we don't know if we are at the start of the window
744 |
745 | The code assumes that a failure will always be found.
746 | If a failure is not found, there is no easy way to get the middle
747 | of the passing window. I guess we can pretty much pick any value
748 | but some values will be better than others. Since the lowest speed
749 | we can clock the DDR interface at is 200 MHz (2x 100 MHz PLB speed),
750 | from experimentation it is safe to say you will always have a failure
751 +-----------------------------------------------------------------*/
752
753 debug("\n\n");
754
755 #if defined(CONFIG_DDR_RFDC_FIXED)
756 mtsdram(SDRAM_RFDC, CONFIG_DDR_RFDC_FIXED);
757 size = 512;
758 rffd_average = CONFIG_DDR_RFDC_FIXED & SDRAM_RFDC_RFFD_MASK;
759 mfsdram(SDRAM_RDCC, rdcc); /* record this value */
760 cal->rdcc = rdcc;
761 #else /* CONFIG_DDR_RFDC_FIXED */
762 in_window = 0;
763 rdcc = 0;
764
765 curr_win_min = curr_win_max = 0;
766 best_win_min = best_win_max = 0;
767 for (rffd = 0; rffd <= SDRAM_RFDC_RFFD_MAX; rffd++) {
768 mfsdram(SDRAM_RFDC, rfdc_reg);
769 rfdc_reg &= ~(SDRAM_RFDC_RFFD_MASK);
770 mtsdram(SDRAM_RFDC, rfdc_reg | SDRAM_RFDC_RFFD_ENCODE(rffd));
771
772 pass = 1;
773 for (bxcr_num = 0; bxcr_num < MAXBXCF; bxcr_num++) {
774 mfsdram(SDRAM_MB0CF + (bxcr_num<<2), bxcf);
775
776 /* Banks enabled */
777 if (bxcf & SDRAM_BXCF_M_BE_MASK) {
778 /* Bank is enabled */
779 membase = get_membase(bxcr_num);
780 pass &= short_mem_test(membase);
781 } /* if bank enabled */
782 } /* for bxcf_num */
783
784 /* If this value passed */
785 if (pass && !in_window) { /* start of passing window */
786 in_window = 1;
787 curr_win_min = curr_win_max = rffd;
788 mfsdram(SDRAM_RDCC, rdcc); /* record this value */
789 } else if (!pass && in_window) { /* end passing window */
790 in_window = 0;
791 } else if (pass && in_window) { /* within the passing window */
792 curr_win_max = rffd;
793 }
794
795 if (in_window) {
796 if ((curr_win_max - curr_win_min) >
797 (best_win_max - best_win_min)) {
798 best_win_min = curr_win_min;
799 best_win_max = curr_win_max;
800 cal->rdcc = rdcc;
801 }
802 passed = 1;
803 }
804 } /* for rffd */
805
806 if ((best_win_min == 0) && (best_win_max == 0))
807 passed = 0;
808 else
809 size = best_win_max - best_win_min;
810
811 debug("RFFD Min: 0x%x\n", best_win_min);
812 debug("RFFD Max: 0x%x\n", best_win_max);
813 rffd_average = ((best_win_min + best_win_max) / 2);
814
815 cal->rffd_min = best_win_min;
816 cal->rffd_max = best_win_max;
817
818 if (rffd_average < 0)
819 rffd_average = 0;
820
821 if (rffd_average > SDRAM_RFDC_RFFD_MAX)
822 rffd_average = SDRAM_RFDC_RFFD_MAX;
823
824 mtsdram(SDRAM_RFDC, rfdc_reg | SDRAM_RFDC_RFFD_ENCODE(rffd_average));
825 #endif /* CONFIG_DDR_RFDC_FIXED */
826
827 in_window = 0;
828
829 curr_win_min = curr_win_max = 0;
830 best_win_min = best_win_max = 0;
831 for (rqfd = 0; rqfd <= SDRAM_RQDC_RQFD_MAX; rqfd++) {
832 mfsdram(SDRAM_RQDC, rqdc_reg);
833 rqdc_reg &= ~(SDRAM_RQDC_RQFD_MASK);
834 mtsdram(SDRAM_RQDC, rqdc_reg | SDRAM_RQDC_RQFD_ENCODE(rqfd));
835
836 pass = 1;
837 for (bxcr_num = 0; bxcr_num < MAXBXCF; bxcr_num++) {
838
839 mfsdram(SDRAM_MB0CF + (bxcr_num<<2), bxcf);
840
841 /* Banks enabled */
842 if (bxcf & SDRAM_BXCF_M_BE_MASK) {
843 /* Bank is enabled */
844 membase = get_membase(bxcr_num);
845 pass &= short_mem_test(membase);
846 } /* if bank enabled */
847 } /* for bxcf_num */
848
849 /* If this value passed */
850 if (pass && !in_window) {
851 in_window = 1;
852 curr_win_min = curr_win_max = rqfd;
853 } else if (!pass && in_window) {
854 in_window = 0;
855 } else if (pass && in_window) {
856 curr_win_max = rqfd;
857 }
858
859 if (in_window) {
860 if ((curr_win_max - curr_win_min) >
861 (best_win_max - best_win_min)) {
862 best_win_min = curr_win_min;
863 best_win_max = curr_win_max;
864 }
865 passed = 1;
866 }
867 } /* for rqfd */
868
869 if ((best_win_min == 0) && (best_win_max == 0))
870 passed = 0;
871
872 debug("RQFD Min: 0x%x\n", best_win_min);
873 debug("RQFD Max: 0x%x\n", best_win_max);
874 rqfd_average = ((best_win_min + best_win_max) / 2);
875
876 if (rqfd_average < 0)
877 rqfd_average = 0;
878
879 if (rqfd_average > SDRAM_RQDC_RQFD_MAX)
880 rqfd_average = SDRAM_RQDC_RQFD_MAX;
881
882 mtsdram(SDRAM_RQDC, (rqdc_reg & ~SDRAM_RQDC_RQFD_MASK) |
883 SDRAM_RQDC_RQFD_ENCODE(rqfd_average));
884
885 mfsdram(SDRAM_RQDC, rqdc_reg);
886 mfsdram(SDRAM_RFDC, rfdc_reg);
887
888 /*
889 * Need to program RQDC before RFDC. The value is read above.
890 * That is the reason why auto cal not work.
891 * See, comments below.
892 */
893 mtsdram(SDRAM_RQDC, rqdc_reg);
894 mtsdram(SDRAM_RFDC, rfdc_reg);
895
896 debug("RQDC: 0x%08lX\n", rqdc_reg);
897 debug("RFDC: 0x%08lX\n", rfdc_reg);
898
899 /* if something passed, then return the size of the largest window */
900 if (passed != 0) {
901 passed = size;
902 cal->rqfd = rqfd_average;
903 cal->rffd = rffd_average;
904 }
905
906 return (uint)passed;
907 }
908 #endif /* defined(CONFIG_PPC4xx_DDR_METHOD_A) */
909
910 /*
911 * Default table for DDR auto-calibration of all
912 * possible WRDTR and CLKTR values.
913 * Table format is:
914 * {SDRAM_WRDTR.[WDTR], SDRAM_CLKTR.[CKTR]}
915 *
916 * Table is terminated with {-1, -1} value pair.
917 *
918 * Board vendors can specify their own board specific subset of
919 * known working {SDRAM_WRDTR.[WDTR], SDRAM_CLKTR.[CKTR]} value
920 * pairs via a board defined ddr_scan_option() function.
921 */
922 static struct sdram_timing full_scan_options[] = {
923 {0, 0}, {0, 1}, {0, 2}, {0, 3},
924 {1, 0}, {1, 1}, {1, 2}, {1, 3},
925 {2, 0}, {2, 1}, {2, 2}, {2, 3},
926 {3, 0}, {3, 1}, {3, 2}, {3, 3},
927 {4, 0}, {4, 1}, {4, 2}, {4, 3},
928 {5, 0}, {5, 1}, {5, 2}, {5, 3},
929 {6, 0}, {6, 1}, {6, 2}, {6, 3},
930 {-1, -1}
931 };
932
933 /*---------------------------------------------------------------------------+
934 | DQS_calibration.
935 +----------------------------------------------------------------------------*/
936 u32 DQS_autocalibration(void)
937 {
938 u32 wdtr;
939 u32 clkp;
940 u32 result = 0;
941 u32 best_result = 0;
942 u32 best_rdcc;
943 struct ddrautocal ddrcal;
944 struct autocal_clks tcal;
945 ulong rfdc_reg;
946 ulong rqdc_reg;
947 u32 val;
948 int verbose_lvl = 0;
949 char *str;
950 char slash[] = "\\|/-\\|/-";
951 int loopi = 0;
952 struct sdram_timing *scan_list;
953
954 #if defined(DEBUG_PPC4xx_DDR_AUTOCALIBRATION)
955 int i;
956 char tmp[64]; /* long enough for environment variables */
957 #endif
958
959 memset(&tcal, 0, sizeof(tcal));
960
961 scan_list = ddr_scan_option(full_scan_options);
962
963 mfsdram(SDRAM_MCOPT1, val);
964 if ((val & SDRAM_MCOPT1_MCHK_CHK_REP) == SDRAM_MCOPT1_MCHK_CHK_REP)
965 str = "ECC Auto calibration -";
966 else
967 str = "Auto calibration -";
968
969 puts(str);
970
971 #if defined(DEBUG_PPC4xx_DDR_AUTOCALIBRATION)
972 i = getenv_f("autocalib", tmp, sizeof(tmp));
973 if (i < 0)
974 strcpy(tmp, CONFIG_AUTOCALIB);
975
976 if (strcmp(tmp, "final") == 0) {
977 /* display the final autocalibration results only */
978 verbose_lvl = 1;
979 } else if (strcmp(tmp, "loop") == 0) {
980 /* display summary autocalibration info per iteration */
981 verbose_lvl = 2;
982 } else if (strcmp(tmp, "display") == 0) {
983 /* display full debug autocalibration window info. */
984 verbose_lvl = 3;
985 }
986 #endif /* (DEBUG_PPC4xx_DDR_AUTOCALIBRATION) */
987
988 best_rdcc = (SDRAM_RDCC_RDSS_T4 >> 30);
989
990 while ((scan_list->wrdtr != -1) && (scan_list->clktr != -1)) {
991 wdtr = scan_list->wrdtr;
992 clkp = scan_list->clktr;
993
994 mfsdram(SDRAM_WRDTR, val);
995 val &= ~(SDRAM_WRDTR_LLWP_MASK | SDRAM_WRDTR_WTR_MASK);
996 mtsdram(SDRAM_WRDTR, (val |
997 ddr_wrdtr(SDRAM_WRDTR_LLWP_1_CYC | (wdtr << 25))));
998
999 mtsdram(SDRAM_CLKTR, clkp << 30);
1000
1001 relock_memory_DLL();
1002
1003 putc('\b');
1004 putc(slash[loopi++ % 8]);
1005
1006 #ifdef DEBUG
1007 debug("\n");
1008 debug("*** --------------\n");
1009 mfsdram(SDRAM_WRDTR, val);
1010 debug("*** SDRAM_WRDTR set to 0x%08x\n", val);
1011 mfsdram(SDRAM_CLKTR, val);
1012 debug("*** SDRAM_CLKTR set to 0x%08x\n", val);
1013 #endif
1014
1015 debug("\n");
1016 if (verbose_lvl > 2) {
1017 printf("*** SDRAM_WRDTR (wdtr) set to %d\n", wdtr);
1018 printf("*** SDRAM_CLKTR (clkp) set to %d\n", clkp);
1019 }
1020
1021 memset(&ddrcal, 0, sizeof(ddrcal));
1022
1023 /*
1024 * DQS calibration.
1025 */
1026 /*
1027 * program_DQS_calibration_method[A|B]() returns 0 if no
1028 * passing RFDC.[RFFD] window is found or returns the size
1029 * of the best passing window; in the case of a found passing
1030 * window, the ddrcal will contain the values of the best
1031 * window RQDC.[RQFD] and RFDC.[RFFD].
1032 */
1033
1034 /*
1035 * Call PPC4xx SDRAM DDR autocalibration methodA or methodB.
1036 * Default is methodB.
1037 * Defined the autocalibration method in the board specific
1038 * header file.
1039 * Please see include/configs/kilauea.h for an example for
1040 * a board specific implementation.
1041 */
1042 #if defined(CONFIG_PPC4xx_DDR_METHOD_A)
1043 result = program_DQS_calibration_methodA(&ddrcal);
1044 #else
1045 result = program_DQS_calibration_methodB(&ddrcal);
1046 #endif
1047
1048 sync();
1049
1050 /*
1051 * Clear potential errors resulting from auto-calibration.
1052 * If not done, then we could get an interrupt later on when
1053 * exceptions are enabled.
1054 */
1055 set_mcsr(get_mcsr());
1056
1057 val = ddrcal.rdcc; /* RDCC from the best passing window */
1058
1059 udelay(100);
1060
1061 if (verbose_lvl > 1) {
1062 char *tstr;
1063 switch ((val >> 30)) {
1064 case 0:
1065 if (result != 0)
1066 tstr = "T1";
1067 else
1068 tstr = "N/A";
1069 break;
1070 case 1:
1071 tstr = "T2";
1072 break;
1073 case 2:
1074 tstr = "T3";
1075 break;
1076 case 3:
1077 tstr = "T4";
1078 break;
1079 default:
1080 tstr = "unknown";
1081 break;
1082 }
1083 printf("** WRDTR(%d) CLKTR(%d), Wind (%d), best (%d), "
1084 "max-min(0x%04x)(0x%04x), RDCC: %s\n",
1085 wdtr, clkp, result, best_result,
1086 ddrcal.rffd_min, ddrcal.rffd_max, tstr);
1087 }
1088
1089 /*
1090 * The DQS calibration "result" is either "0"
1091 * if no passing window was found, or is the
1092 * size of the RFFD passing window.
1093 */
1094 /*
1095 * want the lowest Read Sample Cycle Select
1096 */
1097 val = SDRAM_RDCC_RDSS_DECODE(val);
1098 debug("*** (%d) (%d) current_rdcc, best_rdcc\n",
1099 val, best_rdcc);
1100
1101 if ((result != 0) &&
1102 (val >= SDRAM_RDCC_RDSS_VAL(SDRAM_RDCC_RDSS_T2))) {
1103 if (((result == best_result) && (val < best_rdcc)) ||
1104 ((result > best_result) && (val <= best_rdcc))) {
1105 tcal.autocal.flags = 1;
1106 debug("*** (%d)(%d) result passed window "
1107 "size: 0x%08x, rqfd = 0x%08x, "
1108 "rffd = 0x%08x, rdcc = 0x%08x\n",
1109 wdtr, clkp, result, ddrcal.rqfd,
1110 ddrcal.rffd, ddrcal.rdcc);
1111
1112 /*
1113 * Save the SDRAM_WRDTR and SDRAM_CLKTR
1114 * settings for the largest returned
1115 * RFFD passing window size.
1116 */
1117 best_rdcc = val;
1118 tcal.clocks.wrdtr = wdtr;
1119 tcal.clocks.clktr = clkp;
1120 tcal.clocks.rdcc = SDRAM_RDCC_RDSS_ENCODE(val);
1121 tcal.autocal.rqfd = ddrcal.rqfd;
1122 tcal.autocal.rffd = ddrcal.rffd;
1123 best_result = result;
1124
1125 if (verbose_lvl > 2) {
1126 printf("** (%d)(%d) "
1127 "best result: 0x%04x\n",
1128 wdtr, clkp,
1129 best_result);
1130 printf("** (%d)(%d) "
1131 "best WRDTR: 0x%04x\n",
1132 wdtr, clkp,
1133 tcal.clocks.wrdtr);
1134 printf("** (%d)(%d) "
1135 "best CLKTR: 0x%04x\n",
1136 wdtr, clkp,
1137 tcal.clocks.clktr);
1138 printf("** (%d)(%d) "
1139 "best RQDC: 0x%04x\n",
1140 wdtr, clkp,
1141 tcal.autocal.rqfd);
1142 printf("** (%d)(%d) "
1143 "best RFDC: 0x%04x\n",
1144 wdtr, clkp,
1145 tcal.autocal.rffd);
1146 printf("** (%d)(%d) "
1147 "best RDCC: 0x%08x\n",
1148 wdtr, clkp,
1149 (u32)tcal.clocks.rdcc);
1150 mfsdram(SDRAM_RTSR, val);
1151 printf("** (%d)(%d) best "
1152 "loop RTSR: 0x%08x\n",
1153 wdtr, clkp, val);
1154 mfsdram(SDRAM_FCSR, val);
1155 printf("** (%d)(%d) best "
1156 "loop FCSR: 0x%08x\n",
1157 wdtr, clkp, val);
1158 }
1159 }
1160 } /* if ((result != 0) && (val >= (ddr_rdss_opt()))) */
1161 scan_list++;
1162 } /* while ((scan_list->wrdtr != -1) && (scan_list->clktr != -1)) */
1163
1164 if (tcal.autocal.flags == 1) {
1165 if (verbose_lvl > 0) {
1166 printf("*** --------------\n");
1167 printf("*** best_result window size: %d\n",
1168 best_result);
1169 printf("*** best_result WRDTR: 0x%04x\n",
1170 tcal.clocks.wrdtr);
1171 printf("*** best_result CLKTR: 0x%04x\n",
1172 tcal.clocks.clktr);
1173 printf("*** best_result RQFD: 0x%04x\n",
1174 tcal.autocal.rqfd);
1175 printf("*** best_result RFFD: 0x%04x\n",
1176 tcal.autocal.rffd);
1177 printf("*** best_result RDCC: 0x%04x\n",
1178 tcal.clocks.rdcc);
1179 printf("*** --------------\n");
1180 printf("\n");
1181 }
1182
1183 /*
1184 * if got best passing result window, then lock in the
1185 * best CLKTR, WRDTR, RQFD, and RFFD values
1186 */
1187 mfsdram(SDRAM_WRDTR, val);
1188 mtsdram(SDRAM_WRDTR, (val &
1189 ~(SDRAM_WRDTR_LLWP_MASK | SDRAM_WRDTR_WTR_MASK)) |
1190 ddr_wrdtr(SDRAM_WRDTR_LLWP_1_CYC |
1191 (tcal.clocks.wrdtr << 25)));
1192
1193 mtsdram(SDRAM_CLKTR, tcal.clocks.clktr << 30);
1194
1195 relock_memory_DLL();
1196
1197 mfsdram(SDRAM_RQDC, rqdc_reg);
1198 rqdc_reg &= ~(SDRAM_RQDC_RQFD_MASK);
1199 mtsdram(SDRAM_RQDC, rqdc_reg |
1200 SDRAM_RQDC_RQFD_ENCODE(tcal.autocal.rqfd));
1201
1202 mfsdram(SDRAM_RQDC, rqdc_reg);
1203 debug("*** best_result: read value SDRAM_RQDC 0x%08lx\n",
1204 rqdc_reg);
1205
1206 #if defined(CONFIG_DDR_RFDC_FIXED)
1207 mtsdram(SDRAM_RFDC, CONFIG_DDR_RFDC_FIXED);
1208 #else /* CONFIG_DDR_RFDC_FIXED */
1209 mfsdram(SDRAM_RFDC, rfdc_reg);
1210 rfdc_reg &= ~(SDRAM_RFDC_RFFD_MASK);
1211 mtsdram(SDRAM_RFDC, rfdc_reg |
1212 SDRAM_RFDC_RFFD_ENCODE(tcal.autocal.rffd));
1213 #endif /* CONFIG_DDR_RFDC_FIXED */
1214
1215 mfsdram(SDRAM_RFDC, rfdc_reg);
1216 debug("*** best_result: read value SDRAM_RFDC 0x%08lx\n",
1217 rfdc_reg);
1218 mfsdram(SDRAM_RDCC, val);
1219 debug("*** SDRAM_RDCC 0x%08x\n", val);
1220 } else {
1221 /*
1222 * no valid windows were found
1223 */
1224 printf("DQS memory calibration window can not be determined, "
1225 "terminating u-boot.\n");
1226 ppc4xx_ibm_ddr2_register_dump();
1227 spd_ddr_init_hang();
1228 }
1229
1230 blank_string(strlen(str));
1231
1232 return 0;
1233 }
1234 #else /* defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL) */
1235 u32 DQS_autocalibration(void)
1236 {
1237 return 0;
1238 }
1239 #endif /* !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL) */
"Das U-Boot" Source Tree