2 * SPDX-License-Identifier: GPL-2.0 IBM-pibs
4 * File Name: 405gp_pci.c
6 * Function: Initialization code for the 405GP PCI Configuration regs.
12 * Date Description of Change BY
13 * --------- --------------------- ---
14 * 09-Sep-98 Created MCG
15 * 02-Nov-98 Removed External arbiter selected message JWB
16 * 27-Nov-98 Zero out PTMBAR2 and disable in PTM2MS JWB
17 * 04-Jan-99 Zero out other unused PMM and PTM regs. Change bus scan MCG
18 * from (0 to n) to (1 to n).
19 * 17-May-99 Port to Walnut JWB
20 * 17-Jun-99 Updated for VGA support JWB
21 * 21-Jun-99 Updated to allow SRAM region to be a target from PCI bus JWB
22 * 19-Jul-99 Updated for 405GP pass 1 errata #26 (Low PCI subsequent MCG
23 * target latency timer values are not supported).
24 * Should be fixed in pass 2.
25 * 09-Sep-99 Removed use of PTM2 since the SRAM region no longer needs JWB
26 * to be a PCI target. Zero out PTMBAR2 and disable in PTM2MS.
27 * 10-Dec-99 Updated PCI_Write_CFG_Reg for pass2 errata #6 JWB
28 * 11-Jan-00 Ensure PMMxMAs disabled before setting PMMxLAs. This is not
29 * really required after a reset since PMMxMAs are already
30 * disabled but is a good practice nonetheless. JWB
31 * 12-Jun-01 stefan.roese@esd-electronics.com
32 * - PCI host/adapter handling reworked
33 * 09-Jul-01 stefan.roese@esd-electronics.com
34 * - PCI host now configures from device 0 (not 1) to max_dev,
35 * (host configures itself)
36 * - On CPCI-405 pci base address and size is generated from
37 * SDRAM and FLASH size (CFG regs not used anymore)
38 * - Some minor changes for CPCI-405-A (adapter version)
39 * 14-Sep-01 stefan.roese@esd-electronics.com
40 * - CONFIG_PCI_SCAN_SHOW added to print pci devices upon startup
41 * 28-Sep-01 stefan.roese@esd-electronics.com
42 * - Changed pci master configuration for linux compatibility
43 * (no need for bios_fixup() anymore)
44 * 26-Feb-02 stefan.roese@esd-electronics.com
45 * - Bug fixed in pci configuration (Andrew May)
46 * - Removed pci class code init for CPCI405 board
47 * 15-May-02 stefan.roese@esd-electronics.com
48 * - New vga device handling
49 * 29-May-02 stefan.roese@esd-electronics.com
50 * - PCI class code init added (if defined)
51 *----------------------------------------------------------------------------*/
55 #include <asm/4xx_pci.h>
56 #include <asm/processor.h>
62 DECLARE_GLOBAL_DATA_PTR
;
64 #if defined(CONFIG_405GP) || defined(CONFIG_405EP)
69 * Board-specific pci initialization
70 * Platform code can reimplement pci_pre_init() if needed
72 int __pci_pre_init(struct pci_controller
*hose
)
74 #if defined(CONFIG_405EP)
76 * Enable the internal PCI arbiter by default.
78 * On 405EP CPUs the internal arbiter can be controlled
79 * by the I2C strapping EEPROM. If you want to do so
80 * or if you want to disable the arbiter pci_pre_init()
81 * must be reimplemented without enabling the arbiter.
82 * The arbiter is enabled in this place because of
83 * compatibility reasons.
85 mtdcr(CPC0_PCI
, mfdcr(CPC0_PCI
) | CPC0_PCI_ARBIT_EN
);
86 #endif /* CONFIG_405EP */
90 int pci_pre_init(struct pci_controller
*hose
)
91 __attribute__((weak
, alias("__pci_pre_init")));
93 int __is_pci_host(struct pci_controller
*hose
)
95 #if defined(CONFIG_405GP)
96 if (mfdcr(CPC0_PSR
) & PSR_PCI_ARBIT_EN
)
98 #elif defined (CONFIG_405EP)
99 if (mfdcr(CPC0_PCI
) & CPC0_PCI_ARBIT_EN
)
104 int is_pci_host(struct pci_controller
*hose
) __attribute__((weak
, alias("__is_pci_host")));
106 /*-----------------------------------------------------------------------------+
107 * pci_init. Initializes the 405GP PCI Configuration regs.
108 *-----------------------------------------------------------------------------*/
109 void pci_405gp_init(struct pci_controller
*hose
)
114 unsigned short temp_short
;
115 unsigned long ptmpcila
[2] = {CONFIG_SYS_PCI_PTM1PCI
, CONFIG_SYS_PCI_PTM2PCI
};
116 #if defined(CONFIG_PCI_4xx_PTM_OVERWRITE)
117 char *ptmla_str
, *ptmms_str
;
119 unsigned long ptmla
[2] = {CONFIG_SYS_PCI_PTM1LA
, CONFIG_SYS_PCI_PTM2LA
};
120 unsigned long ptmms
[2] = {CONFIG_SYS_PCI_PTM1MS
, CONFIG_SYS_PCI_PTM2MS
};
121 #if defined(CONFIG_PIP405) || defined (CONFIG_MIP405)
122 unsigned long pmmla
[3] = {0x80000000, 0xA0000000, 0};
123 unsigned long pmmma
[3] = {0xE0000001, 0xE0000001, 0};
124 unsigned long pmmpcila
[3] = {0x80000000, 0x00000000, 0};
125 unsigned long pmmpciha
[3] = {0x00000000, 0x00000000, 0};
127 unsigned long pmmla
[3] = {0x80000000, 0,0};
128 unsigned long pmmma
[3] = {0xC0000001, 0,0};
129 unsigned long pmmpcila
[3] = {0x80000000, 0,0};
130 unsigned long pmmpciha
[3] = {0x00000000, 0,0};
132 #ifdef CONFIG_PCI_PNP
133 #if (CONFIG_PCI_HOST == PCI_HOST_AUTO)
138 #if defined(CONFIG_PCI_4xx_PTM_OVERWRITE)
139 ptmla_str
= getenv("ptm1la");
140 ptmms_str
= getenv("ptm1ms");
141 if(NULL
!= ptmla_str
&& NULL
!= ptmms_str
) {
142 ptmla
[0] = simple_strtoul (ptmla_str
, NULL
, 16);
143 ptmms
[0] = simple_strtoul (ptmms_str
, NULL
, 16);
146 ptmla_str
= getenv("ptm2la");
147 ptmms_str
= getenv("ptm2ms");
148 if(NULL
!= ptmla_str
&& NULL
!= ptmms_str
) {
149 ptmla
[1] = simple_strtoul (ptmla_str
, NULL
, 16);
150 ptmms
[1] = simple_strtoul (ptmms_str
, NULL
, 16);
157 hose
->first_busno
= 0;
158 hose
->last_busno
= 0xff;
160 /* ISA/PCI I/O space */
161 pci_set_region(hose
->regions
+ reg_num
++,
168 pci_set_region(hose
->regions
+ reg_num
++,
180 if (!i
) hose
->pci_fb
= hose
->regions
+ reg_num
;
182 pci_set_region(hose
->regions
+ reg_num
++,
183 ptmpcila
[i
], ptmla
[i
],
184 ~(ptmms
[i
] & 0xfffff000) + 1,
186 PCI_REGION_SYS_MEMORY
);
189 /* PCI memory spaces */
193 pci_set_region(hose
->regions
+ reg_num
++,
194 pmmpcila
[i
], pmmla
[i
],
195 ~(pmmma
[i
] & 0xfffff000) + 1,
199 hose
->region_count
= reg_num
;
201 pci_setup_indirect(hose
,
206 pciauto_region_init(hose
->pci_fb
);
208 /* Let board change/modify hose & do initial checks */
209 if (pci_pre_init(hose
) == 0) {
210 printf("PCI: Board-specific initialization failed.\n");
211 printf("PCI: Configuration aborted.\n");
215 pci_register_hose(hose
);
217 /*--------------------------------------------------------------------------+
218 * 405GP PCI Master configuration.
219 * Map one 512 MB range of PLB/processor addresses to PCI memory space.
220 * PLB address 0x80000000-0xBFFFFFFF ==> PCI address 0x80000000-0xBFFFFFFF
221 * Use byte reversed out routines to handle endianess.
222 *--------------------------------------------------------------------------*/
223 out32r(PMM0MA
, (pmmma
[0]&~0x1)); /* disable, configure PMMxLA, PMMxPCILA first */
224 out32r(PMM0LA
, pmmla
[0]);
225 out32r(PMM0PCILA
, pmmpcila
[0]);
226 out32r(PMM0PCIHA
, pmmpciha
[0]);
227 out32r(PMM0MA
, pmmma
[0]);
229 /*--------------------------------------------------------------------------+
230 * PMM1 is not used. Initialize them to zero.
231 *--------------------------------------------------------------------------*/
232 out32r(PMM1MA
, (pmmma
[1]&~0x1));
233 out32r(PMM1LA
, pmmla
[1]);
234 out32r(PMM1PCILA
, pmmpcila
[1]);
235 out32r(PMM1PCIHA
, pmmpciha
[1]);
236 out32r(PMM1MA
, pmmma
[1]);
238 /*--------------------------------------------------------------------------+
239 * PMM2 is not used. Initialize them to zero.
240 *--------------------------------------------------------------------------*/
241 out32r(PMM2MA
, (pmmma
[2]&~0x1));
242 out32r(PMM2LA
, pmmla
[2]);
243 out32r(PMM2PCILA
, pmmpcila
[2]);
244 out32r(PMM2PCIHA
, pmmpciha
[2]);
245 out32r(PMM2MA
, pmmma
[2]);
247 /*--------------------------------------------------------------------------+
248 * 405GP PCI Target configuration. (PTM1)
249 * Note: PTM1MS is hardwire enabled but we set the enable bit anyway.
250 *--------------------------------------------------------------------------*/
251 out32r(PTM1LA
, ptmla
[0]); /* insert address */
252 out32r(PTM1MS
, ptmms
[0]); /* insert size, enable bit is 1 */
253 pci_write_config_dword(PCIDEVID_405GP
, PCI_BASE_ADDRESS_1
, ptmpcila
[0]);
255 /*--------------------------------------------------------------------------+
256 * 405GP PCI Target configuration. (PTM2)
257 *--------------------------------------------------------------------------*/
258 out32r(PTM2LA
, ptmla
[1]); /* insert address */
259 pci_write_config_dword(PCIDEVID_405GP
, PCI_BASE_ADDRESS_2
, ptmpcila
[1]);
263 out32r(PTM2MS
, 0x00000001); /* set enable bit */
264 pci_write_config_dword(PCIDEVID_405GP
, PCI_BASE_ADDRESS_2
, 0x00000000);
265 out32r(PTM2MS
, 0x00000000); /* disable */
269 out32r(PTM2MS
, ptmms
[1]); /* insert size, enable bit is 1 */
273 * Insert Subsystem Vendor and Device ID
275 pci_write_config_word(PCIDEVID_405GP
, PCI_SUBSYSTEM_VENDOR_ID
, CONFIG_SYS_PCI_SUBSYS_VENDORID
);
276 #ifdef CONFIG_CPCI405
277 if (is_pci_host(hose
))
278 pci_write_config_word(PCIDEVID_405GP
, PCI_SUBSYSTEM_ID
, CONFIG_SYS_PCI_SUBSYS_DEVICEID
);
280 pci_write_config_word(PCIDEVID_405GP
, PCI_SUBSYSTEM_ID
, CONFIG_SYS_PCI_SUBSYS_DEVICEID2
);
282 pci_write_config_word(PCIDEVID_405GP
, PCI_SUBSYSTEM_ID
, CONFIG_SYS_PCI_SUBSYS_DEVICEID
);
288 #ifdef CONFIG_SYS_PCI_CLASSCODE
289 pci_write_config_word(PCIDEVID_405GP
, PCI_CLASS_SUB_CODE
, CONFIG_SYS_PCI_CLASSCODE
);
290 #endif /* CONFIG_SYS_PCI_CLASSCODE */
292 /*--------------------------------------------------------------------------+
293 * If PCI speed = 66MHz, set 66MHz capable bit.
294 *--------------------------------------------------------------------------*/
295 if (bd
->bi_pci_busfreq
>= 66000000) {
296 pci_read_config_word(PCIDEVID_405GP
, PCI_STATUS
, &temp_short
);
297 pci_write_config_word(PCIDEVID_405GP
,PCI_STATUS
,(temp_short
|PCI_STATUS_66MHZ
));
300 #if (CONFIG_PCI_HOST != PCI_HOST_ADAPTER)
301 #if (CONFIG_PCI_HOST == PCI_HOST_AUTO)
302 if (is_pci_host(hose
) ||
303 (((s
= getenv("pciscan")) != NULL
) && (strcmp(s
, "yes") == 0)))
306 /*--------------------------------------------------------------------------+
307 * Write the 405GP PCI Configuration regs.
308 * Enable 405GP to be a master on the PCI bus (PMM).
309 * Enable 405GP to act as a PCI memory target (PTM).
310 *--------------------------------------------------------------------------*/
311 pci_read_config_word(PCIDEVID_405GP
, PCI_COMMAND
, &temp_short
);
312 pci_write_config_word(PCIDEVID_405GP
, PCI_COMMAND
, temp_short
|
313 PCI_COMMAND_MASTER
| PCI_COMMAND_MEMORY
);
317 #if defined(CONFIG_405EP)
319 * on ppc405ep vendor/device id is not set
320 * The user manual says 0x1014 (IBM) / 0x0156 (405GP!)
321 * are the correct values.
323 pci_write_config_word(PCIDEVID_405GP
, PCI_VENDOR_ID
, PCI_VENDOR_ID_IBM
);
324 pci_write_config_word(PCIDEVID_405GP
,
325 PCI_DEVICE_ID
, PCI_DEVICE_ID_IBM_405GP
);
329 * Set HCE bit (Host Configuration Enabled)
331 pci_read_config_word(PCIDEVID_405GP
, PCIBRDGOPT2
, &temp_short
);
332 pci_write_config_word(PCIDEVID_405GP
, PCIBRDGOPT2
, (temp_short
| 0x0001));
334 #ifdef CONFIG_PCI_PNP
335 /*--------------------------------------------------------------------------+
336 * Scan the PCI bus and configure devices found.
337 *--------------------------------------------------------------------------*/
338 #if (CONFIG_PCI_HOST == PCI_HOST_AUTO)
339 if (is_pci_host(hose
) ||
340 (((s
= getenv("pciscan")) != NULL
) && (strcmp(s
, "yes") == 0)))
343 #ifdef CONFIG_PCI_SCAN_SHOW
344 printf("PCI: Bus Dev VenId DevId Class Int\n");
346 hose
->last_busno
= pci_hose_scan(hose
);
348 #endif /* CONFIG_PCI_PNP */
353 * drivers/pci/pci.c skips every host bridge but the 405GP since it could
354 * be set as an Adapter.
356 * I (Andrew May) don't know what we should do here, but I don't want
357 * the auto setup of a PCI device disabling what is done pci_405gp_init
358 * as has happened before.
360 void pci_405gp_setup_bridge(struct pci_controller
*hose
, pci_dev_t dev
,
361 struct pci_config_table
*entry
)
364 printf("405gp_setup_bridge\n");
372 void pci_405gp_fixup_irq(struct pci_controller
*hose
, pci_dev_t dev
)
374 unsigned char int_line
= 0xff;
377 * Write pci interrupt line register (cpci405 specific)
379 switch (PCI_DEV(dev
) & 0x03)
395 pci_hose_write_config_byte(hose
, dev
, PCI_INTERRUPT_LINE
, int_line
);
398 void pci_405gp_setup_vga(struct pci_controller
*hose
, pci_dev_t dev
,
399 struct pci_config_table
*entry
)
401 unsigned int cmdstat
= 0;
403 pciauto_setup_device(hose
, dev
, 6, hose
->pci_mem
, hose
->pci_prefetch
, hose
->pci_io
);
405 /* always enable io space on vga boards */
406 pci_hose_read_config_dword(hose
, dev
, PCI_COMMAND
, &cmdstat
);
407 cmdstat
|= PCI_COMMAND_IO
;
408 pci_hose_write_config_dword(hose
, dev
, PCI_COMMAND
, cmdstat
);
411 #if !(defined(CONFIG_PIP405) || defined (CONFIG_MIP405)) && !(defined (CONFIG_SC3))
414 *As is these functs get called out of flash Not a horrible
415 *thing, but something to keep in mind. (no statics?)
417 static struct pci_config_table pci_405gp_config_table
[] = {
418 /*if VendID is 0 it terminates the table search (ie Walnut)*/
419 #ifdef CONFIG_SYS_PCI_SUBSYS_VENDORID
420 {CONFIG_SYS_PCI_SUBSYS_VENDORID
, PCI_ANY_ID
, PCI_CLASS_BRIDGE_HOST
,
421 PCI_ANY_ID
, PCI_ANY_ID
, PCI_ANY_ID
, pci_405gp_setup_bridge
},
423 {PCI_ANY_ID
, PCI_ANY_ID
, PCI_CLASS_DISPLAY_VGA
,
424 PCI_ANY_ID
, PCI_ANY_ID
, PCI_ANY_ID
, pci_405gp_setup_vga
},
426 {PCI_ANY_ID
, PCI_ANY_ID
, PCI_CLASS_NOT_DEFINED_VGA
,
427 PCI_ANY_ID
, PCI_ANY_ID
, PCI_ANY_ID
, pci_405gp_setup_vga
},
432 static struct pci_controller hose
= {
433 fixup_irq
: pci_405gp_fixup_irq
,
434 config_table
: pci_405gp_config_table
,
437 void pci_init_board(void)
439 /*we want the ptrs to RAM not flash (ie don't use init list)*/
440 hose
.fixup_irq
= pci_405gp_fixup_irq
;
441 hose
.config_table
= pci_405gp_config_table
;
442 pci_405gp_init(&hose
);
447 #endif /* CONFIG_405GP */
449 /*-----------------------------------------------------------------------------+
451 *-----------------------------------------------------------------------------*/
452 #if defined(CONFIG_440)
454 #if defined(CONFIG_SYS_PCI_MASTER_INIT) || defined(CONFIG_SYS_PCI_TARGET_INIT)
455 static struct pci_controller ppc440_hose
= {0};
459 * This routine is called to determine if a pci scan should be
460 * performed. With various hardware environments (especially cPCI and
461 * PPMC) it's insufficient to depend on the state of the arbiter enable
462 * bit in the strap register, or generic host/adapter assumptions.
464 * Rather than hard-code a bad assumption in the general 440 code, the
465 * 440 pci code requires the board to decide at runtime.
467 * Return 0 for adapter mode, non-zero for host (monarch) mode.
469 * Weak default implementation: "Normal" boards implement the PCI
470 * host functionality. This can be overridden for PCI adapter boards.
472 int __is_pci_host(struct pci_controller
*hose
)
476 int is_pci_host(struct pci_controller
*hose
)
477 __attribute__((weak
, alias("__is_pci_host")));
479 #if defined(CONFIG_440EP) || defined(CONFIG_440EPX) || \
480 defined(CONFIG_440GR) || defined(CONFIG_440GRX)
482 #if defined(CONFIG_SYS_PCI_TARGET_INIT)
486 * The bootstrap configuration provides default settings for the pci
487 * inbound map (PIM). But the bootstrap config choices are limited and
488 * may not be sufficient for a given board.
490 void __pci_target_init(struct pci_controller
*hose
)
493 * Set up Direct MMIO registers
497 * PowerPC440 EP PCI Master configuration.
498 * Map one 1Gig range of PLB/processor addresses to PCI memory space.
499 * PLB address 0xA0000000-0xDFFFFFFF ==> PCI address 0xA0000000-0xDFFFFFFF
500 * Use byte reversed out routines to handle endianess.
501 * Make this region non-prefetchable.
503 /* PMM0 Mask/Attribute - disabled b4 setting */
504 out_le32((void *)PCIL0_PMM0MA
, 0x00000000);
505 /* PMM0 Local Address */
506 out_le32((void *)PCIL0_PMM0LA
, CONFIG_SYS_PCI_MEMBASE
);
507 /* PMM0 PCI Low Address */
508 out_le32((void *)PCIL0_PMM0PCILA
, CONFIG_SYS_PCI_MEMBASE
);
509 /* PMM0 PCI High Address */
510 out_le32((void *)PCIL0_PMM0PCIHA
, 0x00000000);
511 /* 512M + No prefetching, and enable region */
512 out_le32((void *)PCIL0_PMM0MA
, 0xE0000001);
514 /* PMM1 Mask/Attribute - disabled b4 setting */
515 out_le32((void *)PCIL0_PMM1MA
, 0x00000000);
516 /* PMM1 Local Address */
517 out_le32((void *)PCIL0_PMM1LA
, CONFIG_SYS_PCI_MEMBASE2
);
518 /* PMM1 PCI Low Address */
519 out_le32((void *)PCIL0_PMM1PCILA
, CONFIG_SYS_PCI_MEMBASE2
);
520 /* PMM1 PCI High Address */
521 out_le32((void *)PCIL0_PMM1PCIHA
, 0x00000000);
522 /* 512M + No prefetching, and enable region */
523 out_le32((void *)PCIL0_PMM1MA
, 0xE0000001);
525 out_le32((void *)PCIL0_PTM1MS
, 0x00000001); /* Memory Size/Attribute */
526 out_le32((void *)PCIL0_PTM1LA
, 0); /* Local Addr. Reg */
527 out_le32((void *)PCIL0_PTM2MS
, 0); /* Memory Size/Attribute */
528 out_le32((void *)PCIL0_PTM2LA
, 0); /* Local Addr. Reg */
531 * Set up Configuration registers
534 /* Program the board's subsystem id/vendor id */
535 pci_write_config_word(0, PCI_SUBSYSTEM_VENDOR_ID
,
536 CONFIG_SYS_PCI_SUBSYS_VENDORID
);
537 pci_write_config_word(0, PCI_SUBSYSTEM_ID
, CONFIG_SYS_PCI_SUBSYS_ID
);
539 /* Configure command register as bus master */
540 pci_write_config_word(0, PCI_COMMAND
, PCI_COMMAND_MASTER
);
542 /* 240nS PCI clock */
543 pci_write_config_word(0, PCI_LATENCY_TIMER
, 1);
545 /* No error reporting */
546 pci_write_config_word(0, PCI_ERREN
, 0);
548 pci_write_config_dword(0, PCI_BRDGOPT2
, 0x00000101);
550 #endif /* CONFIG_SYS_PCI_TARGET_INIT */
555 * This routine is called just prior to registering the hose and gives
556 * the board the opportunity to check things. Returning a value of zero
557 * indicates that things are bad & PCI initialization should be aborted.
559 * Different boards may wish to customize the pci controller structure
560 * (add regions, override default access routines, etc) or perform
561 * certain pre-initialization actions.
564 int __pci_pre_init(struct pci_controller
*hose
)
569 * Set priority for all PLB3 devices to 0.
570 * Set PLB3 arbiter to fair mode.
572 mfsdr(SDR0_AMP1
, reg
);
573 mtsdr(SDR0_AMP1
, (reg
& 0x000000FF) | 0x0000FF00);
574 reg
= mfdcr(PLB3A0_ACR
);
575 mtdcr(PLB3A0_ACR
, reg
| 0x80000000);
578 * Set priority for all PLB4 devices to 0.
580 mfsdr(SDR0_AMP0
, reg
);
581 mtsdr(SDR0_AMP0
, (reg
& 0x000000FF) | 0x0000FF00);
582 reg
= mfdcr(PLB4A0_ACR
) | 0xa0000000;
583 mtdcr(PLB4A0_ACR
, reg
);
586 * Set Nebula PLB4 arbiter to fair mode.
589 reg
= (mfdcr(PLB4A0_ACR
) & ~PLB4Ax_ACR_PPM_MASK
) | PLB4Ax_ACR_PPM_FAIR
;
590 reg
= (reg
& ~PLB4Ax_ACR_HBU_MASK
) | PLB4Ax_ACR_HBU_ENABLED
;
591 reg
= (reg
& ~PLB4Ax_ACR_RDP_MASK
) | PLB4Ax_ACR_RDP_4DEEP
;
592 reg
= (reg
& ~PLB4Ax_ACR_WRP_MASK
) | PLB4Ax_ACR_WRP_2DEEP
;
593 mtdcr(PLB4A0_ACR
, reg
);
596 reg
= (mfdcr(PLB4A1_ACR
) & ~PLB4Ax_ACR_PPM_MASK
) | PLB4Ax_ACR_PPM_FAIR
;
597 reg
= (reg
& ~PLB4Ax_ACR_HBU_MASK
) | PLB4Ax_ACR_HBU_ENABLED
;
598 reg
= (reg
& ~PLB4Ax_ACR_RDP_MASK
) | PLB4Ax_ACR_RDP_4DEEP
;
599 reg
= (reg
& ~PLB4Ax_ACR_WRP_MASK
) | PLB4Ax_ACR_WRP_2DEEP
;
600 mtdcr(PLB4A1_ACR
, reg
);
602 #if defined(CONFIG_SYS_PCI_BOARD_FIXUP_IRQ)
603 hose
->fixup_irq
= board_pci_fixup_irq
;
609 #else /* defined(CONFIG_440EP) ... */
611 #if defined(CONFIG_SYS_PCI_TARGET_INIT)
612 void __pci_target_init(struct pci_controller
* hose
)
617 out_le32((void *)PCIL0_PIM0SA
, 0); /* disable */
618 out_le32((void *)PCIL0_PIM1SA
, 0); /* disable */
619 out_le32((void *)PCIL0_PIM2SA
, 0); /* disable */
620 out_le32((void *)PCIL0_EROMBA
, 0); /* disable expansion rom */
623 * Map all of SDRAM to PCI address 0x0000_0000. Note that the 440
624 * strapping options do not support sizes such as 128/256 MB.
626 out_le32((void *)PCIL0_PIM0LAL
, CONFIG_SYS_SDRAM_BASE
);
627 out_le32((void *)PCIL0_PIM0LAH
, 0);
628 out_le32((void *)PCIL0_PIM0SA
, ~(gd
->ram_size
- 1) | 1);
629 out_le32((void *)PCIL0_BAR0
, 0);
632 * Program the board's subsystem id/vendor id
634 out_le16((void *)PCIL0_SBSYSVID
, CONFIG_SYS_PCI_SUBSYS_VENDORID
);
635 out_le16((void *)PCIL0_SBSYSID
, CONFIG_SYS_PCI_SUBSYS_DEVICEID
);
637 out_le16((void *)PCIL0_CMD
, in_le16((void *)PCIL0_CMD
) |
640 #endif /* CONFIG_SYS_PCI_TARGET_INIT */
642 int __pci_pre_init(struct pci_controller
*hose
)
645 * This board is always configured as the host & requires the
646 * PCI arbiter to be enabled.
648 if (!pci_arbiter_enabled()) {
649 printf("PCI: PCI Arbiter disabled!\n");
656 #endif /* defined(CONFIG_440EP) ... */
658 #if defined(CONFIG_SYS_PCI_TARGET_INIT)
659 void pci_target_init(struct pci_controller
* hose
)
660 __attribute__((weak
, alias("__pci_target_init")));
661 #endif /* CONFIG_SYS_PCI_TARGET_INIT */
663 int pci_pre_init(struct pci_controller
*hose
)
664 __attribute__((weak
, alias("__pci_pre_init")));
666 #if defined(CONFIG_SYS_PCI_MASTER_INIT)
667 void __pci_master_init(struct pci_controller
*hose
)
672 * Write the PowerPC440 EP PCI Configuration regs.
673 * Enable PowerPC440 EP to be a master on the PCI bus (PMM).
674 * Enable PowerPC440 EP to act as a PCI memory target (PTM).
676 pci_read_config_word(0, PCI_COMMAND
, ®
);
677 pci_write_config_word(0, PCI_COMMAND
, reg
|
678 PCI_COMMAND_MASTER
| PCI_COMMAND_MEMORY
);
680 void pci_master_init(struct pci_controller
*hose
)
681 __attribute__((weak
, alias("__pci_master_init")));
682 #endif /* CONFIG_SYS_PCI_MASTER_INIT */
684 #if defined(CONFIG_SYS_PCI_MASTER_INIT) || defined(CONFIG_SYS_PCI_TARGET_INIT)
685 static int pci_440_init (struct pci_controller
*hose
)
689 #ifndef CONFIG_DISABLE_PISE_TEST
690 /*--------------------------------------------------------------------------+
691 * The PCI initialization sequence enable bit must be set ... if not abort
692 * pci setup since updating the bit requires chip reset.
693 *--------------------------------------------------------------------------*/
694 #if defined(CONFIG_440GX) || defined(CONFIG_440SP) || defined(CONFIG_440SPE)
697 mfsdr(SDR0_SDSTP1
,strap
);
698 if ((strap
& SDR0_SDSTP1_PISE_MASK
) == 0) {
699 printf("PCI: SDR0_STRP1[PISE] not set.\n");
700 printf("PCI: Configuration aborted.\n");
703 #elif defined(CONFIG_440GP)
706 strap
= mfdcr(CPC0_STRP1
);
707 if ((strap
& CPC0_STRP1_PISE_MASK
) == 0) {
708 printf("PCI: CPC0_STRP1[PISE] not set.\n");
709 printf("PCI: Configuration aborted.\n");
713 #endif /* CONFIG_DISABLE_PISE_TEST */
715 /*--------------------------------------------------------------------------+
716 * PCI controller init
717 *--------------------------------------------------------------------------*/
718 hose
->first_busno
= 0;
719 hose
->last_busno
= 0;
722 pci_set_region(hose
->regions
+ reg_num
++,
728 /* PCI memory space */
729 pci_set_region(hose
->regions
+ reg_num
++,
730 CONFIG_SYS_PCI_TARGBASE
,
731 CONFIG_SYS_PCI_MEMBASE
,
732 #ifdef CONFIG_SYS_PCI_MEMSIZE
733 CONFIG_SYS_PCI_MEMSIZE
,
739 #if defined(CONFIG_PCI_SYS_MEM_BUS) && defined(CONFIG_PCI_SYS_MEM_PHYS) && \
740 defined(CONFIG_PCI_SYS_MEM_SIZE)
741 /* System memory space */
742 pci_set_region(hose
->regions
+ reg_num
++,
743 CONFIG_PCI_SYS_MEM_BUS
,
744 CONFIG_PCI_SYS_MEM_PHYS
,
745 CONFIG_PCI_SYS_MEM_SIZE
,
746 PCI_REGION_MEM
| PCI_REGION_SYS_MEMORY
);
749 hose
->region_count
= reg_num
;
751 pci_setup_indirect(hose
, PCIL0_CFGADR
, PCIL0_CFGDATA
);
753 /* Let board change/modify hose & do initial checks */
754 if (pci_pre_init(hose
) == 0) {
755 printf("PCI: Board-specific initialization failed.\n");
756 printf("PCI: Configuration aborted.\n");
760 pci_register_hose( hose
);
762 /*--------------------------------------------------------------------------+
764 *--------------------------------------------------------------------------*/
765 #if defined(CONFIG_SYS_PCI_TARGET_INIT)
766 pci_target_init(hose
); /* Let board setup pci target */
768 out16r( PCIL0_SBSYSVID
, CONFIG_SYS_PCI_SUBSYS_VENDORID
);
769 out16r( PCIL0_SBSYSID
, CONFIG_SYS_PCI_SUBSYS_ID
);
770 out16r( PCIL0_CLS
, 0x00060000 ); /* Bridge, host bridge */
773 #if defined(CONFIG_440GX) || defined(CONFIG_440SPE) || \
774 defined(CONFIG_460EX) || defined(CONFIG_460GT)
775 out32r( PCIL0_BRDGOPT1
, 0x04000060 ); /* PLB Rq pri highest */
776 out32r( PCIL0_BRDGOPT2
, in32(PCIL0_BRDGOPT2
) | 0x83 ); /* Enable host config, clear Timeout, ensure int src1 */
777 #elif defined(PCIL0_BRDGOPT1)
778 out32r( PCIL0_BRDGOPT1
, 0x10000060 ); /* PLB Rq pri highest */
779 out32r( PCIL0_BRDGOPT2
, in32(PCIL0_BRDGOPT2
) | 1 ); /* Enable host config */
782 /*--------------------------------------------------------------------------+
783 * PCI master init: default is one 256MB region for PCI memory:
784 * 0x3_00000000 - 0x3_0FFFFFFF ==> CONFIG_SYS_PCI_MEMBASE
785 *--------------------------------------------------------------------------*/
786 #if defined(CONFIG_SYS_PCI_MASTER_INIT)
787 pci_master_init(hose
); /* Let board setup pci master */
789 out32r( PCIL0_POM0SA
, 0 ); /* disable */
790 out32r( PCIL0_POM1SA
, 0 ); /* disable */
791 out32r( PCIL0_POM2SA
, 0 ); /* disable */
792 #if defined(CONFIG_440SPE)
793 out32r( PCIL0_POM0LAL
, 0x10000000 );
794 out32r( PCIL0_POM0LAH
, 0x0000000c );
795 #elif defined(CONFIG_460EX) || defined(CONFIG_460GT)
796 out32r( PCIL0_POM0LAL
, 0x20000000 );
797 out32r( PCIL0_POM0LAH
, 0x0000000c );
799 out32r( PCIL0_POM0LAL
, 0x00000000 );
800 out32r( PCIL0_POM0LAH
, 0x00000003 );
802 out32r( PCIL0_POM0PCIAL
, CONFIG_SYS_PCI_MEMBASE
);
803 out32r( PCIL0_POM0PCIAH
, 0x00000000 );
804 out32r( PCIL0_POM0SA
, 0xf0000001 ); /* 256MB, enabled */
805 out32r( PCIL0_STS
, in32r( PCIL0_STS
) & ~0x0000fff8 );
808 /*--------------------------------------------------------------------------+
809 * PCI host configuration -- we don't make any assumptions here ... the
810 * _board_must_indicate_ what to do -- there's just too many runtime
811 * scenarios in environments like cPCI, PPMC, etc. to make a determination
812 * based on hard-coded values or state of arbiter enable.
813 *--------------------------------------------------------------------------*/
814 if (is_pci_host(hose
)) {
815 #ifdef CONFIG_PCI_SCAN_SHOW
816 printf("PCI: Bus Dev VenId DevId Class Int\n");
818 #if !defined(CONFIG_440EP) && !defined(CONFIG_440GR) && \
819 !defined(CONFIG_440EPX) && !defined(CONFIG_440GRX)
820 out16r( PCIL0_CMD
, in16r( PCIL0_CMD
) | PCI_COMMAND_MASTER
);
822 hose
->last_busno
= pci_hose_scan(hose
);
824 return hose
->last_busno
;
828 void pci_init_board(void)
833 * Only init PCI when either master or target functionality
836 #if defined(CONFIG_SYS_PCI_MASTER_INIT) || defined(CONFIG_SYS_PCI_TARGET_INIT)
837 busno
= pci_440_init(&ppc440_hose
);
841 #if (defined(CONFIG_440SPE) || \
842 defined(CONFIG_460EX) || defined(CONFIG_460GT)) && \
843 !defined(CONFIG_PCI_DISABLE_PCIE)
844 pcie_setup_hoses(busno
+ 1);
848 #endif /* CONFIG_440 */
850 #if defined(CONFIG_405EX)
851 void pci_init_board(void)
853 #ifdef CONFIG_PCI_SCAN_SHOW
854 printf("PCI: Bus Dev VenId DevId Class Int\n");
858 #endif /* CONFIG_405EX */
860 #endif /* CONFIG_PCI */