arch/powerpc/cpu/ppc4xx/4xx_pci.c

   1 /*-----------------------------------------------------------------------------+
   2  *       This source code is dual-licensed.  You may use it under the terms of
   3  *       the GNU General Public license version 2, or under the license below.
   4  *
   5  *       This source code has been made available to you by IBM on an AS-IS
   6  *       basis.  Anyone receiving this source is licensed under IBM
   7  *       copyrights to use it in any way he or she deems fit, including
   8  *       copying it, modifying it, compiling it, and redistributing it either
   9  *       with or without modifications.  No license under IBM patents or
  10  *       patent applications is to be implied by the copyright license.
  11  *
  12  *       Any user of this software should understand that IBM cannot provide
  13  *       technical support for this software and will not be responsible for
  14  *       any consequences resulting from the use of this software.
  15  *
  16  *       Any person who transfers this source code or any derivative work
  17  *       must include the IBM copyright notice, this paragraph, and the
  18  *       preceding two paragraphs in the transferred software.
  19  *
  20  *       COPYRIGHT   I B M   CORPORATION 1995
  21  *       LICENSED MATERIAL  -  PROGRAM PROPERTY OF I B M
  22  *-----------------------------------------------------------------------------*/
  23 /*----------------------------------------------------------------------------+
  24  *
  25  *  File Name:   405gp_pci.c
  26  *
  27  *  Function:    Initialization code for the 405GP PCI Configuration regs.
  28  *
  29  *  Author:      Mark Game
  30  *
  31  *  Change Activity-
  32  *
  33  *  Date        Description of Change                                       BY
  34  *  ---------   ---------------------                                       ---
  35  *  09-Sep-98   Created                                                     MCG
  36  *  02-Nov-98   Removed External arbiter selected message                   JWB
  37  *  27-Nov-98   Zero out PTMBAR2 and disable in PTM2MS                      JWB
  38  *  04-Jan-99   Zero out other unused PMM and PTM regs. Change bus scan     MCG
  39  *              from (0 to n) to (1 to n).
  40  *  17-May-99   Port to Walnut                                              JWB
  41  *  17-Jun-99   Updated for VGA support                                     JWB
  42  *  21-Jun-99   Updated to allow SRAM region to be a target from PCI bus    JWB
  43  *  19-Jul-99   Updated for 405GP pass 1 errata #26 (Low PCI subsequent     MCG
  44  *              target latency timer values are not supported).
  45  *              Should be fixed in pass 2.
  46  *  09-Sep-99   Removed use of PTM2 since the SRAM region no longer needs   JWB
  47  *              to be a PCI target. Zero out PTMBAR2 and disable in PTM2MS.
  48  *  10-Dec-99   Updated PCI_Write_CFG_Reg for pass2 errata #6               JWB
  49  *  11-Jan-00   Ensure PMMxMAs disabled before setting PMMxLAs. This is not
  50  *              really required after a reset since PMMxMAs are already
  51  *              disabled but is a good practice nonetheless.                JWB
  52  *  12-Jun-01   stefan.roese@esd-electronics.com
  53  *              - PCI host/adapter handling reworked
  54  *  09-Jul-01   stefan.roese@esd-electronics.com
  55  *              - PCI host now configures from device 0 (not 1) to max_dev,
  56  *                (host configures itself)
  57  *              - On CPCI-405 pci base address and size is generated from
  58  *                SDRAM and FLASH size (CFG regs not used anymore)
  59  *              - Some minor changes for CPCI-405-A (adapter version)
  60  *  14-Sep-01   stefan.roese@esd-electronics.com
  61  *              - CONFIG_PCI_SCAN_SHOW added to print pci devices upon startup
  62  *  28-Sep-01   stefan.roese@esd-electronics.com
  63  *              - Changed pci master configuration for linux compatibility
  64  *                (no need for bios_fixup() anymore)
  65  *  26-Feb-02   stefan.roese@esd-electronics.com
  66  *              - Bug fixed in pci configuration (Andrew May)
  67  *              - Removed pci class code init for CPCI405 board
  68  *  15-May-02   stefan.roese@esd-electronics.com
  69  *              - New vga device handling
  70  *  29-May-02   stefan.roese@esd-electronics.com
  71  *              - PCI class code init added (if defined)
  72  *----------------------------------------------------------------------------*/
  73
  74 #include <common.h>
  75 #include <command.h>
  76 #include <asm/4xx_pci.h>
  77 #include <asm/processor.h>
  78 #include <asm/io.h>
  79 #include <pci.h>
  80
  81 #ifdef CONFIG_PCI
  82
  83 DECLARE_GLOBAL_DATA_PTR;
  84
  85 #if defined(CONFIG_405GP) || defined(CONFIG_405EP)
  86
  87 #if defined(CONFIG_PMC405)
  88 ushort pmc405_pci_subsys_deviceid(void);
  89 #endif
  90
  91 /*#define DEBUG*/
  92
  93 /*
  94  * Board-specific pci initialization
  95  * Platform code can reimplement pci_pre_init() if needed
  96  */
  97 int __pci_pre_init(struct pci_controller *hose)
  98 {
  99 #if defined(CONFIG_405EP)
 100         /*
 101          * Enable the internal PCI arbiter by default.
 102          *
 103          * On 405EP CPUs the internal arbiter can be controlled
 104          * by the I2C strapping EEPROM. If you want to do so
 105          * or if you want to disable the arbiter pci_pre_init()
 106          * must be reimplemented without enabling the arbiter.
 107          * The arbiter is enabled in this place because of
 108          * compatibility reasons.
 109          */
 110         mtdcr(CPC0_PCI, mfdcr(CPC0_PCI) | CPC0_PCI_ARBIT_EN);
 111 #endif /* CONFIG_405EP */
 112
 113         return 1;
 114 }
 115 int pci_pre_init(struct pci_controller *hose)
 116         __attribute__((weak, alias("__pci_pre_init")));
 117
 118 int __is_pci_host(struct pci_controller *hose)
 119 {
 120 #if defined(CONFIG_405GP)
 121         if (mfdcr(CPC0_PSR) & PSR_PCI_ARBIT_EN)
 122                 return 1;
 123 #elif defined (CONFIG_405EP)
 124         if (mfdcr(CPC0_PCI) & CPC0_PCI_ARBIT_EN)
 125                 return 1;
 126 #endif
 127         return 0;
 128 }
 129 int is_pci_host(struct pci_controller *hose) __attribute__((weak, alias("__is_pci_host")));
 130
 131 /*-----------------------------------------------------------------------------+
 132  * pci_init.  Initializes the 405GP PCI Configuration regs.
 133  *-----------------------------------------------------------------------------*/
 134 void pci_405gp_init(struct pci_controller *hose)
 135 {
 136         int i, reg_num = 0;
 137         bd_t *bd = gd->bd;
 138
 139         unsigned short temp_short;
 140         unsigned long ptmpcila[2] = {CONFIG_SYS_PCI_PTM1PCI, CONFIG_SYS_PCI_PTM2PCI};
 141 #if defined(CONFIG_PCI_4xx_PTM_OVERWRITE)
 142         char *ptmla_str, *ptmms_str;
 143 #endif
 144         unsigned long ptmla[2]    = {CONFIG_SYS_PCI_PTM1LA, CONFIG_SYS_PCI_PTM2LA};
 145         unsigned long ptmms[2]    = {CONFIG_SYS_PCI_PTM1MS, CONFIG_SYS_PCI_PTM2MS};
 146 #if defined(CONFIG_PIP405) || defined (CONFIG_MIP405)
 147         unsigned long pmmla[3]    = {0x80000000, 0xA0000000, 0};
 148         unsigned long pmmma[3]    = {0xE0000001, 0xE0000001, 0};
 149         unsigned long pmmpcila[3] = {0x80000000, 0x00000000, 0};
 150         unsigned long pmmpciha[3] = {0x00000000, 0x00000000, 0};
 151 #else
 152         unsigned long pmmla[3]    = {0x80000000, 0,0};
 153         unsigned long pmmma[3]    = {0xC0000001, 0,0};
 154         unsigned long pmmpcila[3] = {0x80000000, 0,0};
 155         unsigned long pmmpciha[3] = {0x00000000, 0,0};
 156 #endif
 157 #ifdef CONFIG_PCI_PNP
 158 #if (CONFIG_PCI_HOST == PCI_HOST_AUTO)
 159         char *s;
 160 #endif
 161 #endif
 162
 163 #if defined(CONFIG_PCI_4xx_PTM_OVERWRITE)
 164         ptmla_str = getenv("ptm1la");
 165         ptmms_str = getenv("ptm1ms");
 166         if(NULL != ptmla_str && NULL != ptmms_str ) {
 167                 ptmla[0] = simple_strtoul (ptmla_str, NULL, 16);
 168                 ptmms[0] = simple_strtoul (ptmms_str, NULL, 16);
 169         }
 170
 171         ptmla_str = getenv("ptm2la");
 172         ptmms_str = getenv("ptm2ms");
 173         if(NULL != ptmla_str && NULL != ptmms_str ) {
 174                 ptmla[1] = simple_strtoul (ptmla_str, NULL, 16);
 175                 ptmms[1] = simple_strtoul (ptmms_str, NULL, 16);
 176         }
 177 #endif
 178
 179         /*
 180          * Register the hose
 181          */
 182         hose->first_busno = 0;
 183         hose->last_busno = 0xff;
 184
 185         /* ISA/PCI I/O space */
 186         pci_set_region(hose->regions + reg_num++,
 187                        MIN_PCI_PCI_IOADDR,
 188                        MIN_PLB_PCI_IOADDR,
 189                        0x10000,
 190                        PCI_REGION_IO);
 191
 192         /* PCI I/O space */
 193         pci_set_region(hose->regions + reg_num++,
 194                        0x00800000,
 195                        0xe8800000,
 196                        0x03800000,
 197                        PCI_REGION_IO);
 198
 199         reg_num = 2;
 200
 201         /* Memory spaces */
 202         for (i=0; i<2; i++)
 203                 if (ptmms[i] & 1)
 204                 {
 205                         if (!i) hose->pci_fb = hose->regions + reg_num;
 206
 207                         pci_set_region(hose->regions + reg_num++,
 208                                        ptmpcila[i], ptmla[i],
 209                                        ~(ptmms[i] & 0xfffff000) + 1,
 210                                        PCI_REGION_MEM |
 211                                        PCI_REGION_SYS_MEMORY);
 212                 }
 213
 214         /* PCI memory spaces */
 215         for (i=0; i<3; i++)
 216                 if (pmmma[i] & 1)
 217                 {
 218                         pci_set_region(hose->regions + reg_num++,
 219                                        pmmpcila[i], pmmla[i],
 220                                        ~(pmmma[i] & 0xfffff000) + 1,
 221                                        PCI_REGION_MEM);
 222                 }
 223
 224         hose->region_count = reg_num;
 225
 226         pci_setup_indirect(hose,
 227                            PCICFGADR,
 228                            PCICFGDATA);
 229
 230         if (hose->pci_fb)
 231                 pciauto_region_init(hose->pci_fb);
 232
 233         /* Let board change/modify hose & do initial checks */
 234         if (pci_pre_init(hose) == 0) {
 235                 printf("PCI: Board-specific initialization failed.\n");
 236                 printf("PCI: Configuration aborted.\n");
 237                 return;
 238         }
 239
 240         pci_register_hose(hose);
 241
 242         /*--------------------------------------------------------------------------+
 243          * 405GP PCI Master configuration.
 244          * Map one 512 MB range of PLB/processor addresses to PCI memory space.
 245          * PLB address 0x80000000-0xBFFFFFFF ==> PCI address 0x80000000-0xBFFFFFFF
 246          * Use byte reversed out routines to handle endianess.
 247          *--------------------------------------------------------------------------*/
 248         out32r(PMM0MA,    (pmmma[0]&~0x1)); /* disable, configure PMMxLA, PMMxPCILA first */
 249         out32r(PMM0LA,    pmmla[0]);
 250         out32r(PMM0PCILA, pmmpcila[0]);
 251         out32r(PMM0PCIHA, pmmpciha[0]);
 252         out32r(PMM0MA,    pmmma[0]);
 253
 254         /*--------------------------------------------------------------------------+
 255          * PMM1 is not used.  Initialize them to zero.
 256          *--------------------------------------------------------------------------*/
 257         out32r(PMM1MA,    (pmmma[1]&~0x1));
 258         out32r(PMM1LA,    pmmla[1]);
 259         out32r(PMM1PCILA, pmmpcila[1]);
 260         out32r(PMM1PCIHA, pmmpciha[1]);
 261         out32r(PMM1MA,    pmmma[1]);
 262
 263         /*--------------------------------------------------------------------------+
 264          * PMM2 is not used.  Initialize them to zero.
 265          *--------------------------------------------------------------------------*/
 266         out32r(PMM2MA,    (pmmma[2]&~0x1));
 267         out32r(PMM2LA,    pmmla[2]);
 268         out32r(PMM2PCILA, pmmpcila[2]);
 269         out32r(PMM2PCIHA, pmmpciha[2]);
 270         out32r(PMM2MA,    pmmma[2]);
 271
 272         /*--------------------------------------------------------------------------+
 273          * 405GP PCI Target configuration.  (PTM1)
 274          * Note: PTM1MS is hardwire enabled but we set the enable bit anyway.
 275          *--------------------------------------------------------------------------*/
 276         out32r(PTM1LA,    ptmla[0]);         /* insert address                     */
 277         out32r(PTM1MS,    ptmms[0]);         /* insert size, enable bit is 1       */
 278         pci_write_config_dword(PCIDEVID_405GP, PCI_BASE_ADDRESS_1, ptmpcila[0]);
 279
 280         /*--------------------------------------------------------------------------+
 281          * 405GP PCI Target configuration.  (PTM2)
 282          *--------------------------------------------------------------------------*/
 283         out32r(PTM2LA, ptmla[1]);            /* insert address                     */
 284         pci_write_config_dword(PCIDEVID_405GP, PCI_BASE_ADDRESS_2, ptmpcila[1]);
 285
 286         if (ptmms[1] == 0)
 287         {
 288                 out32r(PTM2MS,    0x00000001);   /* set enable bit                     */
 289                 pci_write_config_dword(PCIDEVID_405GP, PCI_BASE_ADDRESS_2, 0x00000000);
 290                 out32r(PTM2MS,    0x00000000);   /* disable                            */
 291         }
 292         else
 293         {
 294                 out32r(PTM2MS, ptmms[1]);        /* insert size, enable bit is 1       */
 295         }
 296
 297         /*
 298          * Insert Subsystem Vendor and Device ID
 299          */
 300         pci_write_config_word(PCIDEVID_405GP, PCI_SUBSYSTEM_VENDOR_ID, CONFIG_SYS_PCI_SUBSYS_VENDORID);
 301 #ifdef CONFIG_CPCI405
 302         if (is_pci_host(hose))
 303                 pci_write_config_word(PCIDEVID_405GP, PCI_SUBSYSTEM_ID, CONFIG_SYS_PCI_SUBSYS_DEVICEID);
 304         else
 305                 pci_write_config_word(PCIDEVID_405GP, PCI_SUBSYSTEM_ID, CONFIG_SYS_PCI_SUBSYS_DEVICEID2);
 306 #else
 307         pci_write_config_word(PCIDEVID_405GP, PCI_SUBSYSTEM_ID, CONFIG_SYS_PCI_SUBSYS_DEVICEID);
 308 #endif
 309
 310         /*
 311          * Insert Class-code
 312          */
 313 #ifdef CONFIG_SYS_PCI_CLASSCODE
 314         pci_write_config_word(PCIDEVID_405GP, PCI_CLASS_SUB_CODE, CONFIG_SYS_PCI_CLASSCODE);
 315 #endif /* CONFIG_SYS_PCI_CLASSCODE */
 316
 317         /*--------------------------------------------------------------------------+
 318          * If PCI speed = 66MHz, set 66MHz capable bit.
 319          *--------------------------------------------------------------------------*/
 320         if (bd->bi_pci_busfreq >= 66000000) {
 321                 pci_read_config_word(PCIDEVID_405GP, PCI_STATUS, &temp_short);
 322                 pci_write_config_word(PCIDEVID_405GP,PCI_STATUS,(temp_short|PCI_STATUS_66MHZ));
 323         }
 324
 325 #if (CONFIG_PCI_HOST != PCI_HOST_ADAPTER)
 326 #if (CONFIG_PCI_HOST == PCI_HOST_AUTO)
 327         if (is_pci_host(hose) ||
 328             (((s = getenv("pciscan")) != NULL) && (strcmp(s, "yes") == 0)))
 329 #endif
 330         {
 331                 /*--------------------------------------------------------------------------+
 332                  * Write the 405GP PCI Configuration regs.
 333                  * Enable 405GP to be a master on the PCI bus (PMM).
 334                  * Enable 405GP to act as a PCI memory target (PTM).
 335                  *--------------------------------------------------------------------------*/
 336                 pci_read_config_word(PCIDEVID_405GP, PCI_COMMAND, &temp_short);
 337                 pci_write_config_word(PCIDEVID_405GP, PCI_COMMAND, temp_short |
 338                                       PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY);
 339         }
 340 #endif
 341
 342 #if defined(CONFIG_405EP)
 343         /*
 344          * on ppc405ep vendor/device id is not set
 345          * The user manual says 0x1014 (IBM) / 0x0156 (405GP!)
 346          * are the correct values.
 347          */
 348         pci_write_config_word(PCIDEVID_405GP, PCI_VENDOR_ID, PCI_VENDOR_ID_IBM);
 349         pci_write_config_word(PCIDEVID_405GP,
 350                               PCI_DEVICE_ID, PCI_DEVICE_ID_IBM_405GP);
 351 #endif
 352
 353         /*
 354          * Set HCE bit (Host Configuration Enabled)
 355          */
 356         pci_read_config_word(PCIDEVID_405GP, PCIBRDGOPT2, &temp_short);
 357         pci_write_config_word(PCIDEVID_405GP, PCIBRDGOPT2, (temp_short | 0x0001));
 358
 359 #ifdef CONFIG_PCI_PNP
 360         /*--------------------------------------------------------------------------+
 361          * Scan the PCI bus and configure devices found.
 362          *--------------------------------------------------------------------------*/
 363 #if (CONFIG_PCI_HOST == PCI_HOST_AUTO)
 364         if (is_pci_host(hose) ||
 365             (((s = getenv("pciscan")) != NULL) && (strcmp(s, "yes") == 0)))
 366 #endif
 367         {
 368 #ifdef CONFIG_PCI_SCAN_SHOW
 369                 printf("PCI:   Bus Dev VenId DevId Class Int\n");
 370 #endif
 371                 hose->last_busno = pci_hose_scan(hose);
 372         }
 373 #endif  /* CONFIG_PCI_PNP */
 374
 375 }
 376
 377 /*
 378  * drivers/pci/pci.c skips every host bridge but the 405GP since it could
 379  * be set as an Adapter.
 380  *
 381  * I (Andrew May) don't know what we should do here, but I don't want
 382  * the auto setup of a PCI device disabling what is done pci_405gp_init
 383  * as has happened before.
 384  */
 385 void pci_405gp_setup_bridge(struct pci_controller *hose, pci_dev_t dev,
 386                             struct pci_config_table *entry)
 387 {
 388 #ifdef DEBUG
 389         printf("405gp_setup_bridge\n");
 390 #endif
 391 }
 392
 393 /*
 394  *
 395  */
 396
 397 void pci_405gp_fixup_irq(struct pci_controller *hose, pci_dev_t dev)
 398 {
 399         unsigned char int_line = 0xff;
 400
 401         /*
 402          * Write pci interrupt line register (cpci405 specific)
 403          */
 404         switch (PCI_DEV(dev) & 0x03)
 405         {
 406         case 0:
 407                 int_line = 27 + 2;
 408                 break;
 409         case 1:
 410                 int_line = 27 + 3;
 411                 break;
 412         case 2:
 413                 int_line = 27 + 0;
 414                 break;
 415         case 3:
 416                 int_line = 27 + 1;
 417                 break;
 418         }
 419
 420         pci_hose_write_config_byte(hose, dev, PCI_INTERRUPT_LINE, int_line);
 421 }
 422
 423 void pci_405gp_setup_vga(struct pci_controller *hose, pci_dev_t dev,
 424                          struct pci_config_table *entry)
 425 {
 426         unsigned int cmdstat = 0;
 427
 428         pciauto_setup_device(hose, dev, 6, hose->pci_mem, hose->pci_prefetch, hose->pci_io);
 429
 430         /* always enable io space on vga boards */
 431         pci_hose_read_config_dword(hose, dev, PCI_COMMAND, &cmdstat);
 432         cmdstat |= PCI_COMMAND_IO;
 433         pci_hose_write_config_dword(hose, dev, PCI_COMMAND, cmdstat);
 434 }
 435
 436 #if !(defined(CONFIG_PIP405) || defined (CONFIG_MIP405)) && !(defined (CONFIG_SC3))
 437
 438 /*
 439  *As is these functs get called out of flash Not a horrible
 440  *thing, but something to keep in mind. (no statics?)
 441  */
 442 static struct pci_config_table pci_405gp_config_table[] = {
 443 /*if VendID is 0 it terminates the table search (ie Walnut)*/
 444 #ifdef CONFIG_SYS_PCI_SUBSYS_VENDORID
 445         {CONFIG_SYS_PCI_SUBSYS_VENDORID, PCI_ANY_ID, PCI_CLASS_BRIDGE_HOST,
 446          PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, pci_405gp_setup_bridge},
 447 #endif
 448         {PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_DISPLAY_VGA,
 449          PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, pci_405gp_setup_vga},
 450
 451         {PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_NOT_DEFINED_VGA,
 452          PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, pci_405gp_setup_vga},
 453
 454         { }
 455 };
 456
 457 static struct pci_controller hose = {
 458         fixup_irq: pci_405gp_fixup_irq,
 459         config_table: pci_405gp_config_table,
 460 };
 461
 462 void pci_init_board(void)
 463 {
 464         /*we want the ptrs to RAM not flash (ie don't use init list)*/
 465         hose.fixup_irq    = pci_405gp_fixup_irq;
 466         hose.config_table = pci_405gp_config_table;
 467         pci_405gp_init(&hose);
 468 }
 469
 470 #endif
 471
 472 #endif /* CONFIG_405GP */
 473
 474 /*-----------------------------------------------------------------------------+
 475  * CONFIG_440
 476  *-----------------------------------------------------------------------------*/
 477 #if defined(CONFIG_440)
 478
 479 #if defined(CONFIG_SYS_PCI_MASTER_INIT) || defined(CONFIG_SYS_PCI_TARGET_INIT)
 480 static struct pci_controller ppc440_hose = {0};
 481 #endif
 482
 483 /*
 484  * This routine is called to determine if a pci scan should be
 485  * performed. With various hardware environments (especially cPCI and
 486  * PPMC) it's insufficient to depend on the state of the arbiter enable
 487  * bit in the strap register, or generic host/adapter assumptions.
 488  *
 489  * Rather than hard-code a bad assumption in the general 440 code, the
 490  * 440 pci code requires the board to decide at runtime.
 491  *
 492  * Return 0 for adapter mode, non-zero for host (monarch) mode.
 493  *
 494  * Weak default implementation: "Normal" boards implement the PCI
 495  * host functionality. This can be overridden for PCI adapter boards.
 496  */
 497 int __is_pci_host(struct pci_controller *hose)
 498 {
 499         return 1;
 500 }
 501 int is_pci_host(struct pci_controller *hose)
 502         __attribute__((weak, alias("__is_pci_host")));
 503
 504 #if defined(CONFIG_440EP) || defined(CONFIG_440EPX) || \
 505     defined(CONFIG_440GR) || defined(CONFIG_440GRX)
 506
 507 #if defined(CONFIG_SYS_PCI_TARGET_INIT)
 508 /*
 509  * pci_target_init
 510  *
 511  * The bootstrap configuration provides default settings for the pci
 512  * inbound map (PIM). But the bootstrap config choices are limited and
 513  * may not be sufficient for a given board.
 514  */
 515 void __pci_target_init(struct pci_controller *hose)
 516 {
 517         /*
 518          * Set up Direct MMIO registers
 519          */
 520
 521         /*
 522          * PowerPC440 EP PCI Master configuration.
 523          * Map one 1Gig range of PLB/processor addresses to PCI memory space.
 524          * PLB address 0xA0000000-0xDFFFFFFF ==> PCI address 0xA0000000-0xDFFFFFFF
 525          * Use byte reversed out routines to handle endianess.
 526          * Make this region non-prefetchable.
 527          */
 528         /* PMM0 Mask/Attribute - disabled b4 setting */
 529         out_le32((void *)PCIL0_PMM0MA, 0x00000000);
 530         /* PMM0 Local Address */
 531         out_le32((void *)PCIL0_PMM0LA, CONFIG_SYS_PCI_MEMBASE);
 532         /* PMM0 PCI Low Address */
 533         out_le32((void *)PCIL0_PMM0PCILA, CONFIG_SYS_PCI_MEMBASE);
 534         /* PMM0 PCI High Address */
 535         out_le32((void *)PCIL0_PMM0PCIHA, 0x00000000);
 536         /* 512M + No prefetching, and enable region */
 537         out_le32((void *)PCIL0_PMM0MA, 0xE0000001);
 538
 539         /* PMM1 Mask/Attribute - disabled b4 setting */
 540         out_le32((void *)PCIL0_PMM1MA, 0x00000000);
 541         /* PMM1 Local Address */
 542         out_le32((void *)PCIL0_PMM1LA, CONFIG_SYS_PCI_MEMBASE2);
 543         /* PMM1 PCI Low Address */
 544         out_le32((void *)PCIL0_PMM1PCILA, CONFIG_SYS_PCI_MEMBASE2);
 545         /* PMM1 PCI High Address */
 546         out_le32((void *)PCIL0_PMM1PCIHA, 0x00000000);
 547         /* 512M + No prefetching, and enable region */
 548         out_le32((void *)PCIL0_PMM1MA, 0xE0000001);
 549
 550         out_le32((void *)PCIL0_PTM1MS, 0x00000001); /* Memory Size/Attribute */
 551         out_le32((void *)PCIL0_PTM1LA, 0);      /* Local Addr. Reg */
 552         out_le32((void *)PCIL0_PTM2MS, 0);      /* Memory Size/Attribute */
 553         out_le32((void *)PCIL0_PTM2LA, 0);      /* Local Addr. Reg */
 554
 555         /*
 556          * Set up Configuration registers
 557          */
 558
 559         /* Program the board's subsystem id/vendor id */
 560         pci_write_config_word(0, PCI_SUBSYSTEM_VENDOR_ID,
 561                               CONFIG_SYS_PCI_SUBSYS_VENDORID);
 562         pci_write_config_word(0, PCI_SUBSYSTEM_ID, CONFIG_SYS_PCI_SUBSYS_ID);
 563
 564         /* Configure command register as bus master */
 565         pci_write_config_word(0, PCI_COMMAND, PCI_COMMAND_MASTER);
 566
 567         /* 240nS PCI clock */
 568         pci_write_config_word(0, PCI_LATENCY_TIMER, 1);
 569
 570         /* No error reporting */
 571         pci_write_config_word(0, PCI_ERREN, 0);
 572
 573         pci_write_config_dword(0, PCI_BRDGOPT2, 0x00000101);
 574 }
 575 #endif /* CONFIG_SYS_PCI_TARGET_INIT */
 576
 577 /*
 578  * pci_pre_init
 579  *
 580  * This routine is called just prior to registering the hose and gives
 581  * the board the opportunity to check things. Returning a value of zero
 582  * indicates that things are bad & PCI initialization should be aborted.
 583  *
 584  * Different boards may wish to customize the pci controller structure
 585  * (add regions, override default access routines, etc) or perform
 586  * certain pre-initialization actions.
 587  *
 588  */
 589 int __pci_pre_init(struct pci_controller *hose)
 590 {
 591         u32 reg;
 592
 593         /*
 594          * Set priority for all PLB3 devices to 0.
 595          * Set PLB3 arbiter to fair mode.
 596          */
 597         mfsdr(SDR0_AMP1, reg);
 598         mtsdr(SDR0_AMP1, (reg & 0x000000FF) | 0x0000FF00);
 599         reg = mfdcr(PLB3A0_ACR);
 600         mtdcr(PLB3A0_ACR, reg | 0x80000000);
 601
 602         /*
 603          * Set priority for all PLB4 devices to 0.
 604          */
 605         mfsdr(SDR0_AMP0, reg);
 606         mtsdr(SDR0_AMP0, (reg & 0x000000FF) | 0x0000FF00);
 607         reg = mfdcr(PLB4A0_ACR) | 0xa0000000;
 608         mtdcr(PLB4A0_ACR, reg);
 609
 610         /*
 611          * Set Nebula PLB4 arbiter to fair mode.
 612          */
 613         /* Segment0 */
 614         reg = (mfdcr(PLB4A0_ACR) & ~PLB4Ax_ACR_PPM_MASK) | PLB4Ax_ACR_PPM_FAIR;
 615         reg = (reg & ~PLB4Ax_ACR_HBU_MASK) | PLB4Ax_ACR_HBU_ENABLED;
 616         reg = (reg & ~PLB4Ax_ACR_RDP_MASK) | PLB4Ax_ACR_RDP_4DEEP;
 617         reg = (reg & ~PLB4Ax_ACR_WRP_MASK) | PLB4Ax_ACR_WRP_2DEEP;
 618         mtdcr(PLB4A0_ACR, reg);
 619
 620         /* Segment1 */
 621         reg = (mfdcr(PLB4A1_ACR) & ~PLB4Ax_ACR_PPM_MASK) | PLB4Ax_ACR_PPM_FAIR;
 622         reg = (reg & ~PLB4Ax_ACR_HBU_MASK) | PLB4Ax_ACR_HBU_ENABLED;
 623         reg = (reg & ~PLB4Ax_ACR_RDP_MASK) | PLB4Ax_ACR_RDP_4DEEP;
 624         reg = (reg & ~PLB4Ax_ACR_WRP_MASK) | PLB4Ax_ACR_WRP_2DEEP;
 625         mtdcr(PLB4A1_ACR, reg);
 626
 627 #if defined(CONFIG_SYS_PCI_BOARD_FIXUP_IRQ)
 628         hose->fixup_irq = board_pci_fixup_irq;
 629 #endif
 630
 631         return 1;
 632 }
 633
 634 #else /* defined(CONFIG_440EP) ... */
 635
 636 #if defined(CONFIG_SYS_PCI_TARGET_INIT)
 637 void __pci_target_init(struct pci_controller * hose)
 638 {
 639         /*
 640          * Disable everything
 641          */
 642         out_le32((void *)PCIL0_PIM0SA, 0); /* disable */
 643         out_le32((void *)PCIL0_PIM1SA, 0); /* disable */
 644         out_le32((void *)PCIL0_PIM2SA, 0); /* disable */
 645         out_le32((void *)PCIL0_EROMBA, 0); /* disable expansion rom */
 646
 647         /*
 648          * Map all of SDRAM to PCI address 0x0000_0000. Note that the 440
 649          * strapping options do not support sizes such as 128/256 MB.
 650          */
 651         out_le32((void *)PCIL0_PIM0LAL, CONFIG_SYS_SDRAM_BASE);
 652         out_le32((void *)PCIL0_PIM0LAH, 0);
 653         out_le32((void *)PCIL0_PIM0SA, ~(gd->ram_size - 1) | 1);
 654         out_le32((void *)PCIL0_BAR0, 0);
 655
 656         /*
 657          * Program the board's subsystem id/vendor id
 658          */
 659         out_le16((void *)PCIL0_SBSYSVID, CONFIG_SYS_PCI_SUBSYS_VENDORID);
 660         out_le16((void *)PCIL0_SBSYSID, CONFIG_SYS_PCI_SUBSYS_DEVICEID);
 661
 662         out_le16((void *)PCIL0_CMD, in_le16((void *)PCIL0_CMD) |
 663                  PCI_COMMAND_MEMORY);
 664 }
 665 #endif /* CONFIG_SYS_PCI_TARGET_INIT */
 666
 667 int __pci_pre_init(struct pci_controller *hose)
 668 {
 669         /*
 670          * This board is always configured as the host & requires the
 671          * PCI arbiter to be enabled.
 672          */
 673         if (!pci_arbiter_enabled()) {
 674                 printf("PCI: PCI Arbiter disabled!\n");
 675                 return 0;
 676         }
 677
 678         return 1;
 679 }
 680
 681 #endif /* defined(CONFIG_440EP) ... */
 682
 683 #if defined(CONFIG_SYS_PCI_TARGET_INIT)
 684 void pci_target_init(struct pci_controller * hose)
 685         __attribute__((weak, alias("__pci_target_init")));
 686 #endif /* CONFIG_SYS_PCI_TARGET_INIT */
 687
 688 int pci_pre_init(struct pci_controller *hose)
 689         __attribute__((weak, alias("__pci_pre_init")));
 690
 691 #if defined(CONFIG_SYS_PCI_MASTER_INIT)
 692 void __pci_master_init(struct pci_controller *hose)
 693 {
 694         u16 reg;
 695
 696         /*
 697          * Write the PowerPC440 EP PCI Configuration regs.
 698          * Enable PowerPC440 EP to be a master on the PCI bus (PMM).
 699          * Enable PowerPC440 EP to act as a PCI memory target (PTM).
 700          */
 701         pci_read_config_word(0, PCI_COMMAND, &reg);
 702         pci_write_config_word(0, PCI_COMMAND, reg |
 703                               PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY);
 704 }
 705 void pci_master_init(struct pci_controller *hose)
 706         __attribute__((weak, alias("__pci_master_init")));
 707 #endif /* CONFIG_SYS_PCI_MASTER_INIT */
 708
 709 #if defined(CONFIG_SYS_PCI_MASTER_INIT) || defined(CONFIG_SYS_PCI_TARGET_INIT)
 710 static int pci_440_init (struct pci_controller *hose)
 711 {
 712         int reg_num = 0;
 713
 714 #ifndef CONFIG_DISABLE_PISE_TEST
 715         /*--------------------------------------------------------------------------+
 716          * The PCI initialization sequence enable bit must be set ... if not abort
 717          * pci setup since updating the bit requires chip reset.
 718          *--------------------------------------------------------------------------*/
 719 #if defined(CONFIG_440GX) || defined(CONFIG_440SP) || defined(CONFIG_440SPE)
 720         unsigned long strap;
 721
 722         mfsdr(SDR0_SDSTP1,strap);
 723         if ((strap & SDR0_SDSTP1_PISE_MASK) == 0) {
 724                 printf("PCI: SDR0_STRP1[PISE] not set.\n");
 725                 printf("PCI: Configuration aborted.\n");
 726                 return -1;
 727         }
 728 #elif defined(CONFIG_440GP)
 729         unsigned long strap;
 730
 731         strap = mfdcr(CPC0_STRP1);
 732         if ((strap & CPC0_STRP1_PISE_MASK) == 0) {
 733                 printf("PCI: CPC0_STRP1[PISE] not set.\n");
 734                 printf("PCI: Configuration aborted.\n");
 735                 return -1;
 736         }
 737 #endif
 738 #endif /* CONFIG_DISABLE_PISE_TEST */
 739
 740         /*--------------------------------------------------------------------------+
 741          * PCI controller init
 742          *--------------------------------------------------------------------------*/
 743         hose->first_busno = 0;
 744         hose->last_busno = 0;
 745
 746         /* PCI I/O space */
 747         pci_set_region(hose->regions + reg_num++,
 748                        0x00000000,
 749                        PCIL0_IOBASE,
 750                        0x10000,
 751                        PCI_REGION_IO);
 752
 753         /* PCI memory space */
 754         pci_set_region(hose->regions + reg_num++,
 755                        CONFIG_SYS_PCI_TARGBASE,
 756                        CONFIG_SYS_PCI_MEMBASE,
 757 #ifdef CONFIG_SYS_PCI_MEMSIZE
 758                        CONFIG_SYS_PCI_MEMSIZE,
 759 #else
 760                        0x10000000,
 761 #endif
 762                        PCI_REGION_MEM );
 763
 764 #if defined(CONFIG_PCI_SYS_MEM_BUS) && defined(CONFIG_PCI_SYS_MEM_PHYS) && \
 765         defined(CONFIG_PCI_SYS_MEM_SIZE)
 766         /* System memory space */
 767         pci_set_region(hose->regions + reg_num++,
 768                        CONFIG_PCI_SYS_MEM_BUS,
 769                        CONFIG_PCI_SYS_MEM_PHYS,
 770                        CONFIG_PCI_SYS_MEM_SIZE,
 771                        PCI_REGION_MEM | PCI_REGION_SYS_MEMORY );
 772 #endif
 773
 774         hose->region_count = reg_num;
 775
 776         pci_setup_indirect(hose, PCIL0_CFGADR, PCIL0_CFGDATA);
 777
 778         /* Let board change/modify hose & do initial checks */
 779         if (pci_pre_init(hose) == 0) {
 780                 printf("PCI: Board-specific initialization failed.\n");
 781                 printf("PCI: Configuration aborted.\n");
 782                 return -1;
 783         }
 784
 785         pci_register_hose( hose );
 786
 787         /*--------------------------------------------------------------------------+
 788          * PCI target init
 789          *--------------------------------------------------------------------------*/
 790 #if defined(CONFIG_SYS_PCI_TARGET_INIT)
 791         pci_target_init(hose);                /* Let board setup pci target */
 792 #else
 793         out16r( PCIL0_SBSYSVID, CONFIG_SYS_PCI_SUBSYS_VENDORID );
 794         out16r( PCIL0_SBSYSID, CONFIG_SYS_PCI_SUBSYS_ID );
 795         out16r( PCIL0_CLS, 0x00060000 ); /* Bridge, host bridge */
 796 #endif
 797
 798 #if defined(CONFIG_440GX) || defined(CONFIG_440SPE) || \
 799     defined(CONFIG_460EX) || defined(CONFIG_460GT)
 800         out32r( PCIL0_BRDGOPT1, 0x04000060 );               /* PLB Rq pri highest   */
 801         out32r( PCIL0_BRDGOPT2, in32(PCIL0_BRDGOPT2) | 0x83 ); /* Enable host config, clear Timeout, ensure int src1  */
 802 #elif defined(PCIL0_BRDGOPT1)
 803         out32r( PCIL0_BRDGOPT1, 0x10000060 );               /* PLB Rq pri highest   */
 804         out32r( PCIL0_BRDGOPT2, in32(PCIL0_BRDGOPT2) | 1 ); /* Enable host config   */
 805 #endif
 806
 807         /*--------------------------------------------------------------------------+
 808          * PCI master init: default is one 256MB region for PCI memory:
 809          * 0x3_00000000 - 0x3_0FFFFFFF  ==> CONFIG_SYS_PCI_MEMBASE
 810          *--------------------------------------------------------------------------*/
 811 #if defined(CONFIG_SYS_PCI_MASTER_INIT)
 812         pci_master_init(hose);          /* Let board setup pci master */
 813 #else
 814         out32r( PCIL0_POM0SA, 0 ); /* disable */
 815         out32r( PCIL0_POM1SA, 0 ); /* disable */
 816         out32r( PCIL0_POM2SA, 0 ); /* disable */
 817 #if defined(CONFIG_440SPE)
 818         out32r( PCIL0_POM0LAL, 0x10000000 );
 819         out32r( PCIL0_POM0LAH, 0x0000000c );
 820 #elif defined(CONFIG_460EX) || defined(CONFIG_460GT)
 821         out32r( PCIL0_POM0LAL, 0x20000000 );
 822         out32r( PCIL0_POM0LAH, 0x0000000c );
 823 #else
 824         out32r( PCIL0_POM0LAL, 0x00000000 );
 825         out32r( PCIL0_POM0LAH, 0x00000003 );
 826 #endif
 827         out32r( PCIL0_POM0PCIAL, CONFIG_SYS_PCI_MEMBASE );
 828         out32r( PCIL0_POM0PCIAH, 0x00000000 );
 829         out32r( PCIL0_POM0SA, 0xf0000001 ); /* 256MB, enabled */
 830         out32r( PCIL0_STS, in32r( PCIL0_STS ) & ~0x0000fff8 );
 831 #endif
 832
 833         /*--------------------------------------------------------------------------+
 834          * PCI host configuration -- we don't make any assumptions here ... the
 835          * _board_must_indicate_ what to do -- there's just too many runtime
 836          * scenarios in environments like cPCI, PPMC, etc. to make a determination
 837          * based on hard-coded values or state of arbiter enable.
 838          *--------------------------------------------------------------------------*/
 839         if (is_pci_host(hose)) {
 840 #ifdef CONFIG_PCI_SCAN_SHOW
 841                 printf("PCI:   Bus Dev VenId DevId Class Int\n");
 842 #endif
 843 #if !defined(CONFIG_440EP) && !defined(CONFIG_440GR) && \
 844     !defined(CONFIG_440EPX) && !defined(CONFIG_440GRX)
 845                 out16r( PCIL0_CMD, in16r( PCIL0_CMD ) | PCI_COMMAND_MASTER);
 846 #endif
 847                 hose->last_busno = pci_hose_scan(hose);
 848         }
 849         return hose->last_busno;
 850 }
 851 #endif
 852
 853 void pci_init_board(void)
 854 {
 855         int busno = 0;
 856
 857         /*
 858          * Only init PCI when either master or target functionality
 859          * is selected.
 860          */
 861 #if defined(CONFIG_SYS_PCI_MASTER_INIT) || defined(CONFIG_SYS_PCI_TARGET_INIT)
 862         busno = pci_440_init(&ppc440_hose);
 863         if (busno < 0)
 864                 return;
 865 #endif
 866 #if (defined(CONFIG_440SPE) || \
 867     defined(CONFIG_460EX) || defined(CONFIG_460GT)) && \
 868     !defined(CONFIG_PCI_DISABLE_PCIE)
 869         pcie_setup_hoses(busno + 1);
 870 #endif
 871 }
 872
 873 #endif /* CONFIG_440 */
 874
 875 #if defined(CONFIG_405EX)
 876 void pci_init_board(void)
 877 {
 878 #ifdef CONFIG_PCI_SCAN_SHOW
 879         printf("PCI:   Bus Dev VenId DevId Class Int\n");
 880 #endif
 881         pcie_setup_hoses(0);
 882 }
 883 #endif /* CONFIG_405EX */
 884
 885 #endif /* CONFIG_PCI */