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Merge git://git.denx.de/u-boot-fsl-qoriq
[people/ms/u-boot.git] / arch / powerpc / cpu / ppc4xx / 4xx_pcie.c
1 /*
2 * (C) Copyright 2006 - 2008
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * Copyright (c) 2005 Cisco Systems. All rights reserved.
6 * Roland Dreier <rolandd@cisco.com>
7 *
8 * SPDX-License-Identifier: GPL-2.0+
9 */
10
11 /* define DEBUG for debugging output (obviously ;-)) */
12 #if 0
13 #define DEBUG
14 #endif
15
16 #include <common.h>
17 #include <pci.h>
18 #include <asm/ppc4xx.h>
19 #include <asm/processor.h>
20 #include <asm/io.h>
21 #include <linux/errno.h>
22
23 #if (defined(CONFIG_440SPE) || defined(CONFIG_405EX) || \
24 defined(CONFIG_460EX) || defined(CONFIG_460GT)) && \
25 defined(CONFIG_PCI) && !defined(CONFIG_PCI_DISABLE_PCIE)
26
27 #include <asm/4xx_pcie.h>
28
29 enum {
30 PTYPE_ENDPOINT = 0x0,
31 PTYPE_LEGACY_ENDPOINT = 0x1,
32 PTYPE_ROOT_PORT = 0x4,
33
34 LNKW_X1 = 0x1,
35 LNKW_X4 = 0x4,
36 LNKW_X8 = 0x8
37 };
38
39 static struct pci_controller pcie_hose[CONFIG_SYS_PCIE_NR_PORTS];
40
41 /*
42 * Per default, all cards are present, so we need to check if the
43 * link comes up.
44 */
45 int __board_pcie_card_present(int port)
46 {
47 return 1;
48 }
49 int board_pcie_card_present(int port)
50 __attribute__((weak, alias("__board_pcie_card_present")));
51
52 /*
53 * Some boards have runtime detection of the first and last PCIe
54 * slot used, so let's provide weak default functions for the
55 * common version.
56 */
57 int __board_pcie_first(void)
58 {
59 return 0;
60 }
61 int board_pcie_first(void)
62 __attribute__((weak, alias("__board_pcie_first")));
63
64 int __board_pcie_last(void)
65 {
66 return CONFIG_SYS_PCIE_NR_PORTS - 1;
67 }
68 int board_pcie_last(void)
69 __attribute__((weak, alias("__board_pcie_last")));
70
71 void __board_pcie_setup_port(int port, int rootpoint)
72 {
73 /* noting in this weak default implementation */
74 }
75 void board_pcie_setup_port(int port, int rootpoint)
76 __attribute__((weak, alias("__board_pcie_setup_port")));
77
78 void pcie_setup_hoses(int busno)
79 {
80 struct pci_controller *hose;
81 int i, bus;
82 int ret = 0;
83 char *env;
84 unsigned int delay;
85 int first = board_pcie_first();
86 int last = board_pcie_last();
87
88 /*
89 * Assume we're called after the PCI(X) hose(s) are initialized,
90 * which takes bus ID 0... and therefore start numbering PCIe's
91 * from the next number.
92 */
93 bus = busno;
94
95 for (i = first; i <= last; i++) {
96 /*
97 * Some boards (e.g. Katmai) can detects via hardware
98 * if a PCIe card is plugged, so let's check this.
99 */
100 if (!board_pcie_card_present(i))
101 continue;
102
103 if (is_end_point(i)) {
104 board_pcie_setup_port(i, 0);
105 ret = ppc4xx_init_pcie_endport(i);
106 } else {
107 board_pcie_setup_port(i, 1);
108 ret = ppc4xx_init_pcie_rootport(i);
109 }
110 if (ret == -ENODEV)
111 continue;
112 if (ret) {
113 printf("PCIE%d: initialization as %s failed\n", i,
114 is_end_point(i) ? "endpoint" : "root-complex");
115 continue;
116 }
117
118 hose = &pcie_hose[i];
119 hose->first_busno = bus;
120 hose->last_busno = bus;
121 hose->current_busno = bus;
122
123 /* setup mem resource */
124 pci_set_region(hose->regions + 0,
125 CONFIG_SYS_PCIE_MEMBASE + i * CONFIG_SYS_PCIE_MEMSIZE,
126 CONFIG_SYS_PCIE_MEMBASE + i * CONFIG_SYS_PCIE_MEMSIZE,
127 CONFIG_SYS_PCIE_MEMSIZE,
128 PCI_REGION_MEM);
129 hose->region_count = 1;
130 pci_register_hose(hose);
131
132 if (is_end_point(i)) {
133 ppc4xx_setup_pcie_endpoint(hose, i);
134 /*
135 * Reson for no scanning is endpoint can not generate
136 * upstream configuration accesses.
137 */
138 } else {
139 ppc4xx_setup_pcie_rootpoint(hose, i);
140 env = getenv ("pciscandelay");
141 if (env != NULL) {
142 delay = simple_strtoul(env, NULL, 10);
143 if (delay > 5)
144 printf("Warning, expect noticable delay before "
145 "PCIe scan due to 'pciscandelay' value!\n");
146 mdelay(delay * 1000);
147 }
148
149 /*
150 * Config access can only go down stream
151 */
152 hose->last_busno = pci_hose_scan(hose);
153 bus = hose->last_busno + 1;
154 }
155 }
156 }
157
158 static int validate_endpoint(struct pci_controller *hose)
159 {
160 if (hose->cfg_data == (u8 *)CONFIG_SYS_PCIE0_CFGBASE)
161 return (is_end_point(0));
162 else if (hose->cfg_data == (u8 *)CONFIG_SYS_PCIE1_CFGBASE)
163 return (is_end_point(1));
164 #if CONFIG_SYS_PCIE_NR_PORTS > 2
165 else if (hose->cfg_data == (u8 *)CONFIG_SYS_PCIE2_CFGBASE)
166 return (is_end_point(2));
167 #endif
168
169 return 0;
170 }
171
172 static u8* pcie_get_base(struct pci_controller *hose, unsigned int devfn)
173 {
174 u8 *base = (u8*)hose->cfg_data;
175
176 /* use local configuration space for the first bus */
177 if (PCI_BUS(devfn) == 0) {
178 if (hose->cfg_data == (u8*)CONFIG_SYS_PCIE0_CFGBASE)
179 base = (u8*)CONFIG_SYS_PCIE0_XCFGBASE;
180 if (hose->cfg_data == (u8*)CONFIG_SYS_PCIE1_CFGBASE)
181 base = (u8*)CONFIG_SYS_PCIE1_XCFGBASE;
182 #if CONFIG_SYS_PCIE_NR_PORTS > 2
183 if (hose->cfg_data == (u8*)CONFIG_SYS_PCIE2_CFGBASE)
184 base = (u8*)CONFIG_SYS_PCIE2_XCFGBASE;
185 #endif
186 }
187
188 return base;
189 }
190
191 static void pcie_dmer_disable(void)
192 {
193 mtdcr (DCRN_PEGPL_CFG(DCRN_PCIE0_BASE),
194 mfdcr (DCRN_PEGPL_CFG(DCRN_PCIE0_BASE)) | GPL_DMER_MASK_DISA);
195 mtdcr (DCRN_PEGPL_CFG(DCRN_PCIE1_BASE),
196 mfdcr (DCRN_PEGPL_CFG(DCRN_PCIE1_BASE)) | GPL_DMER_MASK_DISA);
197 #if CONFIG_SYS_PCIE_NR_PORTS > 2
198 mtdcr (DCRN_PEGPL_CFG(DCRN_PCIE2_BASE),
199 mfdcr (DCRN_PEGPL_CFG(DCRN_PCIE2_BASE)) | GPL_DMER_MASK_DISA);
200 #endif
201 }
202
203 static void pcie_dmer_enable(void)
204 {
205 mtdcr (DCRN_PEGPL_CFG (DCRN_PCIE0_BASE),
206 mfdcr (DCRN_PEGPL_CFG(DCRN_PCIE0_BASE)) & ~GPL_DMER_MASK_DISA);
207 mtdcr (DCRN_PEGPL_CFG (DCRN_PCIE1_BASE),
208 mfdcr (DCRN_PEGPL_CFG(DCRN_PCIE1_BASE)) & ~GPL_DMER_MASK_DISA);
209 #if CONFIG_SYS_PCIE_NR_PORTS > 2
210 mtdcr (DCRN_PEGPL_CFG (DCRN_PCIE2_BASE),
211 mfdcr (DCRN_PEGPL_CFG(DCRN_PCIE2_BASE)) & ~GPL_DMER_MASK_DISA);
212 #endif
213 }
214
215 static int pcie_read_config(struct pci_controller *hose, unsigned int devfn,
216 int offset, int len, u32 *val) {
217
218 *val = 0;
219
220 if (validate_endpoint(hose))
221 return 0; /* No upstream config access */
222
223 /*
224 * Bus numbers are relative to hose->first_busno
225 */
226 devfn -= PCI_BDF(hose->first_busno, 0, 0);
227
228 /*
229 * NOTICE: configuration space ranges are currenlty mapped only for
230 * the first 16 buses, so such limit must be imposed. In case more
231 * buses are required the TLB settings in board/amcc/<board>/init.S
232 * need to be altered accordingly (one bus takes 1 MB of memory space).
233 */
234 if (PCI_BUS(devfn) >= 16)
235 return 0;
236
237 /*
238 * Only single device/single function is supported for the primary and
239 * secondary buses of the 440SPe host bridge.
240 */
241 if ((!((PCI_FUNC(devfn) == 0) && (PCI_DEV(devfn) == 0))) &&
242 ((PCI_BUS(devfn) == 0) || (PCI_BUS(devfn) == 1)))
243 return 0;
244
245 pcie_get_base(hose, devfn);
246 offset += devfn << 4;
247
248 /*
249 * Reading from configuration space of non-existing device can
250 * generate transaction errors. For the read duration we suppress
251 * assertion of machine check exceptions to avoid those.
252 */
253 pcie_dmer_disable ();
254
255 debug("%s: cfg_data=%p offset=%08x\n", __func__,
256 hose->cfg_data, offset);
257 switch (len) {
258 case 1:
259 *val = in_8(hose->cfg_data + offset);
260 break;
261 case 2:
262 *val = in_le16((u16 *)(hose->cfg_data + offset));
263 break;
264 default:
265 *val = in_le32((u32*)(hose->cfg_data + offset));
266 break;
267 }
268
269 pcie_dmer_enable ();
270
271 return 0;
272 }
273
274 static int pcie_write_config(struct pci_controller *hose, unsigned int devfn,
275 int offset, int len, u32 val) {
276
277 if (validate_endpoint(hose))
278 return 0; /* No upstream config access */
279
280 /*
281 * Bus numbers are relative to hose->first_busno
282 */
283 devfn -= PCI_BDF(hose->first_busno, 0, 0);
284
285 /*
286 * Same constraints as in pcie_read_config().
287 */
288 if (PCI_BUS(devfn) >= 16)
289 return 0;
290
291 if ((!((PCI_FUNC(devfn) == 0) && (PCI_DEV(devfn) == 0))) &&
292 ((PCI_BUS(devfn) == 0) || (PCI_BUS(devfn) == 1)))
293 return 0;
294
295 pcie_get_base(hose, devfn);
296 offset += devfn << 4;
297
298 /*
299 * Suppress MCK exceptions, similar to pcie_read_config()
300 */
301 pcie_dmer_disable ();
302
303 switch (len) {
304 case 1:
305 out_8(hose->cfg_data + offset, val);
306 break;
307 case 2:
308 out_le16((u16 *)(hose->cfg_data + offset), val);
309 break;
310 default:
311 out_le32((u32 *)(hose->cfg_data + offset), val);
312 break;
313 }
314
315 pcie_dmer_enable ();
316
317 return 0;
318 }
319
320 int pcie_read_config_byte(struct pci_controller *hose,pci_dev_t dev,int offset,u8 *val)
321 {
322 u32 v;
323 int rv;
324
325 rv = pcie_read_config(hose, dev, offset, 1, &v);
326 *val = (u8)v;
327 return rv;
328 }
329
330 int pcie_read_config_word(struct pci_controller *hose,pci_dev_t dev,int offset,u16 *val)
331 {
332 u32 v;
333 int rv;
334
335 rv = pcie_read_config(hose, dev, offset, 2, &v);
336 *val = (u16)v;
337 return rv;
338 }
339
340 int pcie_read_config_dword(struct pci_controller *hose,pci_dev_t dev,int offset,u32 *val)
341 {
342 u32 v;
343 int rv;
344
345 rv = pcie_read_config(hose, dev, offset, 3, &v);
346 *val = (u32)v;
347 return rv;
348 }
349
350 int pcie_write_config_byte(struct pci_controller *hose,pci_dev_t dev,int offset,u8 val)
351 {
352 return pcie_write_config(hose,(u32)dev,offset,1,val);
353 }
354
355 int pcie_write_config_word(struct pci_controller *hose,pci_dev_t dev,int offset,u16 val)
356 {
357 return pcie_write_config(hose,(u32)dev,offset,2,(u32 )val);
358 }
359
360 int pcie_write_config_dword(struct pci_controller *hose,pci_dev_t dev,int offset,u32 val)
361 {
362 return pcie_write_config(hose,(u32)dev,offset,3,(u32 )val);
363 }
364
365 #if defined(CONFIG_440SPE)
366 static void ppc4xx_setup_utl(u32 port) {
367
368 volatile void *utl_base = NULL;
369
370 /*
371 * Map UTL registers
372 */
373 switch (port) {
374 case 0:
375 mtdcr(DCRN_PEGPL_REGBAH(PCIE0), 0x0000000c);
376 mtdcr(DCRN_PEGPL_REGBAL(PCIE0), 0x20000000);
377 mtdcr(DCRN_PEGPL_REGMSK(PCIE0), 0x00007001);
378 mtdcr(DCRN_PEGPL_SPECIAL(PCIE0), 0x68782800);
379 break;
380
381 case 1:
382 mtdcr(DCRN_PEGPL_REGBAH(PCIE1), 0x0000000c);
383 mtdcr(DCRN_PEGPL_REGBAL(PCIE1), 0x20001000);
384 mtdcr(DCRN_PEGPL_REGMSK(PCIE1), 0x00007001);
385 mtdcr(DCRN_PEGPL_SPECIAL(PCIE1), 0x68782800);
386 break;
387
388 case 2:
389 mtdcr(DCRN_PEGPL_REGBAH(PCIE2), 0x0000000c);
390 mtdcr(DCRN_PEGPL_REGBAL(PCIE2), 0x20002000);
391 mtdcr(DCRN_PEGPL_REGMSK(PCIE2), 0x00007001);
392 mtdcr(DCRN_PEGPL_SPECIAL(PCIE2), 0x68782800);
393 break;
394 }
395 utl_base = (unsigned int *)(CONFIG_SYS_PCIE_BASE + 0x1000 * port);
396
397 /*
398 * Set buffer allocations and then assert VRB and TXE.
399 */
400 out_be32(utl_base + PEUTL_OUTTR, 0x08000000);
401 out_be32(utl_base + PEUTL_INTR, 0x02000000);
402 out_be32(utl_base + PEUTL_OPDBSZ, 0x10000000);
403 out_be32(utl_base + PEUTL_PBBSZ, 0x53000000);
404 out_be32(utl_base + PEUTL_IPHBSZ, 0x08000000);
405 out_be32(utl_base + PEUTL_IPDBSZ, 0x10000000);
406 out_be32(utl_base + PEUTL_RCIRQEN, 0x00f00000);
407 out_be32(utl_base + PEUTL_PCTL, 0x80800066);
408 }
409
410 static int check_error(void)
411 {
412 u32 valPE0, valPE1, valPE2;
413 int err = 0;
414
415 /* SDR0_PEGPLLLCT1 reset */
416 if (!(valPE0 = SDR_READ(PESDR0_PLLLCT1) & 0x01000000))
417 printf("PCIE: SDR0_PEGPLLLCT1 reset error 0x%x\n", valPE0);
418
419 valPE0 = SDR_READ(PESDR0_RCSSET);
420 valPE1 = SDR_READ(PESDR1_RCSSET);
421 valPE2 = SDR_READ(PESDR2_RCSSET);
422
423 /* SDR0_PExRCSSET rstgu */
424 if (!(valPE0 & 0x01000000) ||
425 !(valPE1 & 0x01000000) ||
426 !(valPE2 & 0x01000000)) {
427 printf("PCIE: SDR0_PExRCSSET rstgu error\n");
428 err = -1;
429 }
430
431 /* SDR0_PExRCSSET rstdl */
432 if (!(valPE0 & 0x00010000) ||
433 !(valPE1 & 0x00010000) ||
434 !(valPE2 & 0x00010000)) {
435 printf("PCIE: SDR0_PExRCSSET rstdl error\n");
436 err = -1;
437 }
438
439 /* SDR0_PExRCSSET rstpyn */
440 if ((valPE0 & 0x00001000) ||
441 (valPE1 & 0x00001000) ||
442 (valPE2 & 0x00001000)) {
443 printf("PCIE: SDR0_PExRCSSET rstpyn error\n");
444 err = -1;
445 }
446
447 /* SDR0_PExRCSSET hldplb */
448 if ((valPE0 & 0x10000000) ||
449 (valPE1 & 0x10000000) ||
450 (valPE2 & 0x10000000)) {
451 printf("PCIE: SDR0_PExRCSSET hldplb error\n");
452 err = -1;
453 }
454
455 /* SDR0_PExRCSSET rdy */
456 if ((valPE0 & 0x00100000) ||
457 (valPE1 & 0x00100000) ||
458 (valPE2 & 0x00100000)) {
459 printf("PCIE: SDR0_PExRCSSET rdy error\n");
460 err = -1;
461 }
462
463 /* SDR0_PExRCSSET shutdown */
464 if ((valPE0 & 0x00000100) ||
465 (valPE1 & 0x00000100) ||
466 (valPE2 & 0x00000100)) {
467 printf("PCIE: SDR0_PExRCSSET shutdown error\n");
468 err = -1;
469 }
470 return err;
471 }
472
473 /*
474 * Initialize PCI Express core
475 */
476 int ppc4xx_init_pcie(void)
477 {
478 int time_out = 20;
479
480 /* Set PLL clock receiver to LVPECL */
481 SDR_WRITE(PESDR0_PLLLCT1, SDR_READ(PESDR0_PLLLCT1) | 1 << 28);
482
483 if (check_error()) {
484 printf("ERROR: failed to set PCIe reference clock receiver --"
485 "PESDR0_PLLLCT1 = 0x%08x\n", SDR_READ(PESDR0_PLLLCT1));
486
487 return -1;
488 }
489
490 /* Did resistance calibration work? */
491 if (!(SDR_READ(PESDR0_PLLLCT2) & 0x10000)) {
492 printf("ERROR: PCIe resistance calibration failed --"
493 "PESDR0_PLLLCT2 = 0x%08x\n", SDR_READ(PESDR0_PLLLCT2));
494
495 return -1;
496 }
497 /* De-assert reset of PCIe PLL, wait for lock */
498 SDR_WRITE(PESDR0_PLLLCT1, SDR_READ(PESDR0_PLLLCT1) & ~(1 << 24));
499 udelay(300); /* 300 uS is maximum time lock should take */
500
501 while (time_out) {
502 if (!(SDR_READ(PESDR0_PLLLCT3) & 0x10000000)) {
503 time_out--;
504 udelay(20); /* Wait 20 uS more if needed */
505 } else
506 break;
507 }
508 if (!time_out) {
509 printf("ERROR: PCIe PLL VCO output not locked to ref clock --"
510 "PESDR0_PLLLCTS=0x%08x\n", SDR_READ(PESDR0_PLLLCT3));
511
512 return -1;
513 }
514 return 0;
515 }
516 #endif
517
518 #if defined(CONFIG_460EX) || defined(CONFIG_460GT)
519 static void ppc4xx_setup_utl(u32 port)
520 {
521 volatile void *utl_base = NULL;
522
523 /*
524 * Map UTL registers at 0x0801_n000 (4K 0xfff mask) PEGPLn_REGMSK
525 */
526 switch (port) {
527 case 0:
528 mtdcr(DCRN_PEGPL_REGBAH(PCIE0), U64_TO_U32_HIGH(CONFIG_SYS_PCIE0_UTLBASE));
529 mtdcr(DCRN_PEGPL_REGBAL(PCIE0), U64_TO_U32_LOW(CONFIG_SYS_PCIE0_UTLBASE));
530 mtdcr(DCRN_PEGPL_REGMSK(PCIE0), 0x00007001); /* BAM 11100000=4KB */
531 mtdcr(DCRN_PEGPL_SPECIAL(PCIE0), 0);
532 break;
533
534 case 1:
535 mtdcr(DCRN_PEGPL_REGBAH(PCIE1), U64_TO_U32_HIGH(CONFIG_SYS_PCIE0_UTLBASE));
536 mtdcr(DCRN_PEGPL_REGBAL(PCIE1), U64_TO_U32_LOW(CONFIG_SYS_PCIE0_UTLBASE)
537 + 0x1000);
538 mtdcr(DCRN_PEGPL_REGMSK(PCIE1), 0x00007001); /* BAM 11100000=4KB */
539 mtdcr(DCRN_PEGPL_SPECIAL(PCIE1), 0);
540 break;
541 }
542 utl_base = (unsigned int *)(CONFIG_SYS_PCIE_BASE + 0x1000 * port);
543
544 /*
545 * Set buffer allocations and then assert VRB and TXE.
546 */
547 out_be32(utl_base + PEUTL_PBCTL, 0x0800000c); /* PLBME, CRRE */
548 out_be32(utl_base + PEUTL_OUTTR, 0x08000000);
549 out_be32(utl_base + PEUTL_INTR, 0x02000000);
550 out_be32(utl_base + PEUTL_OPDBSZ, 0x04000000); /* OPD = 512 Bytes */
551 out_be32(utl_base + PEUTL_PBBSZ, 0x00000000); /* Max 512 Bytes */
552 out_be32(utl_base + PEUTL_IPHBSZ, 0x02000000);
553 out_be32(utl_base + PEUTL_IPDBSZ, 0x04000000); /* IPD = 512 Bytes */
554 out_be32(utl_base + PEUTL_RCIRQEN, 0x00f00000);
555 out_be32(utl_base + PEUTL_PCTL, 0x80800066); /* VRB,TXE,timeout=default */
556 }
557
558 /*
559 * TODO: double check PCI express SDR based on the latest user manual
560 * Some registers specified here no longer exist.. has to be
561 * updated based on the final EAS spec.
562 */
563 static int check_error(void)
564 {
565 u32 valPE0, valPE1;
566 int err = 0;
567
568 valPE0 = SDR_READ(SDRN_PESDR_RCSSET(0));
569 valPE1 = SDR_READ(SDRN_PESDR_RCSSET(1));
570
571 /* SDR0_PExRCSSET rstgu */
572 if (!(valPE0 & PESDRx_RCSSET_RSTGU) || !(valPE1 & PESDRx_RCSSET_RSTGU)) {
573 printf("PCIE: SDR0_PExRCSSET rstgu error\n");
574 err = -1;
575 }
576
577 /* SDR0_PExRCSSET rstdl */
578 if (!(valPE0 & PESDRx_RCSSET_RSTDL) || !(valPE1 & PESDRx_RCSSET_RSTDL)) {
579 printf("PCIE: SDR0_PExRCSSET rstdl error\n");
580 err = -1;
581 }
582
583 /* SDR0_PExRCSSET rstpyn */
584 if ((valPE0 & PESDRx_RCSSET_RSTPYN) || (valPE1 & PESDRx_RCSSET_RSTPYN)) {
585 printf("PCIE: SDR0_PExRCSSET rstpyn error\n");
586 err = -1;
587 }
588
589 /* SDR0_PExRCSSET hldplb */
590 if ((valPE0 & PESDRx_RCSSET_HLDPLB) || (valPE1 & PESDRx_RCSSET_HLDPLB)) {
591 printf("PCIE: SDR0_PExRCSSET hldplb error\n");
592 err = -1;
593 }
594
595 /* SDR0_PExRCSSET rdy */
596 if ((valPE0 & PESDRx_RCSSET_RDY) || (valPE1 & PESDRx_RCSSET_RDY)) {
597 printf("PCIE: SDR0_PExRCSSET rdy error\n");
598 err = -1;
599 }
600
601 return err;
602 }
603
604 /*
605 * Initialize PCI Express core as described in User Manual
606 * TODO: double check PE SDR PLL Register with the updated user manual.
607 */
608 int ppc4xx_init_pcie(void)
609 {
610 if (check_error())
611 return -1;
612
613 return 0;
614 }
615 #endif /* CONFIG_460EX */
616
617 #if defined(CONFIG_405EX)
618 static void ppc4xx_setup_utl(u32 port)
619 {
620 u32 utl_base;
621
622 /*
623 * Map UTL registers at 0xef4f_n000 (4K 0xfff mask) PEGPLn_REGMSK
624 */
625 switch (port) {
626 case 0:
627 mtdcr(DCRN_PEGPL_REGBAH(PCIE0), 0x00000000);
628 mtdcr(DCRN_PEGPL_REGBAL(PCIE0), CONFIG_SYS_PCIE0_UTLBASE);
629 mtdcr(DCRN_PEGPL_REGMSK(PCIE0), 0x00007001); /* 4k region, valid */
630 mtdcr(DCRN_PEGPL_SPECIAL(PCIE0), 0);
631 break;
632
633 case 1:
634 mtdcr(DCRN_PEGPL_REGBAH(PCIE1), 0x00000000);
635 mtdcr(DCRN_PEGPL_REGBAL(PCIE1), CONFIG_SYS_PCIE1_UTLBASE);
636 mtdcr(DCRN_PEGPL_REGMSK(PCIE1), 0x00007001); /* 4k region, valid */
637 mtdcr(DCRN_PEGPL_SPECIAL(PCIE1), 0);
638
639 break;
640 }
641 utl_base = (port==0) ? CONFIG_SYS_PCIE0_UTLBASE : CONFIG_SYS_PCIE1_UTLBASE;
642
643 /*
644 * Set buffer allocations and then assert VRB and TXE.
645 */
646 out_be32((u32 *)(utl_base + PEUTL_OUTTR), 0x02000000);
647 out_be32((u32 *)(utl_base + PEUTL_INTR), 0x02000000);
648 out_be32((u32 *)(utl_base + PEUTL_OPDBSZ), 0x04000000);
649 out_be32((u32 *)(utl_base + PEUTL_PBBSZ), 0x21000000);
650 out_be32((u32 *)(utl_base + PEUTL_IPHBSZ), 0x02000000);
651 out_be32((u32 *)(utl_base + PEUTL_IPDBSZ), 0x04000000);
652 out_be32((u32 *)(utl_base + PEUTL_RCIRQEN), 0x00f00000);
653 out_be32((u32 *)(utl_base + PEUTL_PCTL), 0x80800066);
654
655 out_be32((u32 *)(utl_base + PEUTL_PBCTL), 0x0800000c);
656 out_be32((u32 *)(utl_base + PEUTL_RCSTA),
657 in_be32((u32 *)(utl_base + PEUTL_RCSTA)) | 0x000040000);
658 }
659
660 int ppc4xx_init_pcie(void)
661 {
662 /*
663 * Nothing to do on 405EX
664 */
665 return 0;
666 }
667 #endif /* CONFIG_405EX */
668
669 /*
670 * Board-specific pcie initialization
671 * Platform code can reimplement ppc4xx_init_pcie_port_hw() if needed
672 */
673
674 /*
675 * Initialize various parts of the PCI Express core for our port:
676 *
677 * - Set as a root port and enable max width
678 * (PXIE0 -> X8, PCIE1 and PCIE2 -> X4).
679 * - Set up UTL configuration.
680 * - Increase SERDES drive strength to levels suggested by AMCC.
681 * - De-assert RSTPYN, RSTDL and RSTGU.
682 *
683 * NOTICE for 440SPE revB chip: PESDRn_UTLSET2 is not set - we leave it
684 * with default setting 0x11310000. The register has new fields,
685 * PESDRn_UTLSET2[LKINE] in particular: clearing it leads to PCIE core
686 * hang.
687 */
688 #if defined(CONFIG_440SPE)
689 int __ppc4xx_init_pcie_port_hw(int port, int rootport)
690 {
691 u32 val = 1 << 24;
692 u32 utlset1;
693
694 if (rootport) {
695 val = PTYPE_ROOT_PORT << 20;
696 utlset1 = 0x21222222;
697 } else {
698 val = PTYPE_LEGACY_ENDPOINT << 20;
699 utlset1 = 0x20222222;
700 }
701
702 if (port == 0)
703 val |= LNKW_X8 << 12;
704 else
705 val |= LNKW_X4 << 12;
706
707 SDR_WRITE(SDRN_PESDR_DLPSET(port), val);
708 SDR_WRITE(SDRN_PESDR_UTLSET1(port), utlset1);
709 if (!ppc440spe_revB())
710 SDR_WRITE(SDRN_PESDR_UTLSET2(port), 0x11000000);
711 SDR_WRITE(SDRN_PESDR_HSSL0SET1(port), 0x35000000);
712 SDR_WRITE(SDRN_PESDR_HSSL1SET1(port), 0x35000000);
713 SDR_WRITE(SDRN_PESDR_HSSL2SET1(port), 0x35000000);
714 SDR_WRITE(SDRN_PESDR_HSSL3SET1(port), 0x35000000);
715 if (port == 0) {
716 SDR_WRITE(PESDR0_HSSL4SET1, 0x35000000);
717 SDR_WRITE(PESDR0_HSSL5SET1, 0x35000000);
718 SDR_WRITE(PESDR0_HSSL6SET1, 0x35000000);
719 SDR_WRITE(PESDR0_HSSL7SET1, 0x35000000);
720 }
721 SDR_WRITE(SDRN_PESDR_RCSSET(port), (SDR_READ(SDRN_PESDR_RCSSET(port)) &
722 ~(1 << 24 | 1 << 16)) | 1 << 12);
723
724 return 0;
725 }
726 #endif /* CONFIG_440SPE */
727
728 #if defined(CONFIG_460EX) || defined(CONFIG_460GT)
729 int __ppc4xx_init_pcie_port_hw(int port, int rootport)
730 {
731 u32 val;
732 u32 utlset1;
733
734 if (rootport)
735 val = PTYPE_ROOT_PORT << 20;
736 else
737 val = PTYPE_LEGACY_ENDPOINT << 20;
738
739 if (port == 0) {
740 val |= LNKW_X1 << 12;
741 utlset1 = 0x20000000;
742 } else {
743 val |= LNKW_X4 << 12;
744 utlset1 = 0x20101101;
745 }
746
747 SDR_WRITE(SDRN_PESDR_DLPSET(port), val);
748 SDR_WRITE(SDRN_PESDR_UTLSET1(port), utlset1);
749 SDR_WRITE(SDRN_PESDR_UTLSET2(port), 0x01210000);
750
751 switch (port) {
752 case 0:
753 SDR_WRITE(PESDR0_L0CDRCTL, 0x00003230);
754 SDR_WRITE(PESDR0_L0DRV, 0x00000130);
755 SDR_WRITE(PESDR0_L0CLK, 0x00000006);
756
757 SDR_WRITE(PESDR0_PHY_CTL_RST,0x10000000);
758 break;
759
760 case 1:
761 SDR_WRITE(PESDR1_L0CDRCTL, 0x00003230);
762 SDR_WRITE(PESDR1_L1CDRCTL, 0x00003230);
763 SDR_WRITE(PESDR1_L2CDRCTL, 0x00003230);
764 SDR_WRITE(PESDR1_L3CDRCTL, 0x00003230);
765 SDR_WRITE(PESDR1_L0DRV, 0x00000130);
766 SDR_WRITE(PESDR1_L1DRV, 0x00000130);
767 SDR_WRITE(PESDR1_L2DRV, 0x00000130);
768 SDR_WRITE(PESDR1_L3DRV, 0x00000130);
769 SDR_WRITE(PESDR1_L0CLK, 0x00000006);
770 SDR_WRITE(PESDR1_L1CLK, 0x00000006);
771 SDR_WRITE(PESDR1_L2CLK, 0x00000006);
772 SDR_WRITE(PESDR1_L3CLK, 0x00000006);
773
774 SDR_WRITE(PESDR1_PHY_CTL_RST,0x10000000);
775 break;
776 }
777
778 SDR_WRITE(SDRN_PESDR_RCSSET(port), SDR_READ(SDRN_PESDR_RCSSET(port)) |
779 (PESDRx_RCSSET_RSTGU | PESDRx_RCSSET_RSTPYN));
780
781 /* Poll for PHY reset */
782 switch (port) {
783 case 0:
784 while (!(SDR_READ(PESDR0_RSTSTA) & 0x1))
785 udelay(10);
786 break;
787 case 1:
788 while (!(SDR_READ(PESDR1_RSTSTA) & 0x1))
789 udelay(10);
790 break;
791 }
792
793 SDR_WRITE(SDRN_PESDR_RCSSET(port),
794 (SDR_READ(SDRN_PESDR_RCSSET(port)) &
795 ~(PESDRx_RCSSET_RSTGU | PESDRx_RCSSET_RSTDL)) |
796 PESDRx_RCSSET_RSTPYN);
797
798 return 0;
799 }
800 #endif /* CONFIG_440SPE */
801
802 #if defined(CONFIG_405EX)
803 int __ppc4xx_init_pcie_port_hw(int port, int rootport)
804 {
805 u32 val;
806
807 if (rootport)
808 val = 0x00401000;
809 else
810 val = 0x00101000;
811
812 SDR_WRITE(SDRN_PESDR_DLPSET(port), val);
813 SDR_WRITE(SDRN_PESDR_UTLSET1(port), 0x00000000);
814 SDR_WRITE(SDRN_PESDR_UTLSET2(port), 0x01010000);
815 SDR_WRITE(SDRN_PESDR_PHYSET1(port), 0x720F0000);
816 SDR_WRITE(SDRN_PESDR_PHYSET2(port), 0x70600003);
817
818 /* Assert the PE0_PHY reset */
819 SDR_WRITE(SDRN_PESDR_RCSSET(port), 0x01010000);
820 udelay(1000);
821
822 /* deassert the PE0_hotreset */
823 if (is_end_point(port))
824 SDR_WRITE(SDRN_PESDR_RCSSET(port), 0x01111000);
825 else
826 SDR_WRITE(SDRN_PESDR_RCSSET(port), 0x01101000);
827
828 /* poll for phy !reset */
829 while (!(SDR_READ(SDRN_PESDR_PHYSTA(port)) & 0x00001000))
830 ;
831
832 /* deassert the PE0_gpl_utl_reset */
833 SDR_WRITE(SDRN_PESDR_RCSSET(port), 0x00101000);
834
835 if (port == 0)
836 mtdcr(DCRN_PEGPL_CFG(PCIE0), 0x10000000); /* guarded on */
837 else
838 mtdcr(DCRN_PEGPL_CFG(PCIE1), 0x10000000); /* guarded on */
839
840 return 0;
841 }
842 #endif /* CONFIG_405EX */
843
844 int ppc4xx_init_pcie_port_hw(int port, int rootport)
845 __attribute__((weak, alias("__ppc4xx_init_pcie_port_hw")));
846
847 /*
848 * We map PCI Express configuration access into the 512MB regions
849 *
850 * NOTICE: revB is very strict about PLB real addressess and ranges to
851 * be mapped for config space; it seems to only work with d_nnnn_nnnn
852 * range (hangs the core upon config transaction attempts when set
853 * otherwise) while revA uses c_nnnn_nnnn.
854 *
855 * For 440SPe revA:
856 * PCIE0: 0xc_4000_0000
857 * PCIE1: 0xc_8000_0000
858 * PCIE2: 0xc_c000_0000
859 *
860 * For 440SPe revB:
861 * PCIE0: 0xd_0000_0000
862 * PCIE1: 0xd_2000_0000
863 * PCIE2: 0xd_4000_0000
864 *
865 * For 405EX:
866 * PCIE0: 0xa000_0000
867 * PCIE1: 0xc000_0000
868 *
869 * For 460EX/GT:
870 * PCIE0: 0xd_0000_0000
871 * PCIE1: 0xd_2000_0000
872 */
873 static inline u64 ppc4xx_get_cfgaddr(int port)
874 {
875 #if defined(CONFIG_405EX)
876 if (port == 0)
877 return (u64)CONFIG_SYS_PCIE0_CFGBASE;
878 else
879 return (u64)CONFIG_SYS_PCIE1_CFGBASE;
880 #endif
881 #if defined(CONFIG_440SPE)
882 if (ppc440spe_revB()) {
883 switch (port) {
884 default: /* to satisfy compiler */
885 case 0:
886 return 0x0000000d00000000ULL;
887 case 1:
888 return 0x0000000d20000000ULL;
889 case 2:
890 return 0x0000000d40000000ULL;
891 }
892 } else {
893 switch (port) {
894 default: /* to satisfy compiler */
895 case 0:
896 return 0x0000000c40000000ULL;
897 case 1:
898 return 0x0000000c80000000ULL;
899 case 2:
900 return 0x0000000cc0000000ULL;
901 }
902 }
903 #endif
904 #if defined(CONFIG_460EX) || defined(CONFIG_460GT)
905 if (port == 0)
906 return 0x0000000d00000000ULL;
907 else
908 return 0x0000000d20000000ULL;
909 #endif
910 }
911
912 /*
913 * 4xx boards as endpoint and root point setup
914 * and
915 * testing inbound and out bound windows
916 *
917 * 4xx boards can be plugged into another 4xx boards or you can get PCI-E
918 * cable which can be used to setup loop back from one port to another port.
919 * Please rememeber that unless there is a endpoint plugged in to root port it
920 * will not initialize. It is the same in case of endpoint , unless there is
921 * root port attached it will not initialize.
922 *
923 * In this release of software all the PCI-E ports are configured as either
924 * endpoint or rootpoint.In future we will have support for selective ports
925 * setup as endpoint and root point in single board.
926 *
927 * Once your board came up as root point , you can verify by reading
928 * /proc/bus/pci/devices. Where you can see the configuration registers
929 * of endpoint device attached to the port.
930 *
931 * Enpoint cofiguration can be verified by connecting 4xx board to any
932 * host or another 4xx board. Then try to scan the device. In case of
933 * linux use "lspci" or appripriate os command.
934 *
935 * How do I verify the inbound and out bound windows ? (4xx to 4xx)
936 * in this configuration inbound and outbound windows are setup to access
937 * sram memroy area. SRAM is at 0x4 0000 0000 , on PLB bus. This address
938 * is mapped at 0x90000000. From u-boot prompt write data 0xb000 0000,
939 * This is waere your POM(PLB out bound memory window) mapped. then
940 * read the data from other 4xx board's u-boot prompt at address
941 * 0x9000 0000(SRAM). Data should match.
942 * In case of inbound , write data to u-boot command prompt at 0xb000 0000
943 * which is mapped to 0x4 0000 0000. Now on rootpoint yucca u-boot prompt check
944 * data at 0x9000 0000(SRAM).Data should match.
945 */
946 int ppc4xx_init_pcie_port(int port, int rootport)
947 {
948 static int core_init;
949 volatile u32 val = 0;
950 int attempts;
951 u64 addr;
952 u32 low, high;
953
954 if (!core_init) {
955 if (ppc4xx_init_pcie())
956 return -1;
957 ++core_init;
958 }
959
960 /*
961 * Initialize various parts of the PCI Express core for our port
962 */
963 ppc4xx_init_pcie_port_hw(port, rootport);
964
965 /*
966 * Notice: the following delay has critical impact on device
967 * initialization - if too short (<50ms) the link doesn't get up.
968 */
969 mdelay(100);
970
971 val = SDR_READ(SDRN_PESDR_RCSSTS(port));
972 if (val & (1 << 20)) {
973 printf("PCIE%d: PGRST failed %08x\n", port, val);
974 return -1;
975 }
976
977 /*
978 * Verify link is up
979 */
980 val = SDR_READ(SDRN_PESDR_LOOP(port));
981 if (!(val & 0x00001000)) {
982 printf("PCIE%d: link is not up.\n", port);
983 return -ENODEV;
984 }
985
986 /*
987 * Setup UTL registers - but only on revA!
988 * We use default settings for revB chip.
989 */
990 if (!ppc440spe_revB())
991 ppc4xx_setup_utl(port);
992
993 /*
994 * We map PCI Express configuration access into the 512MB regions
995 */
996 addr = ppc4xx_get_cfgaddr(port);
997 low = U64_TO_U32_LOW(addr);
998 high = U64_TO_U32_HIGH(addr);
999
1000 switch (port) {
1001 case 0:
1002 mtdcr(DCRN_PEGPL_CFGBAH(PCIE0), high);
1003 mtdcr(DCRN_PEGPL_CFGBAL(PCIE0), low);
1004 mtdcr(DCRN_PEGPL_CFGMSK(PCIE0), 0xe0000001); /* 512MB region, valid */
1005 break;
1006 case 1:
1007 mtdcr(DCRN_PEGPL_CFGBAH(PCIE1), high);
1008 mtdcr(DCRN_PEGPL_CFGBAL(PCIE1), low);
1009 mtdcr(DCRN_PEGPL_CFGMSK(PCIE1), 0xe0000001); /* 512MB region, valid */
1010 break;
1011 #if CONFIG_SYS_PCIE_NR_PORTS > 2
1012 case 2:
1013 mtdcr(DCRN_PEGPL_CFGBAH(PCIE2), high);
1014 mtdcr(DCRN_PEGPL_CFGBAL(PCIE2), low);
1015 mtdcr(DCRN_PEGPL_CFGMSK(PCIE2), 0xe0000001); /* 512MB region, valid */
1016 break;
1017 #endif
1018 }
1019
1020 /*
1021 * Check for VC0 active and assert RDY.
1022 */
1023 attempts = 10;
1024 while(!(SDR_READ(SDRN_PESDR_RCSSTS(port)) & (1 << 16))) {
1025 if (!(attempts--)) {
1026 printf("PCIE%d: VC0 not active\n", port);
1027 return -1;
1028 }
1029 mdelay(1000);
1030 }
1031 SDR_WRITE(SDRN_PESDR_RCSSET(port),
1032 SDR_READ(SDRN_PESDR_RCSSET(port)) | 1 << 20);
1033 mdelay(100);
1034
1035 return 0;
1036 }
1037
1038 int ppc4xx_init_pcie_rootport(int port)
1039 {
1040 return ppc4xx_init_pcie_port(port, 1);
1041 }
1042
1043 int ppc4xx_init_pcie_endport(int port)
1044 {
1045 return ppc4xx_init_pcie_port(port, 0);
1046 }
1047
1048 void ppc4xx_setup_pcie_rootpoint(struct pci_controller *hose, int port)
1049 {
1050 volatile void *mbase = NULL;
1051
1052 pci_set_ops(hose,
1053 pcie_read_config_byte,
1054 pcie_read_config_word,
1055 pcie_read_config_dword,
1056 pcie_write_config_byte,
1057 pcie_write_config_word,
1058 pcie_write_config_dword);
1059
1060 switch (port) {
1061 case 0:
1062 mbase = (u32 *)CONFIG_SYS_PCIE0_XCFGBASE;
1063 hose->cfg_data = (u8 *)CONFIG_SYS_PCIE0_CFGBASE;
1064 break;
1065 case 1:
1066 mbase = (u32 *)CONFIG_SYS_PCIE1_XCFGBASE;
1067 hose->cfg_data = (u8 *)CONFIG_SYS_PCIE1_CFGBASE;
1068 break;
1069 #if CONFIG_SYS_PCIE_NR_PORTS > 2
1070 case 2:
1071 mbase = (u32 *)CONFIG_SYS_PCIE2_XCFGBASE;
1072 hose->cfg_data = (u8 *)CONFIG_SYS_PCIE2_CFGBASE;
1073 break;
1074 #endif
1075 }
1076
1077 /*
1078 * Set bus numbers on our root port
1079 */
1080 out_8((u8 *)mbase + PCI_PRIMARY_BUS, 0);
1081 out_8((u8 *)mbase + PCI_SECONDARY_BUS, 1);
1082 out_8((u8 *)mbase + PCI_SUBORDINATE_BUS, 1);
1083
1084 /*
1085 * Set up outbound translation to hose->mem_space from PLB
1086 * addresses at an offset of 0xd_0000_0000. We set the low
1087 * bits of the mask to 11 to turn off splitting into 8
1088 * subregions and to enable the outbound translation.
1089 */
1090 out_le32(mbase + PECFG_POM0LAH, 0x00000000);
1091 out_le32(mbase + PECFG_POM0LAL, CONFIG_SYS_PCIE_MEMBASE +
1092 port * CONFIG_SYS_PCIE_MEMSIZE);
1093 debug("PECFG_POM0LA=%08x.%08x\n", in_le32(mbase + PECFG_POM0LAH),
1094 in_le32(mbase + PECFG_POM0LAL));
1095
1096 switch (port) {
1097 case 0:
1098 mtdcr(DCRN_PEGPL_OMR1BAH(PCIE0), CONFIG_SYS_PCIE_ADDR_HIGH);
1099 mtdcr(DCRN_PEGPL_OMR1BAL(PCIE0), CONFIG_SYS_PCIE_MEMBASE +
1100 port * CONFIG_SYS_PCIE_MEMSIZE);
1101 mtdcr(DCRN_PEGPL_OMR1MSKH(PCIE0), 0x7fffffff);
1102 mtdcr(DCRN_PEGPL_OMR1MSKL(PCIE0),
1103 ~(CONFIG_SYS_PCIE_MEMSIZE - 1) | 3);
1104 debug("0:PEGPL_OMR1BA=%08x.%08x MSK=%08x.%08x\n",
1105 mfdcr(DCRN_PEGPL_OMR1BAH(PCIE0)),
1106 mfdcr(DCRN_PEGPL_OMR1BAL(PCIE0)),
1107 mfdcr(DCRN_PEGPL_OMR1MSKH(PCIE0)),
1108 mfdcr(DCRN_PEGPL_OMR1MSKL(PCIE0)));
1109 break;
1110 case 1:
1111 mtdcr(DCRN_PEGPL_OMR1BAH(PCIE1), CONFIG_SYS_PCIE_ADDR_HIGH);
1112 mtdcr(DCRN_PEGPL_OMR1BAL(PCIE1), CONFIG_SYS_PCIE_MEMBASE +
1113 port * CONFIG_SYS_PCIE_MEMSIZE);
1114 mtdcr(DCRN_PEGPL_OMR1MSKH(PCIE1), 0x7fffffff);
1115 mtdcr(DCRN_PEGPL_OMR1MSKL(PCIE1),
1116 ~(CONFIG_SYS_PCIE_MEMSIZE - 1) | 3);
1117 debug("1:PEGPL_OMR1BA=%08x.%08x MSK=%08x.%08x\n",
1118 mfdcr(DCRN_PEGPL_OMR1BAH(PCIE1)),
1119 mfdcr(DCRN_PEGPL_OMR1BAL(PCIE1)),
1120 mfdcr(DCRN_PEGPL_OMR1MSKH(PCIE1)),
1121 mfdcr(DCRN_PEGPL_OMR1MSKL(PCIE1)));
1122 break;
1123 #if CONFIG_SYS_PCIE_NR_PORTS > 2
1124 case 2:
1125 mtdcr(DCRN_PEGPL_OMR1BAH(PCIE2), CONFIG_SYS_PCIE_ADDR_HIGH);
1126 mtdcr(DCRN_PEGPL_OMR1BAL(PCIE2), CONFIG_SYS_PCIE_MEMBASE +
1127 port * CONFIG_SYS_PCIE_MEMSIZE);
1128 mtdcr(DCRN_PEGPL_OMR1MSKH(PCIE2), 0x7fffffff);
1129 mtdcr(DCRN_PEGPL_OMR1MSKL(PCIE2),
1130 ~(CONFIG_SYS_PCIE_MEMSIZE - 1) | 3);
1131 debug("2:PEGPL_OMR1BA=%08x.%08x MSK=%08x.%08x\n",
1132 mfdcr(DCRN_PEGPL_OMR1BAH(PCIE2)),
1133 mfdcr(DCRN_PEGPL_OMR1BAL(PCIE2)),
1134 mfdcr(DCRN_PEGPL_OMR1MSKH(PCIE2)),
1135 mfdcr(DCRN_PEGPL_OMR1MSKL(PCIE2)));
1136 break;
1137 #endif
1138 }
1139
1140 /* Set up 4GB inbound memory window at 0 */
1141 out_le32(mbase + PCI_BASE_ADDRESS_0, 0);
1142 out_le32(mbase + PCI_BASE_ADDRESS_1, 0);
1143 out_le32(mbase + PECFG_BAR0HMPA, 0x7ffffff);
1144 out_le32(mbase + PECFG_BAR0LMPA, 0);
1145
1146 out_le32(mbase + PECFG_PIM01SAH, 0xffff0000);
1147 out_le32(mbase + PECFG_PIM01SAL, 0x00000000);
1148 out_le32(mbase + PECFG_PIM0LAL, 0);
1149 out_le32(mbase + PECFG_PIM0LAH, 0);
1150 out_le32(mbase + PECFG_PIM1LAL, 0x00000000);
1151 out_le32(mbase + PECFG_PIM1LAH, 0x00000004);
1152 out_le32(mbase + PECFG_PIMEN, 0x1);
1153
1154 /* Enable I/O, Mem, and Busmaster cycles */
1155 out_le16((u16 *)(mbase + PCI_COMMAND),
1156 in_le16((u16 *)(mbase + PCI_COMMAND)) |
1157 PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
1158
1159 /* Set Device and Vendor Id */
1160 out_le16(mbase + 0x200, 0xaaa0 + port);
1161 out_le16(mbase + 0x202, 0xbed0 + port);
1162
1163 /* Set Class Code to PCI-PCI bridge and Revision Id to 1 */
1164 out_le32(mbase + 0x208, 0x06040001);
1165
1166 printf("PCIE%d: successfully set as root-complex\n", port);
1167 }
1168
1169 int ppc4xx_setup_pcie_endpoint(struct pci_controller *hose, int port)
1170 {
1171 volatile void *mbase = NULL;
1172 int attempts = 0;
1173
1174 pci_set_ops(hose,
1175 pcie_read_config_byte,
1176 pcie_read_config_word,
1177 pcie_read_config_dword,
1178 pcie_write_config_byte,
1179 pcie_write_config_word,
1180 pcie_write_config_dword);
1181
1182 switch (port) {
1183 case 0:
1184 mbase = (u32 *)CONFIG_SYS_PCIE0_XCFGBASE;
1185 hose->cfg_data = (u8 *)CONFIG_SYS_PCIE0_CFGBASE;
1186 break;
1187 case 1:
1188 mbase = (u32 *)CONFIG_SYS_PCIE1_XCFGBASE;
1189 hose->cfg_data = (u8 *)CONFIG_SYS_PCIE1_CFGBASE;
1190 break;
1191 #if defined(CONFIG_SYS_PCIE2_CFGBASE)
1192 case 2:
1193 mbase = (u32 *)CONFIG_SYS_PCIE2_XCFGBASE;
1194 hose->cfg_data = (u8 *)CONFIG_SYS_PCIE2_CFGBASE;
1195 break;
1196 #endif
1197 }
1198
1199 /*
1200 * Set up outbound translation to hose->mem_space from PLB
1201 * addresses at an offset of 0xd_0000_0000. We set the low
1202 * bits of the mask to 11 to turn off splitting into 8
1203 * subregions and to enable the outbound translation.
1204 */
1205 out_le32(mbase + PECFG_POM0LAH, 0x00001ff8);
1206 out_le32(mbase + PECFG_POM0LAL, 0x00001000);
1207
1208 switch (port) {
1209 case 0:
1210 mtdcr(DCRN_PEGPL_OMR1BAH(PCIE0), CONFIG_SYS_PCIE_ADDR_HIGH);
1211 mtdcr(DCRN_PEGPL_OMR1BAL(PCIE0), CONFIG_SYS_PCIE_MEMBASE +
1212 port * CONFIG_SYS_PCIE_MEMSIZE);
1213 mtdcr(DCRN_PEGPL_OMR1MSKH(PCIE0), 0x7fffffff);
1214 mtdcr(DCRN_PEGPL_OMR1MSKL(PCIE0),
1215 ~(CONFIG_SYS_PCIE_MEMSIZE - 1) | 3);
1216 break;
1217 case 1:
1218 mtdcr(DCRN_PEGPL_OMR1BAH(PCIE1), CONFIG_SYS_PCIE_ADDR_HIGH);
1219 mtdcr(DCRN_PEGPL_OMR1BAL(PCIE1), CONFIG_SYS_PCIE_MEMBASE +
1220 port * CONFIG_SYS_PCIE_MEMSIZE);
1221 mtdcr(DCRN_PEGPL_OMR1MSKH(PCIE1), 0x7fffffff);
1222 mtdcr(DCRN_PEGPL_OMR1MSKL(PCIE1),
1223 ~(CONFIG_SYS_PCIE_MEMSIZE - 1) | 3);
1224 break;
1225 #if CONFIG_SYS_PCIE_NR_PORTS > 2
1226 case 2:
1227 mtdcr(DCRN_PEGPL_OMR1BAH(PCIE2), CONFIG_SYS_PCIE_ADDR_HIGH);
1228 mtdcr(DCRN_PEGPL_OMR1BAL(PCIE2), CONFIG_SYS_PCIE_MEMBASE +
1229 port * CONFIG_SYS_PCIE_MEMSIZE);
1230 mtdcr(DCRN_PEGPL_OMR1MSKH(PCIE2), 0x7fffffff);
1231 mtdcr(DCRN_PEGPL_OMR1MSKL(PCIE2),
1232 ~(CONFIG_SYS_PCIE_MEMSIZE - 1) | 3);
1233 break;
1234 #endif
1235 }
1236
1237 /* Set up 64MB inbound memory window at 0 */
1238 out_le32(mbase + PCI_BASE_ADDRESS_0, 0);
1239 out_le32(mbase + PCI_BASE_ADDRESS_1, 0);
1240
1241 out_le32(mbase + PECFG_PIM01SAH, 0xffffffff);
1242 out_le32(mbase + PECFG_PIM01SAL, 0xfc000000);
1243
1244 /* Setup BAR0 */
1245 out_le32(mbase + PECFG_BAR0HMPA, 0x7fffffff);
1246 out_le32(mbase + PECFG_BAR0LMPA, 0xfc000000 | PCI_BASE_ADDRESS_MEM_TYPE_64);
1247
1248 /* Disable BAR1 & BAR2 */
1249 out_le32(mbase + PECFG_BAR1MPA, 0);
1250 out_le32(mbase + PECFG_BAR2HMPA, 0);
1251 out_le32(mbase + PECFG_BAR2LMPA, 0);
1252
1253 out_le32(mbase + PECFG_PIM0LAL, U64_TO_U32_LOW(CONFIG_SYS_PCIE_INBOUND_BASE));
1254 out_le32(mbase + PECFG_PIM0LAH, U64_TO_U32_HIGH(CONFIG_SYS_PCIE_INBOUND_BASE));
1255 out_le32(mbase + PECFG_PIMEN, 0x1);
1256
1257 /* Enable I/O, Mem, and Busmaster cycles */
1258 out_le16((u16 *)(mbase + PCI_COMMAND),
1259 in_le16((u16 *)(mbase + PCI_COMMAND)) |
1260 PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
1261 out_le16(mbase + 0x200, 0xcaad); /* Setting vendor ID */
1262 out_le16(mbase + 0x202, 0xfeed); /* Setting device ID */
1263
1264 /* Set Class Code to Processor/PPC */
1265 out_le32(mbase + 0x208, 0x0b200001);
1266
1267 attempts = 10;
1268 while(!(SDR_READ(SDRN_PESDR_RCSSTS(port)) & (1 << 8))) {
1269 if (!(attempts--)) {
1270 printf("PCIE%d: BME not active\n", port);
1271 return -1;
1272 }
1273 mdelay(1000);
1274 }
1275
1276 printf("PCIE%d: successfully set as endpoint\n", port);
1277
1278 return 0;
1279 }
1280 #endif /* CONFIG_440SPE && CONFIG_PCI */
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