arch/powerpc/cpu/ppc4xx/4xx_uart.c

   1 /*
   2  * (C) Copyright 2000-2006
   3  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   4  *
   5  * (C) Copyright 2010
   6  * Stefan Roese, DENX Software Engineering, sr@denx.de.
   7  *
   8  * SPDX-License-Identifier:     GPL-2.0+
   9  */
  10
  11 /*
  12  * This source code is dual-licensed.  You may use it under the terms of the
  13  * GNU General Public License version 2, or under the license below.
  14  *
  15  * This source code has been made available to you by IBM on an AS-IS
  16  * basis.  Anyone receiving this source is licensed under IBM
  17  * copyrights to use it in any way he or she deems fit, including
  18  * copying it, modifying it, compiling it, and redistributing it either
  19  * with or without modifications.  No license under IBM patents or
  20  * patent applications is to be implied by the copyright license.
  21  *
  22  * Any user of this software should understand that IBM cannot provide
  23  * technical support for this software and will not be responsible for
  24  * any consequences resulting from the use of this software.
  25  *
  26  * Any person who transfers this source code or any derivative work
  27  * must include the IBM copyright notice, this paragraph, and the
  28  * preceding two paragraphs in the transferred software.
  29  *
  30  * COPYRIGHT   I B M   CORPORATION 1995
  31  * LICENSED MATERIAL  -  PROGRAM PROPERTY OF I B M
  32  */
  33
  34 #include <common.h>
  35 #include <commproc.h>
  36 #include <asm/processor.h>
  37 #include <asm/io.h>
  38 #include <watchdog.h>
  39 #include <asm/ppc4xx.h>
  40
  41 DECLARE_GLOBAL_DATA_PTR;
  42
  43 #if defined(CONFIG_405GP) || defined(CONFIG_405CR) || \
  44     defined(CONFIG_405EP) || defined(CONFIG_405EZ) || \
  45     defined(CONFIG_405EX) || defined(CONFIG_440)
  46
  47 #if defined(CONFIG_440)
  48
  49 #if defined(CONFIG_440GP)
  50 #define CR0_MASK        0x3fff0000
  51 #define CR0_EXTCLK_ENA  0x00600000
  52 #define CR0_UDIV_POS    16
  53 #define UDIV_SUBTRACT   1
  54 #define UART0_SDR       CPC0_CR0
  55 #define MFREG(a, d)     d = mfdcr(a)
  56 #define MTREG(a, d)     mtdcr(a, d)
  57 #else /* #if defined(CONFIG_440GP) */
  58 /* all other 440 PPC's access clock divider via sdr register */
  59 #define CR0_MASK        0xdfffffff
  60 #define CR0_EXTCLK_ENA  0x00800000
  61 #define CR0_UDIV_POS    0
  62 #define UDIV_SUBTRACT   0
  63 #define UART0_SDR       SDR0_UART0
  64 #define UART1_SDR       SDR0_UART1
  65 #if defined(CONFIG_440EP) || defined(CONFIG_440EPX) || \
  66     defined(CONFIG_440GR) || defined(CONFIG_440GRX) || \
  67     defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
  68     defined(CONFIG_460EX) || defined(CONFIG_460GT)
  69 #define UART2_SDR       SDR0_UART2
  70 #endif
  71 #if defined(CONFIG_440EP) || defined(CONFIG_440EPX) || \
  72     defined(CONFIG_440GR) || defined(CONFIG_440GRX) || \
  73     defined(CONFIG_460EX) || defined(CONFIG_460GT)
  74 #define UART3_SDR       SDR0_UART3
  75 #endif
  76 #define MFREG(a, d)     mfsdr(a, d)
  77 #define MTREG(a, d)     mtsdr(a, d)
  78 #endif /* #if defined(CONFIG_440GP) */
  79 #elif defined(CONFIG_405EP) || defined(CONFIG_405EZ)
  80 #define UCR0_MASK       0x0000007f
  81 #define UCR1_MASK       0x00007f00
  82 #define UCR0_UDIV_POS   0
  83 #define UCR1_UDIV_POS   8
  84 #define UDIV_MAX        127
  85 #elif defined(CONFIG_405EX)
  86 #define MFREG(a, d)     mfsdr(a, d)
  87 #define MTREG(a, d)     mtsdr(a, d)
  88 #define CR0_MASK        0x000000ff
  89 #define CR0_EXTCLK_ENA  0x00800000
  90 #define CR0_UDIV_POS    0
  91 #define UDIV_SUBTRACT   0
  92 #define UART0_SDR       SDR0_UART0
  93 #define UART1_SDR       SDR0_UART1
  94 #else /* CONFIG_405GP || CONFIG_405CR */
  95 #define CR0_MASK        0x00001fff
  96 #define CR0_EXTCLK_ENA  0x000000c0
  97 #define CR0_UDIV_POS    1
  98 #define UDIV_MAX        32
  99 #endif
 100
 101 #if defined(CONFIG_405EP) && defined(CONFIG_SYS_EXT_SERIAL_CLOCK)
 102 #error "External serial clock not supported on AMCC PPC405EP!"
 103 #endif
 104
 105 #if (defined(CONFIG_405EX) || defined(CONFIG_405EZ) ||  \
 106      defined(CONFIG_440)) && !defined(CONFIG_SYS_EXT_SERIAL_CLOCK)
 107 /*
 108  * For some SoC's, the cpu clock is on divider chain A, UART on
 109  * divider chain B ... so cpu clock is irrelevant. Get the
 110  * "optimized" values that are subject to the 1/2 opb clock
 111  * constraint.
 112  */
 113 static u16 serial_bdiv(int baudrate, u32 *udiv)
 114 {
 115         sys_info_t sysinfo;
 116         u32 div;                /* total divisor udiv * bdiv */
 117         u32 umin;               /* minimum udiv */
 118         u16 diff;               /* smallest diff */
 119         u16 idiff;              /* current diff */
 120         u16 ibdiv;              /* current bdiv */
 121         u32 i;
 122         u32 est;                /* current estimate */
 123         u32 max;
 124 #if defined(CONFIG_405EZ)
 125         u32 cpr_pllc;
 126         u32 plloutb;
 127         u32 reg;
 128 #endif
 129
 130         get_sys_info(&sysinfo);
 131
 132 #if defined(CONFIG_405EZ)
 133         /* check the pll feedback source */
 134         mfcpr(CPR0_PLLC, cpr_pllc);
 135         plloutb = ((CONFIG_SYS_CLK_FREQ * ((cpr_pllc & PLLC_SRC_MASK) ?
 136                                            sysinfo.pllFwdDivB : sysinfo.pllFwdDiv) *
 137                     sysinfo.pllFbkDiv) / sysinfo.pllFwdDivB);
 138         div = plloutb / (16 * baudrate); /* total divisor */
 139         umin = (plloutb / get_OPB_freq()) << 1; /* 2 x OPB divisor */
 140         max = 256;                      /* highest possible */
 141 #else /* 405EZ */
 142         div = sysinfo.freqPLB / (16 * baudrate); /* total divisor */
 143         umin = sysinfo.pllOpbDiv << 1;  /* 2 x OPB divisor */
 144         max = 32;                       /* highest possible */
 145 #endif /* 405EZ */
 146
 147         *udiv = diff = max;
 148
 149         /*
 150          * i is the test udiv value -- start with the largest
 151          * possible (max) to minimize serial clock and constrain
 152          * search to umin.
 153          */
 154         for (i = max; i > umin; i--) {
 155                 ibdiv = div / i;
 156                 est = i * ibdiv;
 157                 idiff = (est > div) ? (est - div) : (div - est);
 158                 if (idiff == 0) {
 159                         *udiv = i;
 160                         break;          /* can't do better */
 161                 } else if (idiff < diff) {
 162                         *udiv = i;      /* best so far */
 163                         diff = idiff;   /* update lowest diff*/
 164                 }
 165         }
 166
 167 #if defined(CONFIG_405EZ)
 168         mfcpr(CPR0_PERD0, reg);
 169         reg &= ~0x0000ffff;
 170         reg |= ((*udiv - 0) << 8) | (*udiv - 0);
 171         mtcpr(CPR0_PERD0, reg);
 172 #endif
 173
 174         return div / *udiv;
 175 }
 176 #endif /* #if (defined(CONFIG_405EP) ... */
 177
 178 /*
 179  * This function returns the UART clock used by the common
 180  * NS16550 driver. Additionally the SoC internal divisors for
 181  * optimal UART baudrate are configured.
 182  */
 183 int get_serial_clock(void)
 184 {
 185         u32 clk;
 186         u32 udiv;
 187 #if !defined(CONFIG_405EZ)
 188         u32 reg;
 189 #endif
 190 #if !defined(CONFIG_SYS_EXT_SERIAL_CLOCK)
 191         PPC4xx_SYS_INFO sys_info;
 192 #endif
 193
 194         /*
 195          * Programming of the internal divisors is SoC specific.
 196          * Let's handle this in some #ifdef's for the SoC's.
 197          */
 198
 199 #if defined(CONFIG_405CR) || defined(CONFIG_405GP)
 200         reg = mfdcr(CPC0_CR0) & ~CR0_MASK;
 201 #ifdef CONFIG_SYS_EXT_SERIAL_CLOCK
 202         clk = CONFIG_SYS_EXT_SERIAL_CLOCK;
 203         udiv = 1;
 204         reg |= CR0_EXTCLK_ENA;
 205 #else /* CONFIG_SYS_EXT_SERIAL_CLOCK */
 206         clk = gd->cpu_clk;
 207 #ifdef CONFIG_SYS_405_UART_ERRATA_59
 208         udiv = 31;                      /* Errata 59: stuck at 31 */
 209 #else /* CONFIG_SYS_405_UART_ERRATA_59 */
 210         {
 211                 u32 tmp = CONFIG_SYS_BASE_BAUD * 16;
 212
 213                 udiv = (clk + tmp / 2) / tmp;
 214         }
 215         if (udiv > UDIV_MAX)                    /* max. n bits for udiv */
 216                 udiv = UDIV_MAX;
 217 #endif /* CONFIG_SYS_405_UART_ERRATA_59 */
 218 #endif /* CONFIG_SYS_EXT_SERIAL_CLOCK */
 219         reg |= (udiv - 1) << CR0_UDIV_POS;      /* set the UART divisor */
 220         mtdcr (CPC0_CR0, reg);
 221 #ifdef CONFIG_SYS_EXT_SERIAL_CLOCK
 222         clk = CONFIG_SYS_EXT_SERIAL_CLOCK;
 223 #else
 224         clk = CONFIG_SYS_BASE_BAUD * 16;
 225 #endif
 226 #endif /* CONFIG_405CR */
 227
 228 #if defined(CONFIG_405EP)
 229         {
 230                 u32 tmp = CONFIG_SYS_BASE_BAUD * 16;
 231
 232                 reg = mfdcr(CPC0_UCR) & ~(UCR0_MASK | UCR1_MASK);
 233                 clk = gd->cpu_clk;
 234                 udiv = (clk + tmp / 2) / tmp;
 235                 if (udiv > UDIV_MAX)                    /* max. n bits for udiv */
 236                         udiv = UDIV_MAX;
 237         }
 238         reg |= udiv << UCR0_UDIV_POS;           /* set the UART divisor */
 239         reg |= udiv << UCR1_UDIV_POS;           /* set the UART divisor */
 240         mtdcr(CPC0_UCR, reg);
 241         clk = CONFIG_SYS_BASE_BAUD * 16;
 242 #endif /* CONFIG_405EP */
 243
 244 #if defined(CONFIG_405EX) || defined(CONFIG_440)
 245         MFREG(UART0_SDR, reg);
 246         reg &= ~CR0_MASK;
 247
 248 #ifdef CONFIG_SYS_EXT_SERIAL_CLOCK
 249         reg |= CR0_EXTCLK_ENA;
 250         udiv = 1;
 251         clk = CONFIG_SYS_EXT_SERIAL_CLOCK;
 252 #else /* CONFIG_SYS_EXT_SERIAL_CLOCK */
 253         clk = gd->baudrate * serial_bdiv(gd->baudrate, &udiv) * 16;
 254 #endif /* CONFIG_SYS_EXT_SERIAL_CLOCK */
 255
 256         reg |= (udiv - UDIV_SUBTRACT) << CR0_UDIV_POS;  /* set the UART divisor */
 257
 258         /*
 259          * Configure input clock to baudrate generator for all
 260          * available serial ports here
 261          */
 262         MTREG(UART0_SDR, reg);
 263 #if defined(UART1_SDR)
 264         MTREG(UART1_SDR, reg);
 265 #endif
 266 #if defined(UART2_SDR)
 267         MTREG(UART2_SDR, reg);
 268 #endif
 269 #if defined(UART3_SDR)
 270         MTREG(UART3_SDR, reg);
 271 #endif
 272 #endif /* CONFIG_405EX ... */
 273
 274 #if defined(CONFIG_405EZ)
 275         clk = gd->baudrate * serial_bdiv(gd->baudrate, &udiv) * 16;
 276 #endif /* CONFIG_405EZ */
 277
 278         /*
 279          * Correct UART frequency in bd-info struct now that
 280          * the UART divisor is available
 281          */
 282 #ifdef CONFIG_SYS_EXT_SERIAL_CLOCK
 283         gd->arch.uart_clk = CONFIG_SYS_EXT_SERIAL_CLOCK;
 284 #else
 285         get_sys_info(&sys_info);
 286         gd->arch.uart_clk = sys_info.freqUART / udiv;
 287 #endif
 288
 289         return clk;
 290 }
 291 #endif  /* CONFIG_405GP || CONFIG_405CR */