arch/powerpc/cpu/ppc4xx/cache.S

   1 /*
   2  * This file contains miscellaneous low-level functions.
   3  *    Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
   4  *
   5  * Largely rewritten by Cort Dougan (cort@cs.nmt.edu)
   6  * and Paul Mackerras.
   7  *
   8  * SPDX-License-Identifier:     GPL-2.0+
   9  */
  10
  11 #include <config.h>
  12 #include <config.h>
  13 #include <asm/ppc4xx.h>
  14 #include <ppc_asm.tmpl>
  15 #include <ppc_defs.h>
  16 #include <asm/cache.h>
  17 #include <asm/mmu.h>
  18
  19 /*
  20  * Flush instruction cache.
  21  */
  22 _GLOBAL(invalidate_icache)
  23         iccci   r0,r0
  24         isync
  25         blr
  26
  27 /*
  28  * Write any modified data cache blocks out to memory
  29  * and invalidate the corresponding instruction cache blocks.
  30  *
  31  * flush_icache_range(unsigned long start, unsigned long stop)
  32  */
  33 _GLOBAL(flush_icache_range)
  34         li      r5,L1_CACHE_BYTES-1
  35         andc    r3,r3,r5
  36         subf    r4,r3,r4
  37         add     r4,r4,r5
  38         srwi.   r4,r4,L1_CACHE_SHIFT
  39         beqlr
  40         mtctr   r4
  41         mr      r6,r3
  42 1:      dcbst   0,r3
  43         addi    r3,r3,L1_CACHE_BYTES
  44         bdnz    1b
  45         sync                            /* wait for dcbst's to get to ram */
  46         mtctr   r4
  47 2:      icbi    0,r6
  48         addi    r6,r6,L1_CACHE_BYTES
  49         bdnz    2b
  50         sync                            /* additional sync needed on g4 */
  51         isync
  52         blr
  53
  54 /*
  55  * Write any modified data cache blocks out to memory.
  56  * Does not invalidate the corresponding cache lines (especially for
  57  * any corresponding instruction cache).
  58  *
  59  * clean_dcache_range(unsigned long start, unsigned long stop)
  60  */
  61 _GLOBAL(clean_dcache_range)
  62         li      r5,L1_CACHE_BYTES-1
  63         andc    r3,r3,r5
  64         subf    r4,r3,r4
  65         add     r4,r4,r5
  66         srwi.   r4,r4,L1_CACHE_SHIFT
  67         beqlr
  68         mtctr   r4
  69
  70 1:      dcbst   0,r3
  71         addi    r3,r3,L1_CACHE_BYTES
  72         bdnz    1b
  73         sync                            /* wait for dcbst's to get to ram */
  74         blr
  75
  76 /*
  77  * 40x cores have 8K or 16K dcache and 32 byte line size.
  78  * 44x has a 32K dcache and 32 byte line size.
  79  * 8xx has 1, 2, 4, 8K variants.
  80  * For now, cover the worst case of the 44x.
  81  * Must be called with external interrupts disabled.
  82  */
  83 #define CACHE_NWAYS     64
  84 #define CACHE_NLINES    32
  85
  86 _GLOBAL(flush_dcache)
  87         li      r4,(2 * CACHE_NWAYS * CACHE_NLINES)
  88         mtctr   r4
  89         lis     r5,0
  90 1:      lwz     r3,0(r5)                /* Load one word from every line */
  91         addi    r5,r5,L1_CACHE_BYTES
  92         bdnz    1b
  93         sync
  94         blr
  95
  96 _GLOBAL(invalidate_dcache)
  97         addi    r6,0,0x0000             /* clear GPR 6 */
  98         /* Do loop for # of dcache congruence classes. */
  99         lis     r7,(CONFIG_SYS_DCACHE_SIZE / L1_CACHE_BYTES / 2)@ha     /* TBS for large sized cache */
 100         ori     r7,r7,(CONFIG_SYS_DCACHE_SIZE / L1_CACHE_BYTES / 2)@l
 101                                         /* NOTE: dccci invalidates both */
 102         mtctr   r7                      /* ways in the D cache */
 103 ..dcloop:
 104         dccci   0,r6                    /* invalidate line */
 105         addi    r6,r6,L1_CACHE_BYTES    /* bump to next line */
 106         bdnz    ..dcloop
 107         sync
 108         blr
 109
 110 /*
 111  * Cache functions.
 112  *
 113  * NOTE: currently the 440s run with dcache _disabled_ once relocated to DRAM,
 114  * although for some cache-ralated calls stubs have to be provided to satisfy
 115  * symbols resolution.
 116  * Icache-related functions are used in POST framework.
 117  *
 118  */
 119 #ifdef CONFIG_440
 120
 121        .globl  dcache_disable
 122        .globl  dcache_enable
 123        .globl  icache_disable
 124        .globl  icache_enable
 125 dcache_disable:
 126 dcache_enable:
 127 icache_disable:
 128 icache_enable:
 129         blr
 130
 131         .globl  dcache_status
 132         .globl  icache_status
 133 dcache_status:
 134 icache_status:
 135         mr      r3,  0
 136         blr
 137
 138 #else /* CONFIG_440 */
 139
 140         .globl  icache_enable
 141 icache_enable:
 142         mflr    r8
 143         bl      invalidate_icache
 144         mtlr    r8
 145         isync
 146         addis   r3,r0, 0xc000         /* set bit 0 */
 147         mticcr  r3
 148         blr
 149
 150         .globl  icache_disable
 151 icache_disable:
 152         addis   r3,r0, 0x0000         /* clear bit 0 */
 153         mticcr  r3
 154         isync
 155         blr
 156
 157         .globl  icache_status
 158 icache_status:
 159         mficcr  r3
 160         srwi    r3, r3, 31      /* >>31 => select bit 0 */
 161         blr
 162
 163         .globl  dcache_enable
 164 dcache_enable:
 165         mflr    r8
 166         bl      invalidate_dcache
 167         mtlr    r8
 168         isync
 169         addis   r3,r0, 0x8000         /* set bit 0 */
 170         mtdccr  r3
 171         blr
 172
 173         .globl  dcache_disable
 174 dcache_disable:
 175         mflr    r8
 176         bl      flush_dcache
 177         mtlr    r8
 178         addis   r3,r0, 0x0000         /* clear bit 0 */
 179         mtdccr  r3
 180         blr
 181
 182         .globl  dcache_status
 183 dcache_status:
 184         mfdccr  r3
 185         srwi    r3, r3, 31      /* >>31 => select bit 0 */
 186         blr
 187
 188 #endif /* CONFIG_440 */