arch/powerpc/cpu/ppc4xx/cpu_init.c

   1 /*
   2  * (C) Copyright 2000-2007
   3  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  */
  23
  24 #include <common.h>
  25 #include <watchdog.h>
  26 #include <ppc4xx_enet.h>
  27 #include <asm/processor.h>
  28 #include <asm/gpio.h>
  29 #include <ppc4xx.h>
  30
  31 #if defined(CONFIG_405GP)  || defined(CONFIG_405EP)
  32 DECLARE_GLOBAL_DATA_PTR;
  33 #endif
  34
  35 #ifndef CONFIG_SYS_PLL_RECONFIG
  36 #define CONFIG_SYS_PLL_RECONFIG 0
  37 #endif
  38
  39 void reconfigure_pll(u32 new_cpu_freq)
  40 {
  41 #if defined(CONFIG_440EPX)
  42         int     reset_needed = 0;
  43         u32     reg, temp;
  44         u32     prbdv0, target_prbdv0,                          /* CLK_PRIMBD */
  45                 fwdva, target_fwdva, fwdvb, target_fwdvb,       /* CLK_PLLD */
  46                 fbdv, target_fbdv, lfbdv, target_lfbdv,
  47                 perdv0, target_perdv0,                          /* CLK_PERD */
  48                 spcid0, target_spcid0;                          /* CLK_SPCID */
  49
  50         /* Reconfigure clocks if necessary.
  51          * See PPC440EPx User's Manual, sections 8.2 and 14 */
  52         if (new_cpu_freq == 667) {
  53                 target_prbdv0 = 2;
  54                 target_fwdva = 2;
  55                 target_fwdvb = 4;
  56                 target_fbdv = 20;
  57                 target_lfbdv = 1;
  58                 target_perdv0 = 4;
  59                 target_spcid0 = 4;
  60
  61                 mfcpr(CPR0_PRIMBD0, reg);
  62                 temp = (reg & PRBDV_MASK) >> 24;
  63                 prbdv0 = temp ? temp : 8;
  64                 if (prbdv0 != target_prbdv0) {
  65                         reg &= ~PRBDV_MASK;
  66                         reg |= ((target_prbdv0 == 8 ? 0 : target_prbdv0) << 24);
  67                         mtcpr(CPR0_PRIMBD0, reg);
  68                         reset_needed = 1;
  69                 }
  70
  71                 mfcpr(CPR0_PLLD, reg);
  72
  73                 temp = (reg & PLLD_FWDVA_MASK) >> 16;
  74                 fwdva = temp ? temp : 16;
  75
  76                 temp = (reg & PLLD_FWDVB_MASK) >> 8;
  77                 fwdvb = temp ? temp : 8;
  78
  79                 temp = (reg & PLLD_FBDV_MASK) >> 24;
  80                 fbdv = temp ? temp : 32;
  81
  82                 temp = (reg & PLLD_LFBDV_MASK);
  83                 lfbdv = temp ? temp : 64;
  84
  85                 if (fwdva != target_fwdva || fbdv != target_fbdv || lfbdv != target_lfbdv) {
  86                         reg &= ~(PLLD_FWDVA_MASK | PLLD_FWDVB_MASK |
  87                                  PLLD_FBDV_MASK | PLLD_LFBDV_MASK);
  88                         reg |= ((target_fwdva == 16 ? 0 : target_fwdva) << 16) |
  89                                 ((target_fwdvb == 8 ? 0 : target_fwdvb) << 8) |
  90                                 ((target_fbdv == 32 ? 0 : target_fbdv) << 24) |
  91                                 (target_lfbdv == 64 ? 0 : target_lfbdv);
  92                         mtcpr(CPR0_PLLD, reg);
  93                         reset_needed = 1;
  94                 }
  95
  96                 mfcpr(CPR0_PERD, reg);
  97                 perdv0 = (reg & CPR0_PERD_PERDV0_MASK) >> 24;
  98                 if (perdv0 != target_perdv0) {
  99                         reg &= ~CPR0_PERD_PERDV0_MASK;
 100                         reg |= (target_perdv0 << 24);
 101                         mtcpr(CPR0_PERD, reg);
 102                         reset_needed = 1;
 103                 }
 104
 105                 mfcpr(CPR0_SPCID, reg);
 106                 temp = (reg & CPR0_SPCID_SPCIDV0_MASK) >> 24;
 107                 spcid0 = temp ? temp : 4;
 108                 if (spcid0 != target_spcid0) {
 109                         reg &= ~CPR0_SPCID_SPCIDV0_MASK;
 110                         reg |= ((target_spcid0 == 4 ? 0 : target_spcid0) << 24);
 111                         mtcpr(CPR0_SPCID, reg);
 112                         reset_needed = 1;
 113                 }
 114         }
 115
 116         /* Get current value of FWDVA.*/
 117         mfcpr(CPR0_PLLD, reg);
 118         temp = (reg & PLLD_FWDVA_MASK) >> 16;
 119
 120         /*
 121          * Check to see if FWDVA has been set to value of 1. if it has we must
 122          * modify it.
 123          */
 124         if (temp == 1) {
 125                 mfcpr(CPR0_PLLD, reg);
 126                 /* Get current value of fbdv.  */
 127                 temp = (reg & PLLD_FBDV_MASK) >> 24;
 128                 fbdv = temp ? temp : 32;
 129                 /* Get current value of lfbdv. */
 130                 temp = (reg & PLLD_LFBDV_MASK);
 131                 lfbdv = temp ? temp : 64;
 132                 /*
 133                  * Load register that contains current boot strapping option.
 134                  */
 135                 mfcpr(CPR0_ICFG, reg);
 136                 /* Shift strapping option into low 3 bits.*/
 137                 reg = (reg >> 28);
 138
 139                 if ((reg == BOOT_STRAP_OPTION_A) || (reg == BOOT_STRAP_OPTION_B) ||
 140                     (reg == BOOT_STRAP_OPTION_D) || (reg == BOOT_STRAP_OPTION_E)) {
 141                         /*
 142                          * Get current value of FWDVA. Assign current FWDVA to
 143                          * new FWDVB.
 144                          */
 145                         mfcpr(CPR0_PLLD, reg);
 146                         target_fwdvb = (reg & PLLD_FWDVA_MASK) >> 16;
 147                         fwdvb = target_fwdvb ? target_fwdvb : 8;
 148                         /*
 149                          * Get current value of FWDVB. Assign current FWDVB to
 150                          * new FWDVA.
 151                          */
 152                         target_fwdva = (reg & PLLD_FWDVB_MASK) >> 8;
 153                         fwdva = target_fwdva ? target_fwdva : 16;
 154                         /*
 155                          * Update CPR0_PLLD with switched FWDVA and FWDVB.
 156                          */
 157                         reg &= ~(PLLD_FWDVA_MASK | PLLD_FWDVB_MASK |
 158                                 PLLD_FBDV_MASK | PLLD_LFBDV_MASK);
 159                         reg |= ((fwdva == 16 ? 0 : fwdva) << 16) |
 160                                 ((fwdvb == 8 ? 0 : fwdvb) << 8) |
 161                                 ((fbdv == 32 ? 0 : fbdv) << 24) |
 162                                 (lfbdv == 64 ? 0 : lfbdv);
 163                         mtcpr(CPR0_PLLD, reg);
 164                         /* Acknowledge that a reset is required. */
 165                         reset_needed = 1;
 166                 }
 167         }
 168
 169         if (reset_needed) {
 170                 /*
 171                  * Set reload inhibit so configuration will persist across
 172                  * processor resets
 173                  */
 174                 mfcpr(CPR0_ICFG, reg);
 175                 reg &= ~CPR0_ICFG_RLI_MASK;
 176                 reg |= 1 << 31;
 177                 mtcpr(CPR0_ICFG, reg);
 178
 179                 /* Reset processor if configuration changed */
 180                 __asm__ __volatile__ ("sync; isync");
 181                 mtspr(SPRN_DBCR0, 0x20000000);
 182         }
 183 #endif
 184 }
 185
 186 /*
 187  * Breath some life into the CPU...
 188  *
 189  * Reconfigure PLL if necessary,
 190  * set up the memory map,
 191  * initialize a bunch of registers
 192  */
 193 void
 194 cpu_init_f (void)
 195 {
 196 #if defined(CONFIG_WATCHDOG) || defined(CONFIG_440GX) || defined(CONFIG_460EX)
 197         u32 val;
 198 #endif
 199
 200         reconfigure_pll(CONFIG_SYS_PLL_RECONFIG);
 201
 202 #if (defined(CONFIG_405EP) || defined (CONFIG_405EX)) && !defined(CONFIG_SYS_4xx_GPIO_TABLE)
 203         /*
 204          * GPIO0 setup (select GPIO or alternate function)
 205          */
 206 #if defined(CONFIG_SYS_GPIO0_OR)
 207         out32(GPIO0_OR, CONFIG_SYS_GPIO0_OR);           /* set initial state of output pins     */
 208 #endif
 209 #if defined(CONFIG_SYS_GPIO0_ODR)
 210         out32(GPIO0_ODR, CONFIG_SYS_GPIO0_ODR); /* open-drain select                    */
 211 #endif
 212         out32(GPIO0_OSRH, CONFIG_SYS_GPIO0_OSRH);       /* output select                        */
 213         out32(GPIO0_OSRL, CONFIG_SYS_GPIO0_OSRL);
 214         out32(GPIO0_ISR1H, CONFIG_SYS_GPIO0_ISR1H);     /* input select                         */
 215         out32(GPIO0_ISR1L, CONFIG_SYS_GPIO0_ISR1L);
 216         out32(GPIO0_TSRH, CONFIG_SYS_GPIO0_TSRH);       /* three-state select                   */
 217         out32(GPIO0_TSRL, CONFIG_SYS_GPIO0_TSRL);
 218 #if defined(CONFIG_SYS_GPIO0_ISR2H)
 219         out32(GPIO0_ISR2H, CONFIG_SYS_GPIO0_ISR2H);
 220         out32(GPIO0_ISR2L, CONFIG_SYS_GPIO0_ISR2L);
 221 #endif
 222 #if defined (CONFIG_SYS_GPIO0_TCR)
 223         out32(GPIO0_TCR, CONFIG_SYS_GPIO0_TCR); /* enable output driver for outputs     */
 224 #endif
 225 #endif /* CONFIG_405EP ... && !CONFIG_SYS_4xx_GPIO_TABLE */
 226
 227 #if defined (CONFIG_405EP)
 228         /*
 229          * Set EMAC noise filter bits
 230          */
 231         mtdcr(CPC0_EPCTL, CPC0_EPRCSR_E0NFE | CPC0_EPRCSR_E1NFE);
 232 #endif /* CONFIG_405EP */
 233
 234 #if defined(CONFIG_SYS_4xx_GPIO_TABLE)
 235         gpio_set_chip_configuration();
 236 #endif /* CONFIG_SYS_4xx_GPIO_TABLE */
 237
 238         /*
 239          * External Bus Controller (EBC) Setup
 240          */
 241 #if (defined(CONFIG_SYS_EBC_PB0AP) && defined(CONFIG_SYS_EBC_PB0CR))
 242 #if (defined(CONFIG_405GP) || defined(CONFIG_405CR) || \
 243      defined(CONFIG_405EP) || defined(CONFIG_405EZ) || \
 244      defined(CONFIG_405EX) || defined(CONFIG_405))
 245         /*
 246          * Move the next instructions into icache, since these modify the flash
 247          * we are running from!
 248          */
 249         asm volatile("  bl      0f"             ::: "lr");
 250         asm volatile("0:        mflr    3"              ::: "r3");
 251         asm volatile("  addi    4, 0, 14"       ::: "r4");
 252         asm volatile("  mtctr   4"              ::: "ctr");
 253         asm volatile("1:        icbt    0, 3");
 254         asm volatile("  addi    3, 3, 32"       ::: "r3");
 255         asm volatile("  bdnz    1b"             ::: "ctr", "cr0");
 256         asm volatile("  addis   3, 0, 0x0"      ::: "r3");
 257         asm volatile("  ori     3, 3, 0xA000"   ::: "r3");
 258         asm volatile("  mtctr   3"              ::: "ctr");
 259         asm volatile("2:        bdnz    2b"             ::: "ctr", "cr0");
 260 #endif
 261
 262         mtebc(PB0AP, CONFIG_SYS_EBC_PB0AP);
 263         mtebc(PB0CR, CONFIG_SYS_EBC_PB0CR);
 264 #endif
 265
 266 #if (defined(CONFIG_SYS_EBC_PB1AP) && defined(CONFIG_SYS_EBC_PB1CR) && !(CONFIG_SYS_INIT_DCACHE_CS == 1))
 267         mtebc(PB1AP, CONFIG_SYS_EBC_PB1AP);
 268         mtebc(PB1CR, CONFIG_SYS_EBC_PB1CR);
 269 #endif
 270
 271 #if (defined(CONFIG_SYS_EBC_PB2AP) && defined(CONFIG_SYS_EBC_PB2CR) && !(CONFIG_SYS_INIT_DCACHE_CS == 2))
 272         mtebc(PB2AP, CONFIG_SYS_EBC_PB2AP);
 273         mtebc(PB2CR, CONFIG_SYS_EBC_PB2CR);
 274 #endif
 275
 276 #if (defined(CONFIG_SYS_EBC_PB3AP) && defined(CONFIG_SYS_EBC_PB3CR) && !(CONFIG_SYS_INIT_DCACHE_CS == 3))
 277         mtebc(PB3AP, CONFIG_SYS_EBC_PB3AP);
 278         mtebc(PB3CR, CONFIG_SYS_EBC_PB3CR);
 279 #endif
 280
 281 #if (defined(CONFIG_SYS_EBC_PB4AP) && defined(CONFIG_SYS_EBC_PB4CR) && !(CONFIG_SYS_INIT_DCACHE_CS == 4))
 282         mtebc(PB4AP, CONFIG_SYS_EBC_PB4AP);
 283         mtebc(PB4CR, CONFIG_SYS_EBC_PB4CR);
 284 #endif
 285
 286 #if (defined(CONFIG_SYS_EBC_PB5AP) && defined(CONFIG_SYS_EBC_PB5CR) && !(CONFIG_SYS_INIT_DCACHE_CS == 5))
 287         mtebc(PB5AP, CONFIG_SYS_EBC_PB5AP);
 288         mtebc(PB5CR, CONFIG_SYS_EBC_PB5CR);
 289 #endif
 290
 291 #if (defined(CONFIG_SYS_EBC_PB6AP) && defined(CONFIG_SYS_EBC_PB6CR) && !(CONFIG_SYS_INIT_DCACHE_CS == 6))
 292         mtebc(PB6AP, CONFIG_SYS_EBC_PB6AP);
 293         mtebc(PB6CR, CONFIG_SYS_EBC_PB6CR);
 294 #endif
 295
 296 #if (defined(CONFIG_SYS_EBC_PB7AP) && defined(CONFIG_SYS_EBC_PB7CR) && !(CONFIG_SYS_INIT_DCACHE_CS == 7))
 297         mtebc(PB7AP, CONFIG_SYS_EBC_PB7AP);
 298         mtebc(PB7CR, CONFIG_SYS_EBC_PB7CR);
 299 #endif
 300
 301 #if defined (CONFIG_SYS_EBC_CFG)
 302         mtebc(EBC0_CFG, CONFIG_SYS_EBC_CFG);
 303 #endif
 304
 305 #if defined(CONFIG_WATCHDOG)
 306         val = mfspr(tcr);
 307 #if defined(CONFIG_440EP) || defined(CONFIG_440GR)
 308         val |= 0xb8000000;      /* generate system reset after 1.34 seconds */
 309 #elif defined(CONFIG_440EPX)
 310         val |= 0xb0000000;      /* generate system reset after 1.34 seconds */
 311 #else
 312         val |= 0xf0000000;      /* generate system reset after 2.684 seconds */
 313 #endif
 314 #if defined(CONFIG_SYS_4xx_RESET_TYPE)
 315         val &= ~0x30000000;                     /* clear WRC bits */
 316         val |= CONFIG_SYS_4xx_RESET_TYPE << 28; /* set board specific WRC type */
 317 #endif
 318         mtspr(tcr, val);
 319
 320         val = mfspr(tsr);
 321         val |= 0x80000000;      /* enable watchdog timer */
 322         mtspr(tsr, val);
 323
 324         reset_4xx_watchdog();
 325 #endif /* CONFIG_WATCHDOG */
 326
 327 #if defined(CONFIG_440GX)
 328         /* Take the GX out of compatibility mode
 329          * Travis Sawyer, 9 Mar 2004
 330          * NOTE: 440gx user manual inconsistency here
 331          *       Compatibility mode and Ethernet Clock select are not
 332          *       correct in the manual
 333          */
 334         mfsdr(SDR0_MFR, val);
 335         val &= ~0x10000000;
 336         mtsdr(SDR0_MFR,val);
 337 #endif /* CONFIG_440GX */
 338
 339 #if defined(CONFIG_460EX)
 340         /*
 341          * Set SDR0_AHB_CFG[A2P_INCR4] (bit 24) and
 342          * clear SDR0_AHB_CFG[A2P_PROT2] (bit 25) for a new 460EX errata
 343          * regarding concurrent use of AHB USB OTG, USB 2.0 host and SATA
 344          */
 345         mfsdr(SDR0_AHB_CFG, val);
 346         val |= 0x80;
 347         val &= ~0x40;
 348         mtsdr(SDR0_AHB_CFG, val);
 349         mfsdr(SDR0_USB2HOST_CFG, val);
 350         val &= ~0xf00;
 351         val |= 0x400;
 352         mtsdr(SDR0_USB2HOST_CFG, val);
 353 #endif /* CONFIG_460EX */
 354
 355 #if defined(CONFIG_405EX) || \
 356     defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
 357     defined(CONFIG_460EX) || defined(CONFIG_460GT)  || \
 358     defined(CONFIG_460SX)
 359         /*
 360          * Set PLB4 arbiter (Segment 0 and 1) to 4 deep pipeline read
 361          */
 362         mtdcr(PLB0_ACR, (mfdcr(PLB0_ACR) & ~PLB0_ACR_RDP_MASK) |
 363               PLB0_ACR_RDP_4DEEP);
 364         mtdcr(PLB1_ACR, (mfdcr(PLB1_ACR) & ~PLB1_ACR_RDP_MASK) |
 365               PLB1_ACR_RDP_4DEEP);
 366 #endif /* CONFIG_440SP/SPE || CONFIG_460EX/GT || CONFIG_405EX */
 367 }
 368
 369 /*
 370  * initialize higher level parts of CPU like time base and timers
 371  */
 372 int cpu_init_r (void)
 373 {
 374 #if defined(CONFIG_405GP)
 375         uint pvr = get_pvr();
 376
 377         /*
 378          * Set edge conditioning circuitry on PPC405GPr
 379          * for compatibility to existing PPC405GP designs.
 380          */
 381         if ((pvr & 0xfffffff0) == (PVR_405GPR_RB & 0xfffffff0)) {
 382                 mtdcr(CPC0_ECR, 0x60606000);
 383         }
 384 #endif  /* defined(CONFIG_405GP) */
 385
 386         return 0;
 387 }
 388
 389 #if defined(CONFIG_PCI) && \
 390         (defined(CONFIG_440EP) || defined(CONFIG_440EPX) || \
 391          defined(CONFIG_440GR) || defined(CONFIG_440GRX))
 392 /*
 393  * 440EP(x)/GR(x) PCI async/sync clocking restriction:
 394  *
 395  * In asynchronous PCI mode, the synchronous PCI clock must meet
 396  * certain requirements. The following equation describes the
 397  * relationship that must be maintained between the asynchronous PCI
 398  * clock and synchronous PCI clock. Select an appropriate PCI:PLB
 399  * ratio to maintain the relationship:
 400  *
 401  * AsyncPCIClk - 1MHz <= SyncPCIclock <= (2 * AsyncPCIClk) - 1MHz
 402  */
 403 static int ppc4xx_pci_sync_clock_ok(u32 sync, u32 async)
 404 {
 405         if (((async - 1000000) > sync) || (sync > ((2 * async) - 1000000)))
 406                 return 0;
 407         else
 408                 return 1;
 409 }
 410
 411 int ppc4xx_pci_sync_clock_config(u32 async)
 412 {
 413         sys_info_t sys_info;
 414         u32 sync;
 415         int div;
 416         u32 reg;
 417         u32 spcid_val[] = {
 418                 CPR0_SPCID_SPCIDV0_DIV1, CPR0_SPCID_SPCIDV0_DIV2,
 419                 CPR0_SPCID_SPCIDV0_DIV3, CPR0_SPCID_SPCIDV0_DIV4 };
 420
 421         get_sys_info(&sys_info);
 422         sync = sys_info.freqPCI;
 423
 424         /*
 425          * First check if the equation above is met
 426          */
 427         if (!ppc4xx_pci_sync_clock_ok(sync, async)) {
 428                 /*
 429                  * Reconfigure PCI sync clock to meet the equation.
 430                  * Start with highest possible PCI sync frequency
 431                  * (divider 1).
 432                  */
 433                 for (div = 1; div <= 4; div++) {
 434                         sync = sys_info.freqPLB / div;
 435                         if (ppc4xx_pci_sync_clock_ok(sync, async))
 436                             break;
 437                 }
 438
 439                 if (div <= 4) {
 440                         mtcpr(CPR0_SPCID, spcid_val[div]);
 441
 442                         mfcpr(CPR0_ICFG, reg);
 443                         reg |= CPR0_ICFG_RLI_MASK;
 444                         mtcpr(CPR0_ICFG, reg);
 445
 446                         /* do chip reset */
 447                         mtspr(SPRN_DBCR0, 0x20000000);
 448                 } else {
 449                         /* Impossible to configure the PCI sync clock */
 450                         return -1;
 451                 }
 452         }
 453
 454         return 0;
 455 }
 456 #endif