2 * Copyright (c) 2008 Nuovation System Designs, LLC
3 * Grant Erickson <gerickson@nuovations.com>
5 * (C) Copyright 2005-2009
6 * Stefan Roese, DENX Software Engineering, sr@denx.de.
9 * Jun Gu, Artesyn Technology, jung@artesyncp.com
12 * Bill Hunter, Wave 7 Optics, williamhunter@attbi.com
14 * See file CREDITS for list of people who contributed to this
17 * This program is free software; you can redistribute it and/or
18 * modify it under the terms of the GNU General Public License as
19 * published by the Free Software Foundation; either version 2 of
20 * the License, or (at your option) any later version.
22 * This program is distributed in the hope that it will abe useful,
23 * but WITHOUT ANY WARRANTY; without even the implied warranty of
24 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
25 * GNU General Public License for more details.
27 * You should have received a copy of the GNU General Public License
28 * along with this program; if not, write to the Free Software
29 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
33 * This file implements generic DRAM ECC initialization for
34 * PowerPC processors using a SDRAM DDR/DDR2 controller,
35 * including the 405EX(r), 440GP/GX/EP/GR, 440SP(E), and
41 #include <ppc_asm.tmpl>
43 #include <asm/processor.h>
46 #include <asm/cache.h>
50 #if defined(CONFIG_SDRAM_PPC4xx_IBM_DDR) || \
51 defined(CONFIG_SDRAM_PPC4xx_IBM_DDR2)
52 #if defined(CONFIG_DDR_ECC) || defined(CONFIG_SDRAM_ECC)
54 #if defined(CONFIG_405EX)
56 * Currently only 405EX uses 16bit data bus width as an alternative
57 * option to 32bit data width (SDRAM0_MCOPT1_WDTH)
59 #define SDRAM_DATA_ALT_WIDTH 2
61 #define SDRAM_DATA_ALT_WIDTH 8
64 static void wait_ddr_idle(void)
69 mfsdram(SDRAM_MCSTAT
, val
);
70 } while ((val
& SDRAM_MCSTAT_IDLE_MASK
) == SDRAM_MCSTAT_IDLE_NOT
);
73 static void program_ecc_addr(unsigned long start_address
,
74 unsigned long num_bytes
,
75 unsigned long tlb_word2_i_value
)
77 unsigned long current_address
;
78 unsigned long end_address
;
79 unsigned long address_increment
;
81 char str
[] = "ECC generation -";
82 char slash
[] = "\\|/-\\|/-";
86 current_address
= start_address
;
87 mfsdram(SDRAM_MCOPT1
, mcopt1
);
88 if ((mcopt1
& SDRAM_MCOPT1_MCHK_MASK
) != SDRAM_MCOPT1_MCHK_NON
) {
90 (mcopt1
& ~SDRAM_MCOPT1_MCHK_MASK
) | SDRAM_MCOPT1_MCHK_GEN
);
98 if (tlb_word2_i_value
== TLB_WORD2_I_ENABLE
) {
100 /* ECC bit set method for non-cached memory */
101 if ((mcopt1
& SDRAM_MCOPT1_DMWD_MASK
) == SDRAM_MCOPT1_DMWD_32
)
102 address_increment
= 4;
104 address_increment
= SDRAM_DATA_ALT_WIDTH
;
105 end_address
= current_address
+ num_bytes
;
107 while (current_address
< end_address
) {
108 *((unsigned long *)current_address
) = 0;
109 current_address
+= address_increment
;
111 if ((loop
++ % (2 << 20)) == 0) {
113 putc(slash
[loopi
++ % 8]);
118 /* ECC bit set method for cached memory */
119 dcbz_area(start_address
, num_bytes
);
120 /* Write modified dcache lines back to memory */
121 clean_dcache_range(start_address
, start_address
+ num_bytes
);
123 #endif /* CONFIG_440 */
125 blank_string(strlen(str
));
131 /* clear ECC error repoting registers */
132 mtsdram(SDRAM_ECCES
, 0xffffffff);
133 #if defined(CONFIG_SDRAM_PPC4xx_IBM_DDR)
135 * IBM DDR(1) core (440GX):
136 * Clear Mx bits in SDRAM0_BESR0/1
138 mtsdram(SDRAM0_BESR0
, 0xffffffff);
139 mtsdram(SDRAM0_BESR1
, 0xffffffff);
140 #elif defined(CONFIG_440)
143 * Clear EMID (Error PLB Master ID) in MQ0_ESL
145 mtdcr(SDRAM_ERRSTATLL
, 0xfff00000);
148 * 405EX(r) DDR2 core:
149 * Clear M0ID (Error PLB Master ID) in SDRAM_BESR
151 mtsdram(SDRAM_BESR
, 0xf0000000);
154 mtsdram(SDRAM_MCOPT1
,
155 (mcopt1
& ~SDRAM_MCOPT1_MCHK_MASK
) | SDRAM_MCOPT1_MCHK_CHK_REP
);
162 #if defined(CONFIG_SDRAM_PPC4xx_IBM_DDR)
163 void ecc_init(unsigned long * const start
, unsigned long size
)
166 * Init ECC with cache disabled (on PPC's with IBM DDR
167 * controller (non DDR2), not tested with cache enabled yet
169 program_ecc_addr((u32
)start
, size
, TLB_WORD2_I_ENABLE
);
173 #if defined(CONFIG_SDRAM_PPC4xx_IBM_DDR2)
174 void do_program_ecc(unsigned long tlb_word2_i_value
)
176 unsigned long mcopt1
;
177 unsigned long mcopt2
;
178 unsigned long mcstat
;
179 phys_size_t memsize
= sdram_memsize();
181 if (memsize
> CONFIG_MAX_MEM_MAPPED
) {
182 printf("\nWarning: Can't enable ECC on systems with more than 2GB of SDRAM!\n");
186 mfsdram(SDRAM_MCOPT1
, mcopt1
);
187 mfsdram(SDRAM_MCOPT2
, mcopt2
);
189 if ((mcopt1
& SDRAM_MCOPT1_MCHK_MASK
) != SDRAM_MCOPT1_MCHK_NON
) {
190 /* DDR controller must be enabled and not in self-refresh. */
191 mfsdram(SDRAM_MCSTAT
, mcstat
);
192 if (((mcopt2
& SDRAM_MCOPT2_DCEN_MASK
) == SDRAM_MCOPT2_DCEN_ENABLE
)
193 && ((mcopt2
& SDRAM_MCOPT2_SREN_MASK
) == SDRAM_MCOPT2_SREN_EXIT
)
194 && ((mcstat
& (SDRAM_MCSTAT_MIC_MASK
| SDRAM_MCSTAT_SRMS_MASK
))
195 == (SDRAM_MCSTAT_MIC_COMP
| SDRAM_MCSTAT_SRMS_NOT_SF
))) {
197 program_ecc_addr(0, memsize
, tlb_word2_i_value
);
203 #endif /* defined(CONFIG_DDR_ECC) || defined(CONFIG_SDRAM_ECC) */
204 #endif /* defined(CONFIG_SDRAM_PPC4xx_IBM_DDR)... */