arch/powerpc/cpu/ppc4xx/sdram.c

   1 /*
   2  * (C) Copyright 2005-2007
   3  * Stefan Roese, DENX Software Engineering, sr@denx.de.
   4  *
   5  * (C) Copyright 2006
   6  * DAVE Srl <www.dave-tech.it>
   7  *
   8  * (C) Copyright 2002-2004
   9  * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
  10  *
  11  * SPDX-License-Identifier:     GPL-2.0+
  12  */
  13
  14 #include <common.h>
  15 #include <asm/ppc4xx.h>
  16 #include <asm/processor.h>
  17 #include "sdram.h"
  18 #include "ecc.h"
  19
  20 DECLARE_GLOBAL_DATA_PTR;
  21
  22 #ifdef CONFIG_SDRAM_BANK0
  23
  24 #ifndef CONFIG_440
  25
  26 #ifndef CONFIG_SYS_SDRAM_TABLE
  27 sdram_conf_t mb0cf[] = {
  28         {(128 << 20), 13, 0x000A4001},      /* (0-128MB) Address Mode 3, 13x10(4) */
  29         {(64 << 20),  13, 0x00084001},      /* (0-64MB) Address Mode 3, 13x9(4)   */
  30         {(32 << 20),  12, 0x00062001},      /* (0-32MB) Address Mode 2, 12x9(4)   */
  31         {(16 << 20),  12, 0x00046001},      /* (0-16MB) Address Mode 4, 12x8(4)   */
  32         {(4 << 20),   11, 0x00008001},      /* (0-4MB) Address Mode 5, 11x8(2)    */
  33 };
  34 #else
  35 sdram_conf_t mb0cf[] = CONFIG_SYS_SDRAM_TABLE;
  36 #endif
  37
  38 #define N_MB0CF (ARRAY_SIZE(mb0cf))
  39
  40 #ifdef CONFIG_SYS_SDRAM_CASL
  41 static ulong ns2clks(ulong ns)
  42 {
  43         ulong bus_period_x_10 = ONE_BILLION / (get_bus_freq(0) / 10);
  44
  45         return ((ns * 10) + bus_period_x_10) / bus_period_x_10;
  46 }
  47 #endif /* CONFIG_SYS_SDRAM_CASL */
  48
  49 static ulong compute_sdtr1(ulong speed)
  50 {
  51 #ifdef CONFIG_SYS_SDRAM_CASL
  52         ulong tmp;
  53         ulong sdtr1 = 0;
  54
  55         /* CASL */
  56         if (CONFIG_SYS_SDRAM_CASL < 2)
  57                 sdtr1 |= (1 << SDRAM0_TR_CASL);
  58         else
  59                 if (CONFIG_SYS_SDRAM_CASL > 4)
  60                         sdtr1 |= (3 << SDRAM0_TR_CASL);
  61                 else
  62                         sdtr1 |= ((CONFIG_SYS_SDRAM_CASL-1) << SDRAM0_TR_CASL);
  63
  64         /* PTA */
  65         tmp = ns2clks(CONFIG_SYS_SDRAM_PTA);
  66         if ((tmp >= 2) && (tmp <= 4))
  67                 sdtr1 |= ((tmp-1) << SDRAM0_TR_PTA);
  68         else
  69                 sdtr1 |= ((4-1) << SDRAM0_TR_PTA);
  70
  71         /* CTP */
  72         tmp = ns2clks(CONFIG_SYS_SDRAM_CTP);
  73         if ((tmp >= 2) && (tmp <= 4))
  74                 sdtr1 |= ((tmp-1) << SDRAM0_TR_CTP);
  75         else
  76                 sdtr1 |= ((4-1) << SDRAM0_TR_CTP);
  77
  78         /* LDF */
  79         tmp = ns2clks(CONFIG_SYS_SDRAM_LDF);
  80         if ((tmp >= 2) && (tmp <= 4))
  81                 sdtr1 |= ((tmp-1) << SDRAM0_TR_LDF);
  82         else
  83                 sdtr1 |= ((2-1) << SDRAM0_TR_LDF);
  84
  85         /* RFTA */
  86         tmp = ns2clks(CONFIG_SYS_SDRAM_RFTA);
  87         if ((tmp >= 4) && (tmp <= 10))
  88                 sdtr1 |= ((tmp-4) << SDRAM0_TR_RFTA);
  89         else
  90                 sdtr1 |= ((10-4) << SDRAM0_TR_RFTA);
  91
  92         /* RCD */
  93         tmp = ns2clks(CONFIG_SYS_SDRAM_RCD);
  94         if ((tmp >= 2) && (tmp <= 4))
  95                 sdtr1 |= ((tmp-1) << SDRAM0_TR_RCD);
  96         else
  97                 sdtr1 |= ((4-1) << SDRAM0_TR_RCD);
  98
  99         return sdtr1;
 100 #else /* CONFIG_SYS_SDRAM_CASL */
 101         /*
 102          * If no values are configured in the board config file
 103          * use the default values, which seem to be ok for most
 104          * boards.
 105          *
 106          * REMARK:
 107          * For new board ports we strongly recommend to define the
 108          * correct values for the used SDRAM chips in your board
 109          * config file (see PPChameleonEVB.h)
 110          */
 111         if (speed > 100000000) {
 112                 /*
 113                  * 133 MHz SDRAM
 114                  */
 115                 return 0x01074015;
 116         } else {
 117                 /*
 118                  * default: 100 MHz SDRAM
 119                  */
 120                 return 0x0086400d;
 121         }
 122 #endif /* CONFIG_SYS_SDRAM_CASL */
 123 }
 124
 125 /* refresh is expressed in ms */
 126 static ulong compute_rtr(ulong speed, ulong rows, ulong refresh)
 127 {
 128 #ifdef CONFIG_SYS_SDRAM_CASL
 129         ulong tmp;
 130
 131         tmp = ((refresh*1000*1000) / (1 << rows)) * (speed / 1000);
 132         tmp /= 1000000;
 133
 134         return ((tmp & 0x00003FF8) << 16);
 135 #else /* CONFIG_SYS_SDRAM_CASL */
 136         if (speed > 100000000) {
 137                 /*
 138                  * 133 MHz SDRAM
 139                  */
 140                 return 0x07f00000;
 141         } else {
 142                 /*
 143                  * default: 100 MHz SDRAM
 144                  */
 145                 return 0x05f00000;
 146         }
 147 #endif /* CONFIG_SYS_SDRAM_CASL */
 148 }
 149
 150 /*
 151  * Autodetect onboard SDRAM on 405 platforms
 152  */
 153 int dram_init(void)
 154 {
 155         ulong speed;
 156         ulong sdtr1;
 157         int i;
 158
 159         /*
 160          * Determine SDRAM speed
 161          */
 162         speed = get_bus_freq(0); /* parameter not used on ppc4xx */
 163
 164         /*
 165          * sdtr1 (register SDRAM0_TR) must take into account timings listed
 166          * in SDRAM chip datasheet. rtr (register SDRAM0_RTR) must take into
 167          * account actual SDRAM size. So we can set up sdtr1 according to what
 168          * is specified in board configuration file while rtr dependds on SDRAM
 169          * size we are assuming before detection.
 170          */
 171         sdtr1 = compute_sdtr1(speed);
 172
 173         for (i=0; i<N_MB0CF; i++) {
 174                 /*
 175                  * Disable memory controller.
 176                  */
 177                 mtsdram(SDRAM0_CFG, 0x00000000);
 178
 179                 /*
 180                  * Set MB0CF for bank 0.
 181                  */
 182                 mtsdram(SDRAM0_B0CR, mb0cf[i].reg);
 183                 mtsdram(SDRAM0_TR, sdtr1);
 184                 mtsdram(SDRAM0_RTR, compute_rtr(speed, mb0cf[i].rows, 64));
 185
 186                 udelay(200);
 187
 188                 /*
 189                  * Set memory controller options reg, MCOPT1.
 190                  * Set DC_EN to '1' and BRD_PRF to '01' for 16 byte PLB Burst
 191                  * read/prefetch.
 192                  */
 193                 mtsdram(SDRAM0_CFG, 0x80800000);
 194
 195                 udelay(10000);
 196
 197                 if (get_ram_size(0, mb0cf[i].size) == mb0cf[i].size) {
 198                         phys_size_t size = mb0cf[i].size;
 199
 200                         /*
 201                          * OK, size detected.  Enable second bank if
 202                          * defined (assumes same type as bank 0)
 203                          */
 204 #ifdef CONFIG_SDRAM_BANK1
 205                         mtsdram(SDRAM0_CFG, 0x00000000);
 206                         mtsdram(SDRAM0_B1CR, mb0cf[i].size | mb0cf[i].reg);
 207                         mtsdram(SDRAM0_CFG, 0x80800000);
 208                         udelay(10000);
 209
 210                         /*
 211                          * Check if 2nd bank is really available.
 212                          * If the size not equal to the size of the first
 213                          * bank, then disable the 2nd bank completely.
 214                          */
 215                         if (get_ram_size((long *)mb0cf[i].size, mb0cf[i].size) !=
 216                             mb0cf[i].size) {
 217                                 mtsdram(SDRAM0_B1CR, 0);
 218                                 mtsdram(SDRAM0_CFG, 0);
 219                         } else {
 220                                 /*
 221                                  * We have two identical banks, so the size
 222                                  * is twice the bank size
 223                                  */
 224                                 size = 2 * size;
 225                         }
 226 #endif
 227
 228                         /*
 229                          * OK, size detected -> all done
 230                          */
 231                         gd->ram_size = size;
 232
 233                         return 0;
 234                 }
 235         }
 236
 237         return -ENXIO;
 238 }
 239
 240 #else /* CONFIG_440 */
 241
 242 /*
 243  * Define some default values. Those can be overwritten in the
 244  * board config file.
 245  */
 246
 247 #ifndef CONFIG_SYS_SDRAM_TABLE
 248 sdram_conf_t mb0cf[] = {
 249         {(256 << 20), 13, 0x000C4001},  /* 256MB mode 3, 13x10(4)       */
 250         {(128 << 20), 13, 0x000A4001},  /* 128MB mode 3, 13x10(4)       */
 251         {(64 << 20),  12, 0x00082001}   /* 64MB mode 2, 12x9(4)         */
 252 };
 253 #else
 254 sdram_conf_t mb0cf[] = CONFIG_SYS_SDRAM_TABLE;
 255 #endif
 256
 257 #ifndef CONFIG_SYS_SDRAM0_TR0
 258 #define CONFIG_SYS_SDRAM0_TR0           0x41094012
 259 #endif
 260
 261 #ifndef CONFIG_SYS_SDRAM0_WDDCTR
 262 #define CONFIG_SYS_SDRAM0_WDDCTR        0x00000000  /* wrcp=0 dcd=0     */
 263 #endif
 264
 265 #ifndef CONFIG_SYS_SDRAM0_RTR
 266 #define CONFIG_SYS_SDRAM0_RTR           0x04100000 /* 7.8us @ 133MHz PLB */
 267 #endif
 268
 269 #ifndef CONFIG_SYS_SDRAM0_CFG0
 270 #define CONFIG_SYS_SDRAM0_CFG0          0x82000000 /* DCEN=1, PMUD=0, 64-bit */
 271 #endif
 272
 273 #define N_MB0CF (ARRAY_SIZE(mb0cf))
 274
 275 #define NUM_TRIES 64
 276 #define NUM_READS 10
 277
 278 static void sdram_tr1_set(int ram_address, int* tr1_value)
 279 {
 280         int i;
 281         int j, k;
 282         volatile unsigned int* ram_pointer = (unsigned int *)ram_address;
 283         int first_good = -1, last_bad = 0x1ff;
 284
 285         unsigned long test[NUM_TRIES] = {
 286                 0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
 287                 0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
 288                 0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000,
 289                 0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000,
 290                 0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555,
 291                 0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555,
 292                 0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA,
 293                 0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA,
 294                 0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A,
 295                 0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A,
 296                 0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5,
 297                 0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5,
 298                 0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA,
 299                 0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA,
 300                 0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55,
 301                 0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55 };
 302
 303         /* go through all possible SDRAM0_TR1[RDCT] values */
 304         for (i=0; i<=0x1ff; i++) {
 305                 /* set the current value for TR1 */
 306                 mtsdram(SDRAM0_TR1, (0x80800800 | i));
 307
 308                 /* write values */
 309                 for (j=0; j<NUM_TRIES; j++) {
 310                         ram_pointer[j] = test[j];
 311
 312                         /* clear any cache at ram location */
 313                         __asm__("dcbf 0,%0": :"r" (&ram_pointer[j]));
 314                 }
 315
 316                 /* read values back */
 317                 for (j=0; j<NUM_TRIES; j++) {
 318                         for (k=0; k<NUM_READS; k++) {
 319                                 /* clear any cache at ram location */
 320                                 __asm__("dcbf 0,%0": :"r" (&ram_pointer[j]));
 321
 322                                 if (ram_pointer[j] != test[j])
 323                                         break;
 324                         }
 325
 326                         /* read error */
 327                         if (k != NUM_READS)
 328                                 break;
 329                 }
 330
 331                 /* we have a SDRAM0_TR1[RDCT] that is part of the window */
 332                 if (j == NUM_TRIES) {
 333                         if (first_good == -1)
 334                                 first_good = i;         /* found beginning of window */
 335                 } else { /* bad read */
 336                         /* if we have not had a good read then don't care */
 337                         if (first_good != -1) {
 338                                 /* first failure after a good read */
 339                                 last_bad = i-1;
 340                                 break;
 341                         }
 342                 }
 343         }
 344
 345         /* return the current value for TR1 */
 346         *tr1_value = (first_good + last_bad) / 2;
 347 }
 348
 349 /*
 350  * Autodetect onboard DDR SDRAM on 440 platforms
 351  *
 352  * NOTE: Some of the hardcoded values are hardware dependant,
 353  *       so this should be extended for other future boards
 354  *       using this routine!
 355  */
 356 int dram_init(void)
 357 {
 358         int i;
 359         int tr1_bank1;
 360
 361 #if defined(CONFIG_440GX) || defined(CONFIG_440EP) || \
 362     defined(CONFIG_440GR) || defined(CONFIG_440SP)
 363         /*
 364          * Soft-reset SDRAM controller.
 365          */
 366         mtsdr(SDR0_SRST, SDR0_SRST_DMC);
 367         mtsdr(SDR0_SRST, 0x00000000);
 368 #endif
 369
 370         for (i=0; i<N_MB0CF; i++) {
 371                 /*
 372                  * Disable memory controller.
 373                  */
 374                 mtsdram(SDRAM0_CFG0, 0x00000000);
 375
 376                 /*
 377                  * Setup some default
 378                  */
 379                 mtsdram(SDRAM0_UABBA, 0x00000000); /* ubba=0 (default)          */
 380                 mtsdram(SDRAM0_SLIO, 0x00000000);       /* rdre=0 wrre=0 rarw=0         */
 381                 mtsdram(SDRAM0_DEVOPT, 0x00000000); /* dll=0 ds=0 (normal)              */
 382                 mtsdram(SDRAM0_WDDCTR, CONFIG_SYS_SDRAM0_WDDCTR);
 383                 mtsdram(SDRAM0_CLKTR, 0x40000000); /* clkp=1 (90 deg wr) dcdt=0 */
 384
 385                 /*
 386                  * Following for CAS Latency = 2.5 @ 133 MHz PLB
 387                  */
 388                 mtsdram(SDRAM0_B0CR, mb0cf[i].reg);
 389                 mtsdram(SDRAM0_TR0, CONFIG_SYS_SDRAM0_TR0);
 390                 mtsdram(SDRAM0_TR1, 0x80800800);        /* SS=T2 SL=STAGE 3 CD=1 CT=0x00*/
 391                 mtsdram(SDRAM0_RTR, CONFIG_SYS_SDRAM0_RTR);
 392                 mtsdram(SDRAM0_CFG1, 0x00000000);       /* Self-refresh exit, disable PM*/
 393                 udelay(400);                    /* Delay 200 usecs (min)        */
 394
 395                 /*
 396                  * Enable the controller, then wait for DCEN to complete
 397                  */
 398                 mtsdram(SDRAM0_CFG0, CONFIG_SYS_SDRAM0_CFG0);
 399                 udelay(10000);
 400
 401                 if (get_ram_size(0, mb0cf[i].size) == mb0cf[i].size) {
 402                         phys_size_t size = mb0cf[i].size;
 403                         /*
 404                          * Optimize TR1 to current hardware environment
 405                          */
 406                         sdram_tr1_set(0x00000000, &tr1_bank1);
 407                         mtsdram(SDRAM0_TR1, (tr1_bank1 | 0x80800800));
 408
 409
 410                         /*
 411                          * OK, size detected.  Enable second bank if
 412                          * defined (assumes same type as bank 0)
 413                          */
 414 #ifdef CONFIG_SDRAM_BANK1
 415                         mtsdram(SDRAM0_CFG0, 0);
 416                         mtsdram(SDRAM0_B1CR, mb0cf[i].size | mb0cf[i].reg);
 417                         mtsdram(SDRAM0_CFG0, CONFIG_SYS_SDRAM0_CFG0);
 418                         udelay(10000);
 419
 420                         /*
 421                          * Check if 2nd bank is really available.
 422                          * If the size not equal to the size of the first
 423                          * bank, then disable the 2nd bank completely.
 424                          */
 425                         if (get_ram_size((long *)mb0cf[i].size, mb0cf[i].size)
 426                             != mb0cf[i].size) {
 427                                 mtsdram(SDRAM0_CFG0, 0);
 428                                 mtsdram(SDRAM0_B1CR, 0);
 429                                 mtsdram(SDRAM0_CFG0, CONFIG_SYS_SDRAM0_CFG0);
 430                                 udelay(10000);
 431                         } else {
 432                                 /*
 433                                  * We have two identical banks, so the size
 434                                  * is twice the bank size
 435                                  */
 436                                 size = 2 * size;
 437                         }
 438 #endif
 439
 440 #ifdef CONFIG_SDRAM_ECC
 441                         ecc_init(0, size);
 442 #endif
 443
 444                         /*
 445                          * OK, size detected -> all done
 446                          */
 447                         gd->ram_size = size;
 448
 449                         return 0;
 450                 }
 451         }
 452
 453         return -ENXIO;                  /* nothing found !              */
 454 }
 455
 456 #endif /* CONFIG_440 */
 457
 458 #endif /* CONFIG_SDRAM_BANK0 */