arch/powerpc/cpu/ppc4xx/uic.c

   1 /*
   2  * (C) Copyright 2000-2002
   3  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   4  *
   5  * (C) Copyright 2002 (440 port)
   6  * Scott McNutt, Artesyn Communication Producs, smcnutt@artsyncp.com
   7  *
   8  * (C) Copyright 2003 (440GX port)
   9  * Travis B. Sawyer, Sandburst Corporation, tsawyer@sandburst.com
  10  *
  11  * (C) Copyright 2008 (PPC440X05 port for Virtex 5 FX)
  12  * Ricardo Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@uam.es
  13  * Work supported by Qtechnology (htpp://qtec.com)
  14  *
  15  * See file CREDITS for list of people who contributed to this
  16  * project.
  17  *
  18  * This program is free software; you can redistribute it and/or
  19  * modify it under the terms of the GNU General Public License as
  20  * published by the Free Software Foundation; either version 2 of
  21  * the License, or (at your option) any later version.
  22  *
  23  * This program is distributed in the hope that it will be useful,
  24  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  25  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  26  * GNU General Public License for more details.
  27  *
  28  * You should have received a copy of the GNU General Public License
  29  * along with this program; if not, write to the Free Software
  30  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  31  * MA 02111-1307 USA
  32  */
  33
  34 #include <common.h>
  35 #include <watchdog.h>
  36 #include <command.h>
  37 #include <asm/processor.h>
  38 #include <asm/interrupt.h>
  39 #include <ppc4xx.h>
  40 #include <ppc_asm.tmpl>
  41 #include <commproc.h>
  42
  43 #if (UIC_MAX > 3)
  44 #define UICB0_ALL       (UIC_MASK(VECNUM_UIC1CI) | UIC_MASK(VECNUM_UIC1NCI) | \
  45                          UIC_MASK(VECNUM_UIC2CI) | UIC_MASK(VECNUM_UIC2NCI) | \
  46                          UIC_MASK(VECNUM_UIC3CI) | UIC_MASK(VECNUM_UIC3NCI))
  47 #elif (UIC_MAX > 2)
  48 #define UICB0_ALL       (UIC_MASK(VECNUM_UIC1CI) | UIC_MASK(VECNUM_UIC1NCI) | \
  49                          UIC_MASK(VECNUM_UIC2CI) | UIC_MASK(VECNUM_UIC2NCI))
  50 #elif (UIC_MAX > 1)
  51 #define UICB0_ALL       (UIC_MASK(VECNUM_UIC1CI) | UIC_MASK(VECNUM_UIC1NCI))
  52 #else
  53 #define UICB0_ALL       0
  54 #endif
  55
  56 u32 get_dcr(u16);
  57
  58 DECLARE_GLOBAL_DATA_PTR;
  59
  60 void pic_enable(void)
  61 {
  62 #if (UIC_MAX > 1)
  63         /* Install the UIC1 handlers */
  64         irq_install_handler(VECNUM_UIC1NCI, (void *)(void *)external_interrupt, 0);
  65         irq_install_handler(VECNUM_UIC1CI, (void *)(void *)external_interrupt, 0);
  66 #endif
  67 #if (UIC_MAX > 2)
  68         irq_install_handler(VECNUM_UIC2NCI, (void *)(void *)external_interrupt, 0);
  69         irq_install_handler(VECNUM_UIC2CI, (void *)(void *)external_interrupt, 0);
  70 #endif
  71 #if (UIC_MAX > 3)
  72         irq_install_handler(VECNUM_UIC3NCI, (void *)(void *)external_interrupt, 0);
  73         irq_install_handler(VECNUM_UIC3CI, (void *)(void *)external_interrupt, 0);
  74 #endif
  75 }
  76
  77 /* Handler for UIC interrupt */
  78 static void uic_interrupt(u32 uic_base, int vec_base)
  79 {
  80         u32 uic_msr;
  81         u32 msr_shift;
  82         int vec;
  83
  84         /*
  85          * Read masked interrupt status register to determine interrupt source
  86          */
  87         uic_msr = get_dcr(uic_base + UIC_MSR);
  88         msr_shift = uic_msr;
  89         vec = vec_base;
  90
  91         while (msr_shift != 0) {
  92                 if (msr_shift & 0x80000000)
  93                         interrupt_run_handler(vec);
  94                 /*
  95                  * Shift msr to next position and increment vector
  96                  */
  97                 msr_shift <<= 1;
  98                 vec++;
  99         }
 100 }
 101
 102 /*
 103  * Handle external interrupts
 104  */
 105 void external_interrupt(struct pt_regs *regs)
 106 {
 107         u32 uic_msr;
 108
 109         /*
 110          * Read masked interrupt status register to determine interrupt source
 111          */
 112         uic_msr = mfdcr(UIC0MSR);
 113
 114 #if (UIC_MAX > 1)
 115         if ((UIC_MASK(VECNUM_UIC1CI) & uic_msr) ||
 116             (UIC_MASK(VECNUM_UIC1NCI) & uic_msr))
 117                 uic_interrupt(UIC1_DCR_BASE, 32);
 118 #endif
 119
 120 #if (UIC_MAX > 2)
 121         if ((UIC_MASK(VECNUM_UIC2CI) & uic_msr) ||
 122             (UIC_MASK(VECNUM_UIC2NCI) & uic_msr))
 123                 uic_interrupt(UIC2_DCR_BASE, 64);
 124 #endif
 125
 126 #if (UIC_MAX > 3)
 127         if ((UIC_MASK(VECNUM_UIC3CI) & uic_msr) ||
 128             (UIC_MASK(VECNUM_UIC3NCI) & uic_msr))
 129                 uic_interrupt(UIC3_DCR_BASE, 96);
 130 #endif
 131
 132         mtdcr(UIC0SR, (uic_msr & UICB0_ALL));
 133
 134         if (uic_msr & ~(UICB0_ALL))
 135                 uic_interrupt(UIC0_DCR_BASE, 0);
 136
 137         return;
 138 }
 139
 140 void pic_irq_ack(unsigned int vec)
 141 {
 142         if ((vec >= 0) && (vec < 32))
 143                 mtdcr(UIC0SR, UIC_MASK(vec));
 144         else if ((vec >= 32) && (vec < 64))
 145                 mtdcr(UIC1SR, UIC_MASK(vec));
 146         else if ((vec >= 64) && (vec < 96))
 147                 mtdcr(UIC2SR, UIC_MASK(vec));
 148         else if (vec >= 96)
 149                 mtdcr(UIC3SR, UIC_MASK(vec));
 150 }
 151
 152 /*
 153  * Install and free a interrupt handler.
 154  */
 155 void pic_irq_enable(unsigned int vec)
 156 {
 157
 158         if ((vec >= 0) && (vec < 32))
 159                 mtdcr(UIC0ER, mfdcr(UIC0ER) | UIC_MASK(vec));
 160         else if ((vec >= 32) && (vec < 64))
 161                 mtdcr(UIC1ER, mfdcr(UIC1ER) | UIC_MASK(vec));
 162         else if ((vec >= 64) && (vec < 96))
 163                 mtdcr(UIC2ER, mfdcr(UIC2ER) | UIC_MASK(vec));
 164         else if (vec >= 96)
 165                 mtdcr(UIC3ER, mfdcr(UIC3ER) | UIC_MASK(vec));
 166
 167         debug("Install interrupt vector %d\n", vec);
 168 }
 169
 170 void pic_irq_disable(unsigned int vec)
 171 {
 172         if ((vec >= 0) && (vec < 32))
 173                 mtdcr(UIC0ER, mfdcr(UIC0ER) & ~UIC_MASK(vec));
 174         else if ((vec >= 32) && (vec < 64))
 175                 mtdcr(UIC1ER, mfdcr(UIC1ER) & ~UIC_MASK(vec));
 176         else if ((vec >= 64) && (vec < 96))
 177                 mtdcr(UIC2ER, mfdcr(UIC2ER) & ~UIC_MASK(vec));
 178         else if (vec >= 96)
 179                 mtdcr(UIC3ER, mfdcr(UIC3ER) & ~UIC_MASK(vec));
 180 }