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git.ipfire.org Git - people/ms/u-boot.git/blob - arch/powerpc/cpu/ppc4xx/uic.c
2 * (C) Copyright 2000-2002
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * (C) Copyright 2002 (440 port)
6 * Scott McNutt, Artesyn Communication Producs, smcnutt@artsyncp.com
8 * (C) Copyright 2003 (440GX port)
9 * Travis B. Sawyer, Sandburst Corporation, tsawyer@sandburst.com
11 * (C) Copyright 2008 (PPC440X05 port for Virtex 5 FX)
12 * Ricardo Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@gmail.com
13 * Work supported by Qtechnology (htpp://qtec.com)
15 * SPDX-License-Identifier: GPL-2.0+
21 #include <asm/processor.h>
22 #include <asm/interrupt.h>
23 #include <asm/ppc4xx.h>
24 #include <ppc_asm.tmpl>
28 #define UICB0_ALL (UIC_MASK(VECNUM_UIC1CI) | UIC_MASK(VECNUM_UIC1NCI) | \
29 UIC_MASK(VECNUM_UIC2CI) | UIC_MASK(VECNUM_UIC2NCI) | \
30 UIC_MASK(VECNUM_UIC3CI) | UIC_MASK(VECNUM_UIC3NCI))
32 #define UICB0_ALL (UIC_MASK(VECNUM_UIC1CI) | UIC_MASK(VECNUM_UIC1NCI) | \
33 UIC_MASK(VECNUM_UIC2CI) | UIC_MASK(VECNUM_UIC2NCI))
35 #define UICB0_ALL (UIC_MASK(VECNUM_UIC1CI) | UIC_MASK(VECNUM_UIC1NCI))
42 DECLARE_GLOBAL_DATA_PTR
;
47 /* Install the UIC1 handlers */
48 irq_install_handler(VECNUM_UIC1NCI
, (void *)(void *)external_interrupt
, 0);
49 irq_install_handler(VECNUM_UIC1CI
, (void *)(void *)external_interrupt
, 0);
52 irq_install_handler(VECNUM_UIC2NCI
, (void *)(void *)external_interrupt
, 0);
53 irq_install_handler(VECNUM_UIC2CI
, (void *)(void *)external_interrupt
, 0);
56 irq_install_handler(VECNUM_UIC3NCI
, (void *)(void *)external_interrupt
, 0);
57 irq_install_handler(VECNUM_UIC3CI
, (void *)(void *)external_interrupt
, 0);
61 /* Handler for UIC interrupt */
62 static void uic_interrupt(u32 uic_base
, int vec_base
)
69 * Read masked interrupt status register to determine interrupt source
71 uic_msr
= get_dcr(uic_base
+ UIC_MSR
);
75 while (msr_shift
!= 0) {
76 if (msr_shift
& 0x80000000)
77 interrupt_run_handler(vec
);
79 * Shift msr to next position and increment vector
87 * Handle external interrupts
89 void external_interrupt(struct pt_regs
*regs
)
94 * Read masked interrupt status register to determine interrupt source
96 uic_msr
= mfdcr(UIC0MSR
);
99 if ((UIC_MASK(VECNUM_UIC1CI
) & uic_msr
) ||
100 (UIC_MASK(VECNUM_UIC1NCI
) & uic_msr
))
101 uic_interrupt(UIC1_DCR_BASE
, 32);
105 if ((UIC_MASK(VECNUM_UIC2CI
) & uic_msr
) ||
106 (UIC_MASK(VECNUM_UIC2NCI
) & uic_msr
))
107 uic_interrupt(UIC2_DCR_BASE
, 64);
111 if ((UIC_MASK(VECNUM_UIC3CI
) & uic_msr
) ||
112 (UIC_MASK(VECNUM_UIC3NCI
) & uic_msr
))
113 uic_interrupt(UIC3_DCR_BASE
, 96);
116 mtdcr(UIC0SR
, (uic_msr
& UICB0_ALL
));
118 if (uic_msr
& ~(UICB0_ALL
))
119 uic_interrupt(UIC0_DCR_BASE
, 0);
124 void pic_irq_ack(unsigned int vec
)
126 if ((vec
>= 0) && (vec
< 32))
127 mtdcr(UIC0SR
, UIC_MASK(vec
));
128 else if ((vec
>= 32) && (vec
< 64))
129 mtdcr(UIC1SR
, UIC_MASK(vec
));
130 else if ((vec
>= 64) && (vec
< 96))
131 mtdcr(UIC2SR
, UIC_MASK(vec
));
133 mtdcr(UIC3SR
, UIC_MASK(vec
));
137 * Install and free a interrupt handler.
139 void pic_irq_enable(unsigned int vec
)
142 if ((vec
>= 0) && (vec
< 32))
143 mtdcr(UIC0ER
, mfdcr(UIC0ER
) | UIC_MASK(vec
));
144 else if ((vec
>= 32) && (vec
< 64))
145 mtdcr(UIC1ER
, mfdcr(UIC1ER
) | UIC_MASK(vec
));
146 else if ((vec
>= 64) && (vec
< 96))
147 mtdcr(UIC2ER
, mfdcr(UIC2ER
) | UIC_MASK(vec
));
149 mtdcr(UIC3ER
, mfdcr(UIC3ER
) | UIC_MASK(vec
));
151 debug("Install interrupt vector %d\n", vec
);
154 void pic_irq_disable(unsigned int vec
)
156 if ((vec
>= 0) && (vec
< 32))
157 mtdcr(UIC0ER
, mfdcr(UIC0ER
) & ~UIC_MASK(vec
));
158 else if ((vec
>= 32) && (vec
< 64))
159 mtdcr(UIC1ER
, mfdcr(UIC1ER
) & ~UIC_MASK(vec
));
160 else if ((vec
>= 64) && (vec
< 96))
161 mtdcr(UIC2ER
, mfdcr(UIC2ER
) & ~UIC_MASK(vec
));
163 mtdcr(UIC3ER
, mfdcr(UIC3ER
) & ~UIC_MASK(vec
));