arch/powerpc/include/asm/config.h

   1 /*
   2  * Copyright 2009-2011 Freescale Semiconductor, Inc.
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 #ifndef _ASM_CONFIG_H_
   8 #define _ASM_CONFIG_H_
   9
  10 #ifdef CONFIG_MPC85xx
  11 #include <asm/config_mpc85xx.h>
  12 #endif
  13
  14 #ifdef CONFIG_MPC86xx
  15 #include <asm/config_mpc86xx.h>
  16 #endif
  17
  18 #ifdef CONFIG_MPC83xx
  19 #endif
  20
  21 #ifndef HWCONFIG_BUFFER_SIZE
  22   #define HWCONFIG_BUFFER_SIZE 256
  23 #endif
  24
  25 /* CONFIG_HARD_SPI triggers SPI bus initialization in PowerPC */
  26 #if defined(CONFIG_MPC8XXX_SPI) || defined(CONFIG_FSL_ESPI)
  27 # ifndef CONFIG_HARD_SPI
  28 #  define CONFIG_HARD_SPI
  29 # endif
  30 #endif
  31
  32 #define CONFIG_LMB
  33 #define CONFIG_SYS_BOOT_RAMDISK_HIGH
  34 #define CONFIG_SYS_BOOT_GET_CMDLINE
  35 #define CONFIG_SYS_BOOT_GET_KBD
  36
  37 #ifndef CONFIG_MAX_MEM_MAPPED
  38 #if     defined(CONFIG_E500)            || \
  39         defined(CONFIG_MPC86xx)         || \
  40         defined(CONFIG_E300)
  41 #define CONFIG_MAX_MEM_MAPPED   ((phys_size_t)2 << 30)
  42 #else
  43 #define CONFIG_MAX_MEM_MAPPED   (256 << 20)
  44 #endif
  45 #endif
  46
  47 /* Check if boards need to enable FSL DMA engine for SDRAM init */
  48 #if !defined(CONFIG_FSL_DMA) && defined(CONFIG_DDR_ECC)
  49 #if (defined(CONFIG_MPC83xx) && defined(CONFIG_DDR_ECC_INIT_VIA_DMA)) || \
  50         ((defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx)) && \
  51         !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER))
  52 #define CONFIG_FSL_DMA
  53 #endif
  54 #endif
  55
  56 /*
  57  * Provide a default boot page translation virtual address that lines up with
  58  * Freescale's default e500 reset page.
  59  */
  60 #if (defined(CONFIG_E500) && defined(CONFIG_MP))
  61 #ifndef CONFIG_BPTR_VIRT_ADDR
  62 #define CONFIG_BPTR_VIRT_ADDR   0xfffff000
  63 #endif
  64 #endif
  65
  66 /* Since so many PPC SOCs have a semi-common LBC, define this here */
  67 #if defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx) || \
  68         defined(CONFIG_MPC83xx)
  69 #if !defined(CONFIG_FSL_IFC)
  70 #define CONFIG_FSL_LBC
  71 #endif
  72 #endif
  73
  74 /* The TSEC driver uses the PHYLIB infrastructure */
  75 #ifndef CONFIG_PHYLIB
  76 #if defined(CONFIG_TSEC_ENET)
  77 #define CONFIG_PHYLIB
  78
  79 #include <config_phylib_all_drivers.h>
  80 #endif /* TSEC_ENET */
  81 #endif /* !CONFIG_PHYLIB */
  82
  83 /* The FMAN driver uses the PHYLIB infrastructure */
  84 #if defined(CONFIG_FMAN_ENET)
  85 #define CONFIG_PHYLIB
  86 #endif
  87
  88 /* All PPC boards must swap IDE bytes */
  89 #define CONFIG_IDE_SWAP_IO
  90
  91 #if defined(CONFIG_DM_SERIAL)
  92 /*
  93  * TODO: Convert this to a clock driver exists that can give us the UART
  94  * clock here.
  95  */
  96 #define CONFIG_SYS_NS16550_CLK          get_serial_clock()
  97 #endif
  98
  99 #endif /* _ASM_CONFIG_H_ */