arch/powerpc/include/asm/config.h

   1 /*
   2  * Copyright 2009-2010 Freescale Semiconductor, Inc.
   3  *
   4  * This program is free software; you can redistribute it and/or
   5  * modify it under the terms of the GNU General Public License as
   6  * published by the Free Software Foundation; either version 2 of
   7  * the License, or (at your option) any later version.
   8  *
   9  * This program is distributed in the hope that it will be useful,
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  * GNU General Public License for more details.
  13  *
  14  * You should have received a copy of the GNU General Public License
  15  * along with this program; if not, write to the Free Software
  16  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  17  * MA 02111-1307 USA
  18  *
  19  */
  20
  21 #ifndef _ASM_CONFIG_H_
  22 #define _ASM_CONFIG_H_
  23
  24 #define CONFIG_LMB
  25
  26 #ifndef CONFIG_MAX_MEM_MAPPED
  27 #if defined(CONFIG_4xx) || defined(CONFIG_E500) || defined(CONFIG_MPC86xx)
  28 #define CONFIG_MAX_MEM_MAPPED   ((phys_size_t)2 << 30)
  29 #else
  30 #define CONFIG_MAX_MEM_MAPPED   (256 << 20)
  31 #endif
  32 #endif
  33
  34 /* Check if boards need to enable FSL DMA engine for SDRAM init */
  35 #if !defined(CONFIG_FSL_DMA) && defined(CONFIG_DDR_ECC)
  36 #if (defined(CONFIG_MPC83xx) && defined(CONFIG_DDR_ECC_INIT_VIA_DMA)) || \
  37         ((defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx)) && \
  38         !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER))
  39 #define CONFIG_FSL_DMA
  40 #endif
  41 #endif
  42
  43 #if defined(CONFIG_MPC8572) || defined(CONFIG_P1020) || \
  44         defined(CONFIG_P1021) || defined(CONFIG_P1022) || \
  45         defined(CONFIG_P2020) || defined(CONFIG_MPC8641)
  46 #define CONFIG_MAX_CPUS         2
  47 #elif defined(CONFIG_PPC_P3041)
  48 #define CONFIG_MAX_CPUS         4
  49 #elif defined(CONFIG_PPC_P4080)
  50 #define CONFIG_MAX_CPUS         8
  51 #elif defined(CONFIG_PPC_P5020)
  52 #define CONFIG_MAX_CPUS         2
  53 #else
  54 #define CONFIG_MAX_CPUS         1
  55 #endif
  56
  57 /*
  58  * Provide a default boot page translation virtual address that lines up with
  59  * Freescale's default e500 reset page.
  60  */
  61 #if (defined(CONFIG_E500) && defined(CONFIG_MP))
  62 #ifndef CONFIG_BPTR_VIRT_ADDR
  63 #define CONFIG_BPTR_VIRT_ADDR   0xfffff000
  64 #endif
  65 #endif
  66
  67 /* Enable TSEC2.0 for the platforms that have it if we are using TSEC */
  68 #if defined(CONFIG_TSEC_ENET) && \
  69     (defined(CONFIG_P1020) || defined(CONFIG_P1011))
  70 #define CONFIG_TSECV2
  71 #endif
  72
  73 /*
  74  * SEC (crypto unit) major compatible version determination
  75  */
  76 #if defined(CONFIG_FSL_CORENET)
  77 #define CONFIG_SYS_FSL_SEC_COMPAT       4
  78 #elif defined(CONFIG_MPC85xx) || defined(CONFIG_MPC83xx)
  79 #define CONFIG_SYS_FSL_SEC_COMPAT       2
  80 #endif
  81
  82 /* Number of TLB CAM entries we have on FSL Book-E chips */
  83 #if defined(CONFIG_E500MC)
  84 #define CONFIG_SYS_NUM_TLBCAMS  64
  85 #elif defined(CONFIG_E500)
  86 #define CONFIG_SYS_NUM_TLBCAMS  16
  87 #endif
  88
  89 /* Relocation to SDRAM works on all PPC boards */
  90 #define CONFIG_RELOC_FIXUP_WORKS
  91
  92 /* Since so many PPC SOCs have a semi-common LBC, define this here */
  93 #if defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx) || \
  94         defined(CONFIG_MPC83xx)
  95 #define CONFIG_FSL_LBC
  96 #endif
  97
  98 #endif /* _ASM_CONFIG_H_ */