arch/powerpc/include/asm/fsl_dma.h

   1 /*
   2  * Freescale DMA Controller
   3  *
   4  * Copyright 2006 Freescale Semiconductor, Inc.
   5  *
   6  * This software may be used and distributed according to the
   7  * terms of the GNU Public License, Version 2, incorporated
   8  * herein by reference.
   9  *
  10  * This program is free software; you can redistribute it and/or
  11  * modify it under the terms of the GNU General Public License
  12  * Version 2 as published by the Free Software Foundation.
  13  *
  14  * This program is distributed in the hope that it will be useful,
  15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  * GNU General Public License for more details.
  18  *
  19  * You should have received a copy of the GNU General Public License
  20  * along with this program; if not, write to the Free Software
  21  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  22  * MA 02111-1307 USA
  23  */
  24
  25 #ifndef _ASM_FSL_DMA_H_
  26 #define _ASM_FSL_DMA_H_
  27
  28 #include <asm/types.h>
  29
  30 #ifdef CONFIG_MPC83xx
  31 typedef struct fsl_dma {
  32         uint    mr;             /* DMA mode register */
  33 #define FSL_DMA_MR_CS           0x00000001      /* Channel start */
  34 #define FSL_DMA_MR_CC           0x00000002      /* Channel continue */
  35 #define FSL_DMA_MR_CTM          0x00000004      /* Channel xfer mode */
  36 #define FSL_DMA_MR_CTM_DIRECT   0x00000004      /* Direct channel xfer mode */
  37 #define FSL_DMA_MR_EOTIE        0x00000080      /* End-of-transfer interrupt en */
  38 #define FSL_DMA_MR_PRC_MASK     0x00000c00      /* PCI read command */
  39 #define FSL_DMA_MR_SAHE         0x00001000      /* Source addr hold enable */
  40 #define FSL_DMA_MR_DAHE         0x00002000      /* Dest addr hold enable */
  41 #define FSL_DMA_MR_SAHTS_MASK   0x0000c000      /* Source addr hold xfer size */
  42 #define FSL_DMA_MR_DAHTS_MASK   0x00030000      /* Dest addr hold xfer size */
  43 #define FSL_DMA_MR_EMS_EN       0x00040000      /* Ext master start en */
  44 #define FSL_DMA_MR_IRQS         0x00080000      /* Interrupt steer */
  45 #define FSL_DMA_MR_DMSEN        0x00100000      /* Direct mode snooping en */
  46 #define FSL_DMA_MR_BWC_MASK     0x00e00000      /* Bandwidth/pause ctl */
  47 #define FSL_DMA_MR_DRCNT        0x0f000000      /* DMA request count */
  48         uint    sr;             /* DMA status register */
  49 #define FSL_DMA_SR_EOCDI        0x00000001      /* End-of-chain/direct interrupt */
  50 #define FSL_DMA_SR_EOSI         0x00000002      /* End-of-segment interrupt */
  51 #define FSL_DMA_SR_CB           0x00000004      /* Channel busy */
  52 #define FSL_DMA_SR_TE           0x00000080      /* Transfer error */
  53         uint    cdar;           /* DMA current descriptor address register */
  54         char    res0[4];
  55         uint    sar;            /* DMA source address register */
  56         char    res1[4];
  57         uint    dar;            /* DMA destination address register */
  58         char    res2[4];
  59         uint    bcr;            /* DMA byte count register */
  60         uint    ndar;           /* DMA next descriptor address register */
  61         uint    gsr;            /* DMA general status register (DMA3 ONLY!) */
  62         char    res3[84];
  63 } fsl_dma_t;
  64 #else
  65 typedef struct fsl_dma {
  66         uint    mr;             /* DMA mode register */
  67 #define FSL_DMA_MR_CS           0x00000001      /* Channel start */
  68 #define FSL_DMA_MR_CC           0x00000002      /* Channel continue */
  69 #define FSL_DMA_MR_CTM          0x00000004      /* Channel xfer mode */
  70 #define FSL_DMA_MR_CTM_DIRECT   0x00000004      /* Direct channel xfer mode */
  71 #define FSL_DMA_MR_CA           0x00000008      /* Channel abort */
  72 #define FSL_DMA_MR_CDSM         0x00000010
  73 #define FSL_DMA_MR_XFE          0x00000020      /* Extended features en */
  74 #define FSL_DMA_MR_EIE          0x00000040      /* Error interrupt en */
  75 #define FSL_DMA_MR_EOLSIE       0x00000080      /* End-of-lists interrupt en */
  76 #define FSL_DMA_MR_EOLNIE       0x00000100      /* End-of-links interrupt en */
  77 #define FSL_DMA_MR_EOSIE        0x00000200      /* End-of-seg interrupt en */
  78 #define FSL_DMA_MR_SRW          0x00000400      /* Single register write */
  79 #define FSL_DMA_MR_SAHE         0x00001000      /* Source addr hold enable */
  80 #define FSL_DMA_MR_DAHE         0x00002000      /* Dest addr hold enable */
  81 #define FSL_DMA_MR_SAHTS_MASK   0x0000c000      /* Source addr hold xfer size */
  82 #define FSL_DMA_MR_DAHTS_MASK   0x00030000      /* Dest addr hold xfer size */
  83 #define FSL_DMA_MR_EMS_EN       0x00040000      /* Ext master start en */
  84 #define FSL_DMA_MR_EMP_EN       0x00200000      /* Ext master pause en */
  85 #define FSL_DMA_MR_BWC_MASK     0x0f000000      /* Bandwidth/pause ctl */
  86 #define FSL_DMA_MR_BWC_DIS      0x0f000000      /* Bandwidth/pause ctl disable */
  87         uint    sr;             /* DMA status register */
  88 #define FSL_DMA_SR_EOLSI        0x00000001      /* End-of-list interrupt */
  89 #define FSL_DMA_SR_EOSI         0x00000002      /* End-of-segment interrupt */
  90 #define FSL_DMA_SR_CB           0x00000004      /* Channel busy */
  91 #define FSL_DMA_SR_EOLNI        0x00000008      /* End-of-links interrupt */
  92 #define FSL_DMA_SR_PE           0x00000010      /* Programming error */
  93 #define FSL_DMA_SR_CH           0x00000020      /* Channel halted */
  94 #define FSL_DMA_SR_TE           0x00000080      /* Transfer error */
  95         char    res0[4];
  96         uint    clndar;         /* DMA current link descriptor address register */
  97         uint    satr;           /* DMA source attributes register */
  98 #define FSL_DMA_SATR_ESAD_MASK          0x000001ff      /* Extended source addr */
  99 #define FSL_DMA_SATR_SREAD_NO_SNOOP     0x00040000      /* Read, don't snoop */
 100 #define FSL_DMA_SATR_SREAD_SNOOP        0x00050000      /* Read, snoop */
 101 #define FSL_DMA_SATR_SREAD_UNLOCK       0x00070000      /* Read, unlock l2 */
 102 #define FSL_DMA_SATR_STRAN_MASK         0x00f00000      /* Source interface  */
 103 #define FSL_DMA_SATR_SSME               0x01000000      /* Source stride en */
 104 #define FSL_DMA_SATR_SPCIORDER          0x02000000      /* PCI transaction order */
 105 #define FSL_DMA_SATR_STFLOWLVL_MASK     0x0c000000      /* RIO flow level */
 106 #define FSL_DMA_SATR_SBPATRMU           0x20000000      /* Bypass ATMU */
 107         uint    sar;            /* DMA source address register */
 108         uint    datr;           /* DMA destination attributes register */
 109 #define FSL_DMA_DATR_EDAD_MASK          0x000001ff      /* Extended dest addr */
 110 #define FSL_DMA_DATR_DWRITE_NO_SNOOP    0x00040000      /* Write, don't snoop */
 111 #define FSL_DMA_DATR_DWRITE_SNOOP       0x00050000      /* Write, snoop */
 112 #define FSL_DMA_DATR_DWRITE_ALLOC       0x00060000      /* Write, alloc l2 */
 113 #define FSL_DMA_DATR_DWRITE_LOCK        0x00070000      /* Write, lock l2 */
 114 #define FSL_DMA_DATR_DTRAN_MASK         0x00f00000      /* Dest interface  */
 115 #define FSL_DMA_DATR_DSME               0x01000000      /* Dest stride en */
 116 #define FSL_DMA_DATR_DPCIORDER          0x02000000      /* PCI transaction order */
 117 #define FSL_DMA_DATR_DTFLOWLVL_MASK     0x0c000000      /* RIO flow level */
 118 #define FSL_DMA_DATR_DBPATRMU           0x20000000      /* Bypass ATMU */
 119         uint    dar;            /* DMA destination address register */
 120         uint    bcr;            /* DMA byte count register */
 121         char    res1[4];
 122         uint    nlndar;         /* DMA next link descriptor address register */
 123         char    res2[8];
 124         uint    clabdar;        /* DMA current List - alternate base descriptor address Register */
 125         char    res3[4];
 126         uint    nlsdar;         /* DMA next list descriptor address register */
 127         uint    ssr;            /* DMA source stride register */
 128         uint    dsr;            /* DMA destination stride register */
 129         char    res4[56];
 130 } fsl_dma_t;
 131 #endif /* !CONFIG_MPC83xx */
 132
 133 #ifdef CONFIG_FSL_DMA
 134 void dma_init(void);
 135 int dmacpy(phys_addr_t dest, phys_addr_t src, phys_size_t n);
 136 #if (defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER))
 137 void dma_meminit(uint val, uint size);
 138 #endif
 139 #endif
 140
 141 #endif  /* _ASM_DMA_H_ */