2 * Copyright 2008-2011 Freescale Semiconductor, Inc.
4 * SPDX-License-Identifier: GPL-2.0
11 #include <linux/log2.h>
13 #define LAW_EN 0x80000000
15 #define SET_LAW_ENTRY(idx, a, sz, trgt) \
16 { .index = idx, .addr = a, .size = sz, .trgt_id = trgt }
18 #define SET_LAW(a, sz, trgt) \
19 { .index = -1, .addr = a, .size = sz, .trgt_id = trgt }
48 #define law_size_bits(sz) (__ilog2_u64(sz) - 1)
49 #define lawar_size(x) (1ULL << ((x & 0x3f) + 1))
51 #ifdef CONFIG_FSL_CORENET
53 LAW_TRGT_IF_PCIE_1
= 0x00,
54 LAW_TRGT_IF_PCIE_2
= 0x01,
55 LAW_TRGT_IF_PCIE_3
= 0x02,
56 LAW_TRGT_IF_PCIE_4
= 0x03,
57 LAW_TRGT_IF_RIO_1
= 0x08,
58 LAW_TRGT_IF_RIO_2
= 0x09,
60 LAW_TRGT_IF_DDR_1
= 0x10,
61 LAW_TRGT_IF_DDR_2
= 0x11, /* 2nd controller */
62 LAW_TRGT_IF_DDR_3
= 0x12,
63 LAW_TRGT_IF_DDR_4
= 0x13,
64 LAW_TRGT_IF_DDR_INTRLV
= 0x14,
65 LAW_TRGT_IF_DDR_INTLV_34
= 0x15,
66 LAW_TRGT_IF_DDR_INTLV_123
= 0x17,
67 LAW_TRGT_IF_DDR_INTLV_1234
= 0x16,
68 LAW_TRGT_IF_BMAN
= 0x18,
69 LAW_TRGT_IF_DCSR
= 0x1d,
70 LAW_TRGT_IF_CCSR
= 0x1e,
71 LAW_TRGT_IF_LBC
= 0x1f,
72 LAW_TRGT_IF_QMAN
= 0x3c,
74 LAW_TRGT_IF_MAPLE
= 0x50,
76 #define LAW_TRGT_IF_DDR LAW_TRGT_IF_DDR_1
77 #define LAW_TRGT_IF_IFC LAW_TRGT_IF_LBC
80 LAW_TRGT_IF_PCI
= 0x00,
81 LAW_TRGT_IF_PCI_2
= 0x01,
82 #ifndef CONFIG_MPC8641
83 LAW_TRGT_IF_PCIE_1
= 0x02,
85 #if defined(CONFIG_BSC9131) || defined(CONFIG_BSC9132)
86 LAW_TRGT_IF_OCN_DSP
= 0x03,
88 #if !defined(CONFIG_MPC8572) && !defined(CONFIG_P2020)
89 LAW_TRGT_IF_PCIE_3
= 0x03,
92 LAW_TRGT_IF_LBC
= 0x04,
93 LAW_TRGT_IF_CCSR
= 0x08,
94 LAW_TRGT_IF_DSP_CCSR
= 0x09,
95 LAW_TRGT_IF_PLATFORM_SRAM
= 0x0a,
96 LAW_TRGT_IF_DDR_INTRLV
= 0x0b,
97 LAW_TRGT_IF_RIO
= 0x0c,
98 #if defined(CONFIG_BSC9132)
99 LAW_TRGT_IF_CLASS_DSP
= 0x0d,
101 LAW_TRGT_IF_RIO_2
= 0x0d,
103 LAW_TRGT_IF_DPAA_SWP_SRAM
= 0x0e,
104 LAW_TRGT_IF_DDR
= 0x0f,
105 LAW_TRGT_IF_DDR_2
= 0x16, /* 2nd controller */
106 /* place holder for 3-way and 4-way interleaving */
109 LAW_TRGT_IF_DDR_INTLV_34
,
110 LAW_TRGT_IF_DDR_INTLV_123
,
111 LAW_TRGT_IF_DDR_INTLV_1234
,
113 #define LAW_TRGT_IF_DDR_1 LAW_TRGT_IF_DDR
114 #define LAW_TRGT_IF_PCI_1 LAW_TRGT_IF_PCI
115 #define LAW_TRGT_IF_PCIX LAW_TRGT_IF_PCI
116 #define LAW_TRGT_IF_PCIE_2 LAW_TRGT_IF_PCI_2
117 #define LAW_TRGT_IF_RIO_1 LAW_TRGT_IF_RIO
118 #define LAW_TRGT_IF_IFC LAW_TRGT_IF_LBC
120 #ifdef CONFIG_MPC8641
121 #define LAW_TRGT_IF_PCIE_1 LAW_TRGT_IF_PCI
124 #if defined(CONFIG_MPC8572) || defined(CONFIG_P2020)
125 #define LAW_TRGT_IF_PCIE_3 LAW_TRGT_IF_PCI
127 #endif /* CONFIG_FSL_CORENET */
133 enum law_trgt_if trgt_id
;
136 extern void set_law(u8 idx
, phys_addr_t addr
, enum law_size sz
, enum law_trgt_if id
);
137 extern int set_next_law(phys_addr_t addr
, enum law_size sz
, enum law_trgt_if id
);
138 extern int set_last_law(phys_addr_t addr
, enum law_size sz
, enum law_trgt_if id
);
139 extern int set_ddr_laws(u64 start
, u64 sz
, enum law_trgt_if id
);
140 extern struct law_entry
find_law(phys_addr_t addr
);
141 extern void disable_law(u8 idx
);
142 extern void init_laws(void);
143 extern void print_laws(void);
145 /* define in board code */
146 extern struct law_entry law_table
[];
147 extern int num_law_entries
;