arch/powerpc/include/asm/fsl_secure_boot.h

   1 /*
   2  * Copyright 2010-2011 Freescale Semiconductor, Inc.
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 #ifndef __FSL_SECURE_BOOT_H
   8 #define __FSL_SECURE_BOOT_H
   9 #include <asm/config_mpc85xx.h>
  10
  11 #ifdef CONFIG_SECURE_BOOT
  12 #if defined(CONFIG_FSL_CORENET)
  13 #define CONFIG_SYS_PBI_FLASH_BASE               0xc0000000
  14 #elif defined(CONFIG_TARGET_BSC9132QDS)
  15 #define CONFIG_SYS_PBI_FLASH_BASE               0xc8000000
  16 #elif defined(CONFIG_TARGET_C29XPCIE)
  17 #define CONFIG_SYS_PBI_FLASH_BASE               0xcc000000
  18 #else
  19 #define CONFIG_SYS_PBI_FLASH_BASE               0xce000000
  20 #endif
  21 #define CONFIG_SYS_PBI_FLASH_WINDOW             0xcff80000
  22
  23 #if defined(CONFIG_TARGET_B4860QDS) || \
  24         defined(CONFIG_TARGET_B4420QDS) || \
  25         defined(CONFIG_TARGET_T4160QDS) || \
  26         defined(CONFIG_TARGET_T4240QDS) || \
  27         defined(CONFIG_TARGET_T2080QDS) || \
  28         defined(CONFIG_TARGET_T2080RDB) || \
  29         defined(CONFIG_TARGET_T1040QDS) || \
  30         defined(CONFIG_TARGET_T1040RDB) || \
  31         defined(CONFIG_TARGET_T1040D4RDB) || \
  32         defined(CONFIG_TARGET_T1042RDB) || \
  33         defined(CONFIG_TARGET_T1042D4RDB) || \
  34         defined(CONFIG_TARGET_T1042RDB_PI) || \
  35         defined(CONFIG_ARCH_T1023) || \
  36         defined(CONFIG_ARCH_T1024)
  37 #ifndef CONFIG_SYS_RAMBOOT
  38 #define CONFIG_SYS_CPC_REINIT_F
  39 #endif
  40 #define CONFIG_KEY_REVOCATION
  41 #undef CONFIG_SYS_INIT_L3_ADDR
  42 #define CONFIG_SYS_INIT_L3_ADDR                 0xbff00000
  43 #endif
  44
  45 #if defined(CONFIG_RAMBOOT_PBL)
  46 #undef CONFIG_SYS_INIT_L3_ADDR
  47 #ifdef CONFIG_SYS_INIT_L3_VADDR
  48 #define CONFIG_SYS_INIT_L3_ADDR \
  49                         (CONFIG_SYS_INIT_L3_VADDR & ~0xFFF00000) | \
  50                                         0xbff00000
  51 #else
  52 #define CONFIG_SYS_INIT_L3_ADDR         0xbff00000
  53 #endif
  54 #endif
  55
  56 #if defined(CONFIG_TARGET_C29XPCIE)
  57 #define CONFIG_KEY_REVOCATION
  58 #endif
  59
  60 #if defined(CONFIG_ARCH_P3041)  ||      \
  61         defined(CONFIG_ARCH_P4080) ||   \
  62         defined(CONFIG_ARCH_P5020) ||   \
  63         defined(CONFIG_ARCH_P5040) ||   \
  64         defined(CONFIG_ARCH_P2041)
  65         #define CONFIG_FSL_TRUST_ARCH_v1
  66 #endif
  67
  68 #if defined(CONFIG_FSL_CORENET) && !defined(CONFIG_SYS_RAMBOOT)
  69 /* The key used for verification of next level images
  70  * is picked up from an Extension Table which has
  71  * been verified by the ISBC (Internal Secure boot Code)
  72  * in boot ROM of the SoC.
  73  * The feature is only applicable in case of NOR boot and is
  74  * not applicable in case of RAMBOOT (NAND, SD, SPI).
  75  */
  76 #define CONFIG_FSL_ISBC_KEY_EXT
  77 #endif
  78 #endif /* #ifdef CONFIG_SECURE_BOOT */
  79
  80 #ifdef CONFIG_CHAIN_OF_TRUST
  81 #ifdef CONFIG_SPL_BUILD
  82 /*
  83  * PPAACT and SPAACT table for PAMU must be placed on DDR after DDR init
  84  * due to space crunch on CPC and thus malloc will not work.
  85  */
  86 #define CONFIG_SPL_PPAACT_ADDR          0x2e000000
  87 #define CONFIG_SPL_SPAACT_ADDR          0x2f000000
  88 #define CONFIG_SPL_JR0_LIODN_S          454
  89 #define CONFIG_SPL_JR0_LIODN_NS         458
  90 /*
  91  * Define the key hash for U-Boot here if public/private key pair used to
  92  * sign U-boot are different from the SRK hash put in the fuse
  93  * Example of defining KEY_HASH is
  94  * #define CONFIG_SPL_UBOOT_KEY_HASH \
  95  *      "41066b564c6ffcef40ccbc1e0a5d0d519604000c785d97bbefd25e4d288d1c8b"
  96  * else leave it defined as NULL
  97  */
  98
  99 #define CONFIG_SPL_UBOOT_KEY_HASH       NULL
 100 #endif /* ifdef CONFIG_SPL_BUILD */
 101
 102 #define CONFIG_FSL_SEC_MON
 103
 104 #ifndef CONFIG_SPL_BUILD
 105 /*
 106  * fsl_setenv_chain_of_trust() must be called from
 107  * board_late_init()
 108  */
 109
 110 /* If Boot Script is not on NOR and is required to be copied on RAM */
 111 #ifdef CONFIG_BOOTSCRIPT_COPY_RAM
 112 #define CONFIG_BS_HDR_ADDR_RAM          0x00010000
 113 #define CONFIG_BS_HDR_ADDR_DEVICE       0x00800000
 114 #define CONFIG_BS_HDR_SIZE              0x00002000
 115 #define CONFIG_BS_ADDR_RAM              0x00012000
 116 #define CONFIG_BS_ADDR_DEVICE           0x00802000
 117 #define CONFIG_BS_SIZE                  0x00001000
 118
 119 #define CONFIG_BOOTSCRIPT_HDR_ADDR      CONFIG_BS_HDR_ADDR_RAM
 120 #else
 121
 122 /* The bootscript header address is different for B4860 because the NOR
 123  * mapping is different on B4 due to reduced NOR size.
 124  */
 125 #if defined(CONFIG_TARGET_B4860QDS) || defined(CONFIG_TARGET_B4420QDS)
 126 #define CONFIG_BOOTSCRIPT_HDR_ADDR      0xecc00000
 127 #elif defined(CONFIG_FSL_CORENET)
 128 #define CONFIG_BOOTSCRIPT_HDR_ADDR      0xe8e00000
 129 #elif defined(CONFIG_TARGET_BSC9132QDS)
 130 #define CONFIG_BOOTSCRIPT_HDR_ADDR      0x88020000
 131 #elif defined(CONFIG_TARGET_C29XPCIE)
 132 #define CONFIG_BOOTSCRIPT_HDR_ADDR      0xec020000
 133 #else
 134 #define CONFIG_BOOTSCRIPT_HDR_ADDR      0xee020000
 135 #endif
 136
 137 #endif /* #ifdef CONFIG_BOOTSCRIPT_COPY_RAM */
 138
 139 #include <config_fsl_chain_trust.h>
 140 #endif /* #ifndef CONFIG_SPL_BUILD */
 141 #endif /* #ifdef CONFIG_CHAIN_OF_TRUST */
 142 #endif