arch/powerpc/include/asm/fsl_serdes.h

   1 /*
   2  * Copyright 2010 Freescale Semiconductor, Inc.
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 #ifndef __FSL_SERDES_H
   8 #define __FSL_SERDES_H
   9
  10 #include <config.h>
  11
  12 enum srds_prtcl {
  13         NONE = 0,
  14         PCIE1,
  15         PCIE2,
  16         PCIE3,
  17         PCIE4,
  18         SATA1,
  19         SATA2,
  20         SRIO1,
  21         SRIO2,
  22         SGMII_FM1_DTSEC1,
  23         SGMII_FM1_DTSEC2,
  24         SGMII_FM1_DTSEC3,
  25         SGMII_FM1_DTSEC4,
  26         SGMII_FM1_DTSEC5,
  27         SGMII_FM1_DTSEC6,
  28         SGMII_FM1_DTSEC9,
  29         SGMII_FM1_DTSEC10,
  30         SGMII_FM2_DTSEC1,
  31         SGMII_FM2_DTSEC2,
  32         SGMII_FM2_DTSEC3,
  33         SGMII_FM2_DTSEC4,
  34         SGMII_FM2_DTSEC5,
  35         SGMII_FM2_DTSEC6,
  36         SGMII_FM2_DTSEC9,
  37         SGMII_FM2_DTSEC10,
  38         SGMII_TSEC1,
  39         SGMII_TSEC2,
  40         SGMII_TSEC3,
  41         SGMII_TSEC4,
  42         XAUI_FM1,
  43         XAUI_FM2,
  44         AURORA,
  45         CPRI1,
  46         CPRI2,
  47         CPRI3,
  48         CPRI4,
  49         CPRI5,
  50         CPRI6,
  51         CPRI7,
  52         CPRI8,
  53         XAUI_FM1_MAC9,
  54         XAUI_FM1_MAC10,
  55         XAUI_FM2_MAC9,
  56         XAUI_FM2_MAC10,
  57         HIGIG_FM1_MAC9,
  58         HIGIG_FM1_MAC10,
  59         HIGIG_FM2_MAC9,
  60         HIGIG_FM2_MAC10,
  61         QSGMII_FM1_A,           /* A indicates MACs 1-4 */
  62         QSGMII_FM1_B,           /* B indicates MACs 5,6,9,10 */
  63         QSGMII_FM2_A,
  64         QSGMII_FM2_B,
  65         XFI_FM1_MAC9,
  66         XFI_FM1_MAC10,
  67         XFI_FM2_MAC9,
  68         XFI_FM2_MAC10,
  69         INTERLAKEN,
  70         SGMII_SW1_DTSEC1,       /* SW indicates on L2 switch */
  71         SGMII_SW1_DTSEC2,
  72         SGMII_SW1_DTSEC3,
  73         SGMII_SW1_DTSEC4,
  74         SGMII_SW1_DTSEC5,
  75         SGMII_SW1_DTSEC6,
  76         QSGMII_SW1_A,           /* SW indicates on L2 swtich */
  77         QSGMII_SW1_B,
  78 };
  79
  80 enum srds {
  81         FSL_SRDS_1  = 0,
  82         FSL_SRDS_2  = 1,
  83         FSL_SRDS_3  = 2,
  84         FSL_SRDS_4  = 3,
  85 };
  86
  87 int is_serdes_configured(enum srds_prtcl device);
  88 void fsl_serdes_init(void);
  89
  90 #ifdef CONFIG_FSL_CORENET
  91 #ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
  92 int serdes_get_first_lane(u32 sd, enum srds_prtcl device);
  93 #else
  94 int serdes_get_first_lane(enum srds_prtcl device);
  95 #endif
  96 #ifdef CONFIG_SYS_P4080_ERRATUM_SERDES9
  97 void serdes_reset_rx(enum srds_prtcl device);
  98 #endif
  99 #endif
 100
 101 #endif /* __FSL_SERDES_H */