arch/powerpc/include/asm/immap_86xx.h

   1 /*
   2  * MPC86xx Internal Memory Map
   3  *
   4  * Copyright 2004, 2011 Freescale Semiconductor
   5  * Jeff Brown (Jeffrey@freescale.com)
   6  * Srikanth Srinivasan (srikanth.srinivasan@freescale.com)
   7  *
   8  */
   9
  10 #ifndef __IMMAP_86xx__
  11 #define __IMMAP_86xx__
  12
  13 #include <asm/types.h>
  14 #include <asm/fsl_dma.h>
  15 #include <asm/fsl_lbc.h>
  16 #include <asm/fsl_i2c.h>
  17
  18 /* Local-Access Registers and MCM Registers(0x0000-0x2000) */
  19 typedef struct ccsr_local_mcm {
  20         uint    ccsrbar;        /* 0x0 - Control Configuration Status Registers Base Address Register */
  21         char    res1[4];
  22         uint    altcbar;        /* 0x8 - Alternate Configuration Base Address Register */
  23         char    res2[4];
  24         uint    altcar;         /* 0x10 - Alternate Configuration Attribute Register */
  25         char    res3[12];
  26         uint    bptr;           /* 0x20 - Boot Page Translation Register */
  27         char    res4[3044];
  28         uint    lawbar0;        /* 0xc08 - Local Access Window 0 Base Address Register */
  29         char    res5[4];
  30         uint    lawar0;         /* 0xc10 - Local Access Window 0 Attributes Register */
  31         char    res6[20];
  32         uint    lawbar1;        /* 0xc28 - Local Access Window 1 Base Address Register */
  33         char    res7[4];
  34         uint    lawar1;         /* 0xc30 - Local Access Window 1 Attributes Register */
  35         char    res8[20];
  36         uint    lawbar2;        /* 0xc48 - Local Access Window 2 Base Address Register */
  37         char    res9[4];
  38         uint    lawar2;         /* 0xc50 - Local Access Window 2 Attributes Register */
  39         char    res10[20];
  40         uint    lawbar3;        /* 0xc68 - Local Access Window 3 Base Address Register */
  41         char    res11[4];
  42         uint    lawar3;         /* 0xc70 - Local Access Window 3 Attributes Register */
  43         char    res12[20];
  44         uint    lawbar4;        /* 0xc88 - Local Access Window 4 Base Address Register */
  45         char    res13[4];
  46         uint    lawar4;         /* 0xc90 - Local Access Window 4 Attributes Register */
  47         char    res14[20];
  48         uint    lawbar5;        /* 0xca8 - Local Access Window 5 Base Address Register */
  49         char    res15[4];
  50         uint    lawar5;         /* 0xcb0 - Local Access Window 5 Attributes Register */
  51         char    res16[20];
  52         uint    lawbar6;        /* 0xcc8 - Local Access Window 6 Base Address Register */
  53         char    res17[4];
  54         uint    lawar6;         /* 0xcd0 - Local Access Window 6 Attributes Register */
  55         char    res18[20];
  56         uint    lawbar7;        /* 0xce8 - Local Access Window 7 Base Address Register */
  57         char    res19[4];
  58         uint    lawar7;         /* 0xcf0 - Local Access Window 7 Attributes Register */
  59         char    res20[20];
  60         uint    lawbar8;        /* 0xd08 - Local Access Window 8 Base Address Register */
  61         char    res21[4];
  62         uint    lawar8;         /* 0xd10 - Local Access Window 8 Attributes Register */
  63         char    res22[20];
  64         uint    lawbar9;        /* 0xd28 - Local Access Window 9 Base Address Register */
  65         char    res23[4];
  66         uint    lawar9;         /* 0xd30 - Local Access Window 9 Attributes Register */
  67         char    res24[716];
  68         uint    abcr;           /* 0x1000 - MCM CCB Address Configuration Register */
  69         char    res25[4];
  70         uint    dbcr;           /* 0x1008 - MCM MPX data bus Configuration Register */
  71         char    res26[4];
  72         uint    pcr;            /* 0x1010 - MCM CCB Port Configuration Register */
  73         char    res27[44];
  74         uint    hpmr0;          /* 0x1040 - MCM HPM Threshold Count Register 0 */
  75         uint    hpmr1;          /* 0x1044 - MCM HPM Threshold Count Register 1 */
  76         uint    hpmr2;          /* 0x1048 - MCM HPM Threshold Count Register 2 */
  77         uint    hpmr3;          /* 0x104c - MCM HPM Threshold Count Register 3 */
  78         char    res28[16];
  79         uint    hpmr4;          /* 0x1060 - MCM HPM Threshold Count Register 4 */
  80         uint    hpmr5;          /* 0x1064 - MCM HPM Threshold Count Register 5 */
  81         uint    hpmccr;         /* 0x1068 - MCM HPM Cycle Count Register */
  82         char    res29[3476];
  83         uint    edr;            /* 0x1e00 - MCM Error Detect Register */
  84         char    res30[4];
  85         uint    eer;            /* 0x1e08 - MCM Error Enable Register */
  86         uint    eatr;           /* 0x1e0c - MCM Error Attributes Capture Register */
  87         uint    eladr;          /* 0x1e10 - MCM Error Low Address Capture Register */
  88         uint    ehadr;          /* 0x1e14 - MCM Error High Address Capture Register */
  89         char    res31[488];
  90 } ccsr_local_mcm_t;
  91
  92 /* DDR memory controller registers(0x2000-0x3000) and (0x6000-0x7000) */
  93
  94 typedef struct ccsr_ddr {
  95         uint    cs0_bnds;               /* 0x2000 - DDR Chip Select 0 Memory Bounds */
  96         char    res1[4];
  97         uint    cs1_bnds;               /* 0x2008 - DDR Chip Select 1 Memory Bounds */
  98         char    res2[4];
  99         uint    cs2_bnds;               /* 0x2010 - DDR Chip Select 2 Memory Bounds */
 100         char    res3[4];
 101         uint    cs3_bnds;               /* 0x2018 - DDR Chip Select 3 Memory Bounds */
 102         char    res4[4];
 103         uint    cs4_bnds;               /* 0x2020 - DDR Chip Select 4 Memory Bounds */
 104         char    res5[4];
 105         uint    cs5_bnds;               /* 0x2028 - DDR Chip Select 5 Memory Bounds */
 106         char    res6[84];
 107         uint    cs0_config;             /* 0x2080 - DDR Chip Select Configuration */
 108         uint    cs1_config;             /* 0x2084 - DDR Chip Select Configuration */
 109         uint    cs2_config;             /* 0x2088 - DDR Chip Select Configuration */
 110         uint    cs3_config;             /* 0x208c - DDR Chip Select Configuration */
 111         uint    cs4_config;             /* 0x2090 - DDR Chip Select Configuration */
 112         uint    cs5_config;             /* 0x2094 - DDR Chip Select Configuration */
 113         char    res7[104];
 114         uint    timing_cfg_3;           /* 0x2100 - DDR SDRAM Timing Configuration Register 3 */
 115         uint    timing_cfg_0;           /* 0x2104 - DDR SDRAM Timing Configuration Register 0 */
 116         uint    timing_cfg_1;           /* 0x2108 - DDR SDRAM Timing Configuration Register 1 */
 117         uint    timing_cfg_2;           /* 0x210c - DDR SDRAM Timing Configuration Register 2 */
 118         uint    sdram_cfg;              /* 0x2110 - DDR SDRAM Control Configuration 1 */
 119         uint    sdram_cfg_2;            /* 0x2114 - DDR SDRAM Control Configuration 2 */
 120         uint    sdram_mode;             /* 0x2118 - DDR SDRAM Mode Configuration 1 */
 121         uint    sdram_mode_2;           /* 0x211c - DDR SDRAM Mode Configuration 2 */
 122         uint    sdram_mode_cntl;        /* 0x2120 - DDR SDRAM Mode Control */
 123         uint    sdram_interval;         /* 0x2124 - DDR SDRAM Interval Configuration */
 124         uint    sdram_data_init;        /* 0x2128 - DDR SDRAM Data Initialization */
 125         char    res8[4];
 126         uint    sdram_clk_cntl;         /* 0x2130 - DDR SDRAM Clock Control */
 127         char    res9[12];
 128         uint    sdram_ocd_cntl;         /* 0x2140 - DDR SDRAM OCD Control */
 129         uint    sdram_ocd_status;       /* 0x2144 - DDR SDRAM OCD Status */
 130         uint    init_addr;              /* 0x2148 - DDR training initialzation address */
 131         uint    init_ext_addr;          /* 0x214C - DDR training initialzation extended address */
 132         char    res10[2728];
 133         uint    ip_rev1;                /* 0x2BF8 - DDR IP Block Revision 1 */
 134         uint    ip_rev2;                /* 0x2BFC - DDR IP Block Revision 2 */
 135         char    res11[512];
 136         uint    data_err_inject_hi;     /* 0x2e00 - DDR Memory Data Path Error Injection Mask High */
 137         uint    data_err_inject_lo;     /* 0x2e04 - DDR Memory Data Path Error Injection Mask Low */
 138         uint    ecc_err_inject;         /* 0x2e08 - DDR Memory Data Path Error Injection Mask ECC */
 139         char    res12[20];
 140         uint    capture_data_hi;        /* 0x2e20 - DDR Memory Data Path Read Capture High */
 141         uint    capture_data_lo;        /* 0x2e24 - DDR Memory Data Path Read Capture Low */
 142         uint    capture_ecc;            /* 0x2e28 - DDR Memory Data Path Read Capture ECC */
 143         char    res13[20];
 144         uint    err_detect;             /* 0x2e40 - DDR Memory Error Detect */
 145         uint    err_disable;            /* 0x2e44 - DDR Memory Error Disable */
 146         uint    err_int_en;             /* 0x2e48 - DDR Memory Error Interrupt Enable */
 147         uint    capture_attributes;     /* 0x2e4c - DDR Memory Error Attributes Capture */
 148         uint    capture_address;        /* 0x2e50 - DDR Memory Error Address Capture */
 149         uint    capture_ext_address;    /* 0x2e54 - DDR Memory Error Extended Address Capture */
 150         uint    err_sbe;                /* 0x2e58 - DDR Memory Single-Bit ECC Error Management */
 151         char    res14[164];
 152         uint    debug_1;                /* 0x2f00 */
 153         uint    debug_2;
 154         uint    debug_3;
 155         uint    debug_4;
 156         uint    debug_5;
 157         char    res15[236];
 158 } ccsr_ddr_t;
 159
 160
 161 /* Daul I2C Registers(0x3000-0x4000) */
 162 typedef struct ccsr_i2c {
 163         struct fsl_i2c  i2c[2];
 164         u8      res[4096 - 2 * sizeof(struct fsl_i2c)];
 165 } ccsr_i2c_t;
 166
 167 /* DUART Registers(0x4000-0x5000) */
 168 typedef struct ccsr_duart {
 169         char    res1[1280];
 170         u_char  urbr1_uthr1_udlb1;/* 0x4500 - URBR1, UTHR1, UDLB1 with the same address offset of 0x04500 */
 171         u_char  uier1_udmb1;    /* 0x4501 - UIER1, UDMB1 with the same address offset of 0x04501 */
 172         u_char  uiir1_ufcr1_uafr1;/* 0x4502 - UIIR1, UFCR1, UAFR1 with the same address offset of 0x04502 */
 173         u_char  ulcr1;          /* 0x4503 - UART1 Line Control Register */
 174         u_char  umcr1;          /* 0x4504 - UART1 Modem Control Register */
 175         u_char  ulsr1;          /* 0x4505 - UART1 Line Status Register */
 176         u_char  umsr1;          /* 0x4506 - UART1 Modem Status Register */
 177         u_char  uscr1;          /* 0x4507 - UART1 Scratch Register */
 178         char    res2[8];
 179         u_char  udsr1;          /* 0x4510 - UART1 DMA Status Register */
 180         char    res3[239];
 181         u_char  urbr2_uthr2_udlb2;/* 0x4600 - URBR2, UTHR2, UDLB2 with the same address offset of 0x04600 */
 182         u_char  uier2_udmb2;    /* 0x4601 - UIER2, UDMB2 with the same address offset of 0x04601 */
 183         u_char  uiir2_ufcr2_uafr2;/* 0x4602 - UIIR2, UFCR2, UAFR2 with the same address offset of 0x04602 */
 184         u_char  ulcr2;          /* 0x4603 - UART2 Line Control Register */
 185         u_char  umcr2;          /* 0x4604 - UART2 Modem Control Register */
 186         u_char  ulsr2;          /* 0x4605 - UART2 Line Status Register */
 187         u_char  umsr2;          /* 0x4606 - UART2 Modem Status Register */
 188         u_char  uscr2;          /* 0x4607 - UART2 Scratch Register */
 189         char    res4[8];
 190         u_char  udsr2;          /* 0x4610 - UART2 DMA Status Register */
 191         char    res5[2543];
 192 } ccsr_duart_t;
 193
 194 /* PCI Express Registers(0x8000-0x9000) and (0x9000-0xA000) */
 195 typedef struct ccsr_pex {
 196         uint    cfg_addr;       /* 0x8000 - PEX Configuration Address Register */
 197         uint    cfg_data;       /* 0x8004 - PEX Configuration Data Register */
 198         char    res1[4];
 199         uint    out_comp_to;    /* 0x800C - PEX Outbound Completion Timeout Register */
 200         char    res2[16];
 201         uint    pme_msg_det;    /* 0x8020 - PEX PME & message detect register */
 202         uint    pme_msg_int_en; /* 0x8024 - PEX PME & message interrupt enable register */
 203         uint    pme_msg_dis;    /* 0x8028 - PEX PME & message disable register */
 204         uint    pm_command;     /* 0x802c - PEX PM Command register */
 205         char    res3[3016];
 206         uint    block_rev1;     /* 0x8bf8 - PEX Block Revision register 1 */
 207         uint    block_rev2;     /* 0x8bfc - PEX Block Revision register 2 */
 208         uint    potar0;         /* 0x8c00 - PEX Outbound Transaction Address Register 0 */
 209         uint    potear0;        /* 0x8c04 - PEX Outbound Translation Extended Address Register 0 */
 210         char    res4[8];
 211         uint    powar0;         /* 0x8c10 - PEX Outbound Window Attributes Register 0 */
 212         char    res5[12];
 213         uint    potar1;         /* 0x8c20 - PEX Outbound Transaction Address Register 1 */
 214         uint    potear1;        /* 0x8c24 - PEX Outbound Translation Extended Address Register 1 */
 215         uint    powbar1;        /* 0x8c28 - PEX Outbound Window Base Address Register 1 */
 216         char    res6[4];
 217         uint    powar1;         /* 0x8c30 - PEX Outbound Window Attributes Register 1 */
 218         char    res7[12];
 219         uint    potar2;         /* 0x8c40 - PEX Outbound Transaction Address Register 2 */
 220         uint    potear2;        /* 0x8c44 - PEX Outbound Translation Extended Address Register 2 */
 221         uint    powbar2;        /* 0x8c48 - PEX Outbound Window Base Address Register 2 */
 222         char    res8[4];
 223         uint    powar2;         /* 0x8c50 - PEX Outbound Window Attributes Register 2 */
 224         char    res9[12];
 225         uint    potar3;         /* 0x8c60 - PEX Outbound Transaction Address Register 3 */
 226         uint    potear3;        /* 0x8c64 - PEX Outbound Translation Extended Address Register 3 */
 227         uint    powbar3;        /* 0x8c68 - PEX Outbound Window Base Address Register 3 */
 228         char    res10[4];
 229         uint    powar3;         /* 0x8c70 - PEX Outbound Window Attributes Register 3 */
 230         char    res11[12];
 231         uint    potar4;         /* 0x8c80 - PEX Outbound Transaction Address Register 4 */
 232         uint    potear4;        /* 0x8c84 - PEX Outbound Translation Extended Address Register 4 */
 233         uint    powbar4;        /* 0x8c88 - PEX Outbound Window Base Address Register 4 */
 234         char    res12[4];
 235         uint    powar4;         /* 0x8c90 - PEX Outbound Window Attributes Register 4 */
 236         char    res13[12];
 237         char    res14[256];
 238         uint    pitar3;         /* 0x8da0 - PEX Inbound Translation Address Register 3  */
 239         char    res15[4];
 240         uint    piwbar3;        /* 0x8da8 - PEX Inbound Window Base Address Register 3 */
 241         uint    piwbear3;       /* 0x8dac - PEX Inbound Window Base Extended Address Register 3 */
 242         uint    piwar3;         /* 0x8db0 - PEX Inbound Window Attributes Register 3 */
 243         char    res16[12];
 244         uint    pitar2;         /* 0x8dc0 - PEX Inbound Translation Address Register 2  */
 245         char    res17[4];
 246         uint    piwbar2;        /* 0x8dc8 - PEX Inbound Window Base Address Register 2 */
 247         uint    piwbear2;       /* 0x8dcc - PEX Inbound Window Base Extended Address Register 2 */
 248         uint    piwar2;         /* 0x8dd0 - PEX Inbound Window Attributes Register 2 */
 249         char    res18[12];
 250         uint    pitar1;         /* 0x8de0 - PEX Inbound Translation Address Register 1  */
 251         char    res19[4];
 252         uint    piwbar1;        /* 0x8de8 - PEX Inbound Window Base Address Register 1 */
 253         uint    piwbear1;
 254         uint    piwar1;         /* 0x8df0 - PEX Inbound Window Attributes Register 1 */
 255         char    res20[12];
 256         uint    pedr;           /* 0x8e00 - PEX Error Detect Register */
 257         char    res21[4];
 258         uint    peer;           /* 0x8e08 - PEX Error Interrupt Enable Register */
 259         char    res22[4];
 260         uint    pecdr;          /* 0x8e10 - PEX Error Disable Register */
 261         char    res23[12];
 262         uint    peer_stat;      /* 0x8e20 - PEX Error Capture Status Register */
 263         char    res24[4];
 264         uint    perr_cap0;      /* 0x8e28 - PEX Error Capture Register 0 */
 265         uint    perr_cap1;      /* 0x8e2c - PEX Error Capture Register 1 */
 266         uint    perr_cap2;      /* 0x8e30 - PEX Error Capture Register 2 */
 267         uint    perr_cap3;      /* 0x8e34 - PEX Error Capture Register 3 */
 268         char    res25[452];
 269         char    res26[4];
 270 } ccsr_pex_t;
 271
 272 /* Hyper Transport Register Block (0xA000-0xB000) */
 273 typedef struct ccsr_ht {
 274         uint    hcfg_addr;      /* 0xa000 - HT Configuration Address register */
 275         uint    hcfg_data;      /* 0xa004 - HT Configuration Data register */
 276         char    res1[3064];
 277         uint    howtar0;        /* 0xac00 - HT Outbound Window 0 Translation register */
 278         char    res2[12];
 279         uint    howar0;         /* 0xac10 - HT Outbound Window 0 Attributes register */
 280         char    res3[12];
 281         uint    howtar1;        /* 0xac20 - HT Outbound Window 1 Translation register */
 282         char    res4[4];
 283         uint    howbar1;        /* 0xac28 - HT Outbound Window 1 Base Address register */
 284         char    res5[4];
 285         uint    howar1;         /* 0xac30 - HT Outbound Window 1 Attributes register */
 286         char    res6[12];
 287         uint    howtar2;        /* 0xac40 - HT Outbound Window 2 Translation register */
 288         char    res7[4];
 289         uint    howbar2;        /* 0xac48 - HT Outbound Window 2 Base Address register */
 290         char    res8[4];
 291         uint    howar2;         /* 0xac50 - HT Outbound Window 2 Attributes register */
 292         char    res9[12];
 293         uint    howtar3;        /* 0xac60 - HT Outbound Window 3 Translation register */
 294         char    res10[4];
 295         uint    howbar3;        /* 0xac68 - HT Outbound Window 3 Base Address register */
 296         char    res11[4];
 297         uint    howar3;         /* 0xac70 - HT Outbound Window 3 Attributes  register */
 298         char    res12[12];
 299         uint    howtar4;        /* 0xac80 - HT Outbound Window 4 Translation register */
 300         char    res13[4];
 301         uint    howbar4;        /* 0xac88 - HT Outbound Window 4 Base Address register */
 302         char    res14[4];
 303         uint    howar4;         /* 0xac90 - HT Outbound Window 4 Attributes register */
 304         char    res15[236];
 305         uint    hiwtar4;        /* 0xad80 - HT Inbound Window 4 Translation register */
 306         char    res16[4];
 307         uint    hiwbar4;        /* 0xad88 - HT Inbound Window 4 Base Address register */
 308         char    res17[4];
 309         uint    hiwar4;         /* 0xad90 - HT Inbound Window 4 Attributes register */
 310         char    res18[12];
 311         uint    hiwtar3;        /* 0xada0 - HT Inbound Window 3 Translation register */
 312         char    res19[4];
 313         uint    hiwbar3;        /* 0xada8 - HT Inbound Window 3 Base Address register */
 314         char    res20[4];
 315         uint    hiwar3;         /* 0xadb0 - HT Inbound Window 3 Attributes register */
 316         char    res21[12];
 317         uint    hiwtar2;        /* 0xadc0 - HT Inbound Window 2 Translation register */
 318         char    res22[4];
 319         uint    hiwbar2;        /* 0xadc8 - HT Inbound Window 2 Base Address register */
 320         char    res23[4];
 321         uint    hiwar2;         /* 0xadd0 - HT Inbound Window 2 Attributes register */
 322         char    res24[12];
 323         uint    hiwtar1;        /* 0xade0 - HT Inbound Window 1 Translation register */
 324         char    res25[4];
 325         uint    hiwbar1;        /* 0xade8 - HT Inbound Window 1 Base Address register */
 326         char    res26[4];
 327         uint    hiwar1;         /* 0xadf0 - HT Inbound Window 1 Attributes register */
 328         char    res27[12];
 329         uint    hedr;           /* 0xae00 - HT Error Detect register */
 330         char    res28[4];
 331         uint    heier;          /* 0xae08 - HT Error Interrupt Enable register */
 332         char    res29[4];
 333         uint    hecdr;          /* 0xae10 - HT Error Capture Disbale register */
 334         char    res30[12];
 335         uint    hecsr;          /* 0xae20 - HT Error Capture Status register */
 336         char    res31[4];
 337         uint    hec0;           /* 0xae28 - HT Error Capture 0 register */
 338         uint    hec1;           /* 0xae2c - HT Error Capture 1 register */
 339         uint    hec2;           /* 0xae30 - HT Error Capture 2 register */
 340         char    res32[460];
 341 } ccsr_ht_t;
 342
 343 /* DMA Registers(0x2_1000-0x2_2000) */
 344 typedef struct ccsr_dma {
 345         char    res1[256];
 346         struct fsl_dma dma[4];
 347         uint    dgsr;           /* 0x21300 - DMA General Status Register */
 348         char    res2[3324];
 349 } ccsr_dma_t;
 350
 351 /* tsec1-4: 24000-28000 */
 352 typedef struct ccsr_tsec {
 353         uint    id;             /* 0x24000 - Controller ID Register */
 354         char    res1[12];
 355         uint    ievent;         /* 0x24010 - Interrupt Event Register */
 356         uint    imask;          /* 0x24014 - Interrupt Mask Register */
 357         uint    edis;           /* 0x24018 - Error Disabled Register */
 358         char    res2[4];
 359         uint    ecntrl;         /* 0x24020 - Ethernet Control Register */
 360         char    res2_1[4];
 361         uint    ptv;            /* 0x24028 - Pause Time Value Register */
 362         uint    dmactrl;        /* 0x2402c - DMA Control Register */
 363         uint    tbipa;          /* 0x24030 - TBI PHY Address Register */
 364         char    res3[88];
 365         uint    fifo_tx_thr;    /* 0x2408c - FIFO transmit threshold register */
 366         char    res4[8];
 367         uint    fifo_tx_starve; /* 0x24098 - FIFO transmit starve register */
 368         uint    fifo_tx_starve_shutoff;/* 0x2409c - FIFO transmit starve shutoff register */
 369         char    res4_1[4];
 370         uint    fifo_rx_pause;  /* 0x240a4 - FIFO receive pause threshold register */
 371         uint    fifo_rx_alarm;  /* 0x240a8 - FIFO receive alarm threshold register */
 372         char    res5[84];
 373         uint    tctrl;          /* 0x24100 - Transmit Control Register */
 374         uint    tstat;          /* 0x24104 - Transmit Status Register */
 375         uint    dfvlan;         /* 0x24108 - Default VLAN control word */
 376         char    res6[4];
 377         uint    txic;           /* 0x24110 - Transmit interrupt coalescing Register */
 378         uint    tqueue;         /* 0x24114 - Transmit Queue Control Register */
 379         char    res7[40];
 380         uint    tr03wt;         /* 0x24140 - TxBD Rings 0-3 round-robin weightings */
 381         uint    tw47wt;         /* 0x24144 - TxBD Rings 4-7 round-robin weightings */
 382         char    res8[52];
 383         uint    tbdbph;         /* 0x2417c - Transmit Data Buffer Pointer High Register */
 384         char    res9[4];
 385         uint    tbptr0;         /* 0x24184 - Transmit Buffer Descriptor Pointer for Ring 0 */
 386         char    res10[4];
 387         uint    tbptr1;         /* 0x2418C - Transmit Buffer Descriptor Pointer for Ring 1 */
 388         char    res11[4];
 389         uint    tbptr2;         /* 0x24194 - Transmit Buffer Descriptor Pointer for Ring 2 */
 390         char    res12[4];
 391         uint    tbptr3;         /* 0x2419C - Transmit Buffer Descriptor Pointer for Ring 3 */
 392         char    res13[4];
 393         uint    tbptr4;         /* 0x241A4 - Transmit Buffer Descriptor Pointer for Ring 4 */
 394         char    res14[4];
 395         uint    tbptr5;         /* 0x241AC - Transmit Buffer Descriptor Pointer for Ring 5 */
 396         char    res15[4];
 397         uint    tbptr6;         /* 0x241B4 - Transmit Buffer Descriptor Pointer for Ring 6 */
 398         char    res16[4];
 399         uint    tbptr7;         /* 0x241BC - Transmit Buffer Descriptor Pointer for Ring 7 */
 400         char    res17[64];
 401         uint    tbaseh;         /* 0x24200 - Transmit Descriptor Base Address High Register */
 402         uint    tbase0;         /* 0x24204 - Transmit Descriptor Base Address Register of Ring 0 */
 403         char    res18[4];
 404         uint    tbase1;         /* 0x2420C - Transmit Descriptor base address of Ring 1 */
 405         char    res19[4];
 406         uint    tbase2;         /* 0x24214 - Transmit Descriptor base address of Ring 2 */
 407         char    res20[4];
 408         uint    tbase3;         /* 0x2421C - Transmit Descriptor base address of Ring 3 */
 409         char    res21[4];
 410         uint    tbase4;         /* 0x24224 - Transmit Descriptor base address of Ring 4 */
 411         char    res22[4];
 412         uint    tbase5;         /* 0x2422C - Transmit Descriptor base address of Ring 5 */
 413         char    res23[4];
 414         uint    tbase6;         /* 0x24234 - Transmit Descriptor base address of Ring 6 */
 415         char    res24[4];
 416         uint    tbase7;         /* 0x2423C - Transmit Descriptor base address of Ring 7 */
 417         char    res25[192];
 418         uint    rctrl;          /* 0x24300 - Receive Control Register */
 419         uint    rstat;          /* 0x24304 - Receive Status Register */
 420         char    res26[8];
 421         uint    rxic;           /* 0x24310 - Receive Interrupt Coalecing Register */
 422         uint    rqueue;         /* 0x24314 - Receive queue control register */
 423         char    res27[24];
 424         uint    rbifx;          /* 0x24330 - Receive bit field extract control Register */
 425         uint    rqfar;          /* 0x24334 - Receive queue filing table address Register */
 426         uint    rqfcr;          /* 0x24338 - Receive queue filing table control Register */
 427         uint    rqfpr;          /* 0x2433c - Receive queue filing table property Register */
 428         uint    mrblr;          /* 0x24340 - Maximum Receive Buffer Length Register */
 429         char    res28[56];
 430         uint    rbdbph;         /* 0x2437C - Receive Data Buffer Pointer High */
 431         char    res29[4];
 432         uint    rbptr0;         /* 0x24384 - Receive Buffer Descriptor Pointer for Ring 0 */
 433         char    res30[4];
 434         uint    rbptr1;         /* 0x2438C - Receive Buffer Descriptor Pointer for Ring 1 */
 435         char    res31[4];
 436         uint    rbptr2;         /* 0x24394 - Receive Buffer Descriptor Pointer for Ring 2 */
 437         char    res32[4];
 438         uint    rbptr3;         /* 0x2439C - Receive Buffer Descriptor Pointer for Ring 3 */
 439         char    res33[4];
 440         uint    rbptr4;         /* 0x243A4 - Receive Buffer Descriptor Pointer for Ring 4 */
 441         char    res34[4];
 442         uint    rbptr5;         /* 0x243AC - Receive Buffer Descriptor Pointer for Ring 5 */
 443         char    res35[4];
 444         uint    rbptr6;         /* 0x243B4 - Receive Buffer Descriptor Pointer for Ring 6 */
 445         char    res36[4];
 446         uint    rbptr7;         /* 0x243BC - Receive Buffer Descriptor Pointer for Ring 7 */
 447         char    res37[64];
 448         uint    rbaseh;         /* 0x24400 - Receive Descriptor Base Address High 0 */
 449         uint    rbase0;         /* 0x24404 - Receive Descriptor Base Address of Ring 0 */
 450         char    res38[4];
 451         uint    rbase1;         /* 0x2440C - Receive Descriptor Base Address of Ring 1 */
 452         char    res39[4];
 453         uint    rbase2;         /* 0x24414 - Receive Descriptor Base Address of Ring 2 */
 454         char    res40[4];
 455         uint    rbase3;         /* 0x2441C - Receive Descriptor Base Address of Ring 3 */
 456         char    res41[4];
 457         uint    rbase4;         /* 0x24424 - Receive Descriptor Base Address of Ring 4 */
 458         char    res42[4];
 459         uint    rbase5;         /* 0x2442C - Receive Descriptor Base Address of Ring 5 */
 460         char    res43[4];
 461         uint    rbase6;         /* 0x24434 - Receive Descriptor Base Address of Ring 6 */
 462         char    res44[4];
 463         uint    rbase7;         /* 0x2443C - Receive Descriptor Base Address of Ring 7 */
 464         char    res45[192];
 465         uint    maccfg1;        /* 0x24500 - MAC Configuration 1 Register */
 466         uint    maccfg2;        /* 0x24504 - MAC Configuration 2 Register */
 467         uint    ipgifg;         /* 0x24508 - Inter Packet Gap/Inter Frame Gap Register */
 468         uint    hafdup;         /* 0x2450c - Half Duplex Register */
 469         uint    maxfrm;         /* 0x24510 - Maximum Frame Length Register */
 470         char    res46[12];
 471         uint    miimcfg;        /* 0x24520 - MII Management Configuration Register */
 472         uint    miimcom;        /* 0x24524 - MII Management Command Register */
 473         uint    miimadd;        /* 0x24528 - MII Management Address Register */
 474         uint    miimcon;        /* 0x2452c - MII Management Control Register */
 475         uint    miimstat;       /* 0x24530 - MII Management Status Register */
 476         uint    miimind;        /* 0x24534 - MII Management Indicator Register */
 477         uint    ifctrl;         /* 0x24538 - Interface Contrl Register */
 478         uint    ifstat;         /* 0x2453c - Interface Status Register */
 479         uint    macstnaddr1;    /* 0x24540 - Station Address Part 1 Register */
 480         uint    macstnaddr2;    /* 0x24544 - Station Address Part 2 Register */
 481         uint    mac01addr1;     /* 0x24548 - MAC exact match address 1, part 1 */
 482         uint    mac01addr2;     /* 0x2454C - MAC exact match address 1, part 2 */
 483         uint    mac02addr1;     /* 0x24550 - MAC exact match address 2, part 1 */
 484         uint    mac02addr2;     /* 0x24554 - MAC exact match address 2, part 2 */
 485         uint    mac03addr1;     /* 0x24558 - MAC exact match address 3, part 1 */
 486         uint    mac03addr2;     /* 0x2455C - MAC exact match address 3, part 2 */
 487         uint    mac04addr1;     /* 0x24560 - MAC exact match address 4, part 1 */
 488         uint    mac04addr2;     /* 0x24564 - MAC exact match address 4, part 2 */
 489         uint    mac05addr1;     /* 0x24568 - MAC exact match address 5, part 1 */
 490         uint    mac05addr2;     /* 0x2456C - MAC exact match address 5, part 2 */
 491         uint    mac06addr1;     /* 0x24570 - MAC exact match address 6, part 1 */
 492         uint    mac06addr2;     /* 0x24574 - MAC exact match address 6, part 2 */
 493         uint    mac07addr1;     /* 0x24578 - MAC exact match address 7, part 1 */
 494         uint    mac07addr2;     /* 0x2457C - MAC exact match address 7, part 2 */
 495         uint    mac08addr1;     /* 0x24580 - MAC exact match address 8, part 1 */
 496         uint    mac08addr2;     /* 0x24584 - MAC exact match address 8, part 2 */
 497         uint    mac09addr1;     /* 0x24588 - MAC exact match address 9, part 1 */
 498         uint    mac09addr2;     /* 0x2458C - MAC exact match address 9, part 2 */
 499         uint    mac10addr1;     /* 0x24590 - MAC exact match address 10, part 1 */
 500         uint    mac10addr2;     /* 0x24594 - MAC exact match address 10, part 2 */
 501         uint    mac11addr1;     /* 0x24598 - MAC exact match address 11, part 1 */
 502         uint    mac11addr2;     /* 0x2459C - MAC exact match address 11, part 2 */
 503         uint    mac12addr1;     /* 0x245A0 - MAC exact match address 12, part 1 */
 504         uint    mac12addr2;     /* 0x245A4 - MAC exact match address 12, part 2 */
 505         uint    mac13addr1;     /* 0x245A8 - MAC exact match address 13, part 1 */
 506         uint    mac13addr2;     /* 0x245AC - MAC exact match address 13, part 2 */
 507         uint    mac14addr1;     /* 0x245B0 - MAC exact match address 14, part 1 */
 508         uint    mac14addr2;     /* 0x245B4 - MAC exact match address 14, part 2 */
 509         uint    mac15addr1;     /* 0x245B8 - MAC exact match address 15, part 1 */
 510         uint    mac15addr2;     /* 0x245BC - MAC exact match address 15, part 2 */
 511         char    res48[192];
 512         uint    tr64;           /* 0x24680 - Transmit and Receive 64-byte Frame Counter */
 513         uint    tr127;          /* 0x24684 - Transmit and Receive 65-127 byte Frame Counter */
 514         uint    tr255;          /* 0x24688 - Transmit and Receive 128-255 byte Frame Counter */
 515         uint    tr511;          /* 0x2468c - Transmit and Receive 256-511 byte Frame Counter */
 516         uint    tr1k;           /* 0x24690 - Transmit and Receive 512-1023 byte Frame Counter */
 517         uint    trmax;          /* 0x24694 - Transmit and Receive 1024-1518 byte Frame Counter */
 518         uint    trmgv;          /* 0x24698 - Transmit and Receive 1519-1522 byte Good VLAN Frame */
 519         uint    rbyt;           /* 0x2469c - Receive Byte Counter */
 520         uint    rpkt;           /* 0x246a0 - Receive Packet Counter */
 521         uint    rfcs;           /* 0x246a4 - Receive FCS Error Counter */
 522         uint    rmca;           /* 0x246a8 - Receive Multicast Packet Counter */
 523         uint    rbca;           /* 0x246ac - Receive Broadcast Packet Counter */
 524         uint    rxcf;           /* 0x246b0 - Receive Control Frame Packet Counter */
 525         uint    rxpf;           /* 0x246b4 - Receive Pause Frame Packet Counter */
 526         uint    rxuo;           /* 0x246b8 - Receive Unknown OP Code Counter */
 527         uint    raln;           /* 0x246bc - Receive Alignment Error Counter */
 528         uint    rflr;           /* 0x246c0 - Receive Frame Length Error Counter */
 529         uint    rcde;           /* 0x246c4 - Receive Code Error Counter */
 530         uint    rcse;           /* 0x246c8 - Receive Carrier Sense Error Counter */
 531         uint    rund;           /* 0x246cc - Receive Undersize Packet Counter */
 532         uint    rovr;           /* 0x246d0 - Receive Oversize Packet Counter */
 533         uint    rfrg;           /* 0x246d4 - Receive Fragments Counter */
 534         uint    rjbr;           /* 0x246d8 - Receive Jabber Counter */
 535         uint    rdrp;           /* 0x246dc - Receive Drop Counter */
 536         uint    tbyt;           /* 0x246e0 - Transmit Byte Counter Counter */
 537         uint    tpkt;           /* 0x246e4 - Transmit Packet Counter */
 538         uint    tmca;           /* 0x246e8 - Transmit Multicast Packet Counter */
 539         uint    tbca;           /* 0x246ec - Transmit Broadcast Packet Counter */
 540         uint    txpf;           /* 0x246f0 - Transmit Pause Control Frame Counter */
 541         uint    tdfr;           /* 0x246f4 - Transmit Deferral Packet Counter */
 542         uint    tedf;           /* 0x246f8 - Transmit Excessive Deferral Packet Counter */
 543         uint    tscl;           /* 0x246fc - Transmit Single Collision Packet Counter */
 544         uint    tmcl;           /* 0x24700 - Transmit Multiple Collision Packet Counter */
 545         uint    tlcl;           /* 0x24704 - Transmit Late Collision Packet Counter */
 546         uint    txcl;           /* 0x24708 - Transmit Excessive Collision Packet Counter */
 547         uint    tncl;           /* 0x2470c - Transmit Total Collision Counter */
 548         char    res49[4];
 549         uint    tdrp;           /* 0x24714 - Transmit Drop Frame Counter */
 550         uint    tjbr;           /* 0x24718 - Transmit Jabber Frame Counter */
 551         uint    tfcs;           /* 0x2471c - Transmit FCS Error Counter */
 552         uint    txcf;           /* 0x24720 - Transmit Control Frame Counter */
 553         uint    tovr;           /* 0x24724 - Transmit Oversize Frame Counter */
 554         uint    tund;           /* 0x24728 - Transmit Undersize Frame Counter */
 555         uint    tfrg;           /* 0x2472c - Transmit Fragments Frame Counter */
 556         uint    car1;           /* 0x24730 - Carry Register One */
 557         uint    car2;           /* 0x24734 - Carry Register Two */
 558         uint    cam1;           /* 0x24738 - Carry Mask Register One */
 559         uint    cam2;           /* 0x2473c - Carry Mask Register Two */
 560         uint    rrej;           /* 0x24740 - Receive filer rejected packet counter */
 561         char    res50[188];
 562         uint    iaddr0;         /* 0x24800 - Indivdual address register 0 */
 563         uint    iaddr1;         /* 0x24804 - Indivdual address register 1 */
 564         uint    iaddr2;         /* 0x24808 - Indivdual address register 2 */
 565         uint    iaddr3;         /* 0x2480c - Indivdual address register 3 */
 566         uint    iaddr4;         /* 0x24810 - Indivdual address register 4 */
 567         uint    iaddr5;         /* 0x24814 - Indivdual address register 5 */
 568         uint    iaddr6;         /* 0x24818 - Indivdual address register 6 */
 569         uint    iaddr7;         /* 0x2481c - Indivdual address register 7 */
 570         char    res51[96];
 571         uint    gaddr0;         /* 0x24880 - Global address register 0 */
 572         uint    gaddr1;         /* 0x24884 - Global address register 1 */
 573         uint    gaddr2;         /* 0x24888 - Global address register 2 */
 574         uint    gaddr3;         /* 0x2488c - Global address register 3 */
 575         uint    gaddr4;         /* 0x24890 - Global address register 4 */
 576         uint    gaddr5;         /* 0x24894 - Global address register 5 */
 577         uint    gaddr6;         /* 0x24898 - Global address register 6 */
 578         uint    gaddr7;         /* 0x2489c - Global address register 7 */
 579         char    res52[352];
 580         uint    fifocfg;        /* 0x24A00 - FIFO interface configuration register */
 581         char    res53[500];
 582         uint    attr;           /* 0x24BF8 - DMA Attribute register */
 583         uint    attreli;        /* 0x24BFC - DMA Attribute extract length and index register */
 584         char    res54[1024];
 585 } ccsr_tsec_t;
 586
 587 /* PIC Registers(0x4_0000-0x6_1000) */
 588
 589 typedef struct ccsr_pic {
 590         char    res1[64];
 591         uint    ipidr0;         /* 0x40040 - Interprocessor Interrupt Dispatch Register 0 */
 592         char    res2[12];
 593         uint    ipidr1;         /* 0x40050 - Interprocessor Interrupt Dispatch Register 1 */
 594         char    res3[12];
 595         uint    ipidr2;         /* 0x40060 - Interprocessor Interrupt Dispatch Register 2 */
 596         char    res4[12];
 597         uint    ipidr3;         /* 0x40070 - Interprocessor Interrupt Dispatch Register 3 */
 598         char    res5[12];
 599         uint    ctpr;           /* 0x40080 - Current Task Priority Register */
 600         char    res6[12];
 601         uint    whoami;         /* 0x40090 - Who Am I Register */
 602         char    res7[12];
 603         uint    iack;           /* 0x400a0 - Interrupt Acknowledge Register */
 604         char    res8[12];
 605         uint    eoi;            /* 0x400b0 - End Of Interrupt Register */
 606         char    res9[3916];
 607         uint    frr;            /* 0x41000 - Feature Reporting Register */
 608         char    res10[28];
 609         uint    gcr;            /* 0x41020 - Global Configuration Register */
 610 #define MPC86xx_PICGCR_RST      0x80000000
 611 #define MPC86xx_PICGCR_MODE     0x20000000
 612         char    res11[92];
 613         uint    vir;            /* 0x41080 - Vendor Identification Register */
 614         char    res12[12];
 615         uint    pir;            /* 0x41090 - Processor Initialization Register */
 616         char    res13[12];
 617         uint    ipivpr0;        /* 0x410a0 - IPI Vector/Priority Register 0 */
 618         char    res14[12];
 619         uint    ipivpr1;        /* 0x410b0 - IPI Vector/Priority Register 1 */
 620         char    res15[12];
 621         uint    ipivpr2;        /* 0x410c0 - IPI Vector/Priority Register 2 */
 622         char    res16[12];
 623         uint    ipivpr3;        /* 0x410d0 - IPI Vector/Priority Register 3 */
 624         char    res17[12];
 625         uint    svr;            /* 0x410e0 - Spurious Vector Register */
 626         char    res18[12];
 627         uint    tfrr;           /* 0x410f0 - Timer Frequency Reporting Register */
 628         char    res19[12];
 629         uint    gtccr0;         /* 0x41100 - Global Timer Current Count Register 0 */
 630         char    res20[12];
 631         uint    gtbcr0;         /* 0x41110 - Global Timer Base Count Register 0 */
 632         char    res21[12];
 633         uint    gtvpr0;         /* 0x41120 - Global Timer Vector/Priority Register 0 */
 634         char    res22[12];
 635         uint    gtdr0;          /* 0x41130 - Global Timer Destination Register 0 */
 636         char    res23[12];
 637         uint    gtccr1;         /* 0x41140 - Global Timer Current Count Register 1 */
 638         char    res24[12];
 639         uint    gtbcr1;         /* 0x41150 - Global Timer Base Count Register 1 */
 640         char    res25[12];
 641         uint    gtvpr1;         /* 0x41160 - Global Timer Vector/Priority Register 1 */
 642         char    res26[12];
 643         uint    gtdr1;          /* 0x41170 - Global Timer Destination Register 1 */
 644         char    res27[12];
 645         uint    gtccr2;         /* 0x41180 - Global Timer Current Count Register 2 */
 646         char    res28[12];
 647         uint    gtbcr2;         /* 0x41190 - Global Timer Base Count Register 2 */
 648         char    res29[12];
 649         uint    gtvpr2;         /* 0x411a0 - Global Timer Vector/Priority Register 2 */
 650         char    res30[12];
 651         uint    gtdr2;          /* 0x411b0 - Global Timer Destination Register 2 */
 652         char    res31[12];
 653         uint    gtccr3;         /* 0x411c0 - Global Timer Current Count Register 3 */
 654         char    res32[12];
 655         uint    gtbcr3;         /* 0x411d0 - Global Timer Base Count Register 3 */
 656         char    res33[12];
 657         uint    gtvpr3;         /* 0x411e0 - Global Timer Vector/Priority Register 3 */
 658         char    res34[12];
 659         uint    gtdr3;          /* 0x411f0 - Global Timer Destination Register 3 */
 660         char    res35[268];
 661         uint    tcr;            /* 0x41300 - Timer Control Register */
 662         char    res36[12];
 663         uint    irqsr0;         /* 0x41310 - IRQ_OUT Summary Register 0 */
 664         char    res37[12];
 665         uint    irqsr1;         /* 0x41320 - IRQ_OUT Summary Register 1 */
 666         char    res38[12];
 667         uint    cisr0;          /* 0x41330 - Critical Interrupt Summary Register 0 */
 668         char    res39[12];
 669         uint    cisr1;          /* 0x41340 - Critical Interrupt Summary Register 1 */
 670         char    res40[12];
 671         uint    pm0mr0;         /* 0x41350 - Performance monitor 0 mask register 0  */
 672         char    res41[12];
 673         uint    pm0mr1;         /* 0x41360 - Performance monitor 0 mask register 1  */
 674         char    res42[12];
 675         uint    pm1mr0;         /* 0x41370 - Performance monitor 1 mask register 0  */
 676         char    res43[12];
 677         uint    pm1mr1;         /* 0x41380 - Performance monitor 1 mask register 1  */
 678         char    res44[12];
 679         uint    pm2mr0;         /* 0x41390 - Performance monitor 2 mask register 0  */
 680         char    res45[12];
 681         uint    pm2mr1;         /* 0x413A0 - Performance monitor 2 mask register 1  */
 682         char    res46[12];
 683         uint    pm3mr0;         /* 0x413B0 - Performance monitor 3 mask register 0  */
 684         char    res47[12];
 685         uint    pm3mr1;         /* 0x413C0 - Performance monitor 3 mask register 1  */
 686         char    res48[60];
 687         uint    msgr0;          /* 0x41400 - Message Register 0 */
 688         char    res49[12];
 689         uint    msgr1;          /* 0x41410 - Message Register 1 */
 690         char    res50[12];
 691         uint    msgr2;          /* 0x41420 - Message Register 2 */
 692         char    res51[12];
 693         uint    msgr3;          /* 0x41430 - Message Register 3 */
 694         char    res52[204];
 695         uint    mer;            /* 0x41500 - Message Enable Register */
 696         char    res53[12];
 697         uint    msr;            /* 0x41510 - Message Status Register */
 698         char    res54[60140];
 699         uint    eivpr0;         /* 0x50000 - External Interrupt Vector/Priority Register 0 */
 700         char    res55[12];
 701         uint    eidr0;          /* 0x50010 - External Interrupt Destination Register 0 */
 702         char    res56[12];
 703         uint    eivpr1;         /* 0x50020 - External Interrupt Vector/Priority Register 1 */
 704         char    res57[12];
 705         uint    eidr1;          /* 0x50030 - External Interrupt Destination Register 1 */
 706         char    res58[12];
 707         uint    eivpr2;         /* 0x50040 - External Interrupt Vector/Priority Register 2 */
 708         char    res59[12];
 709         uint    eidr2;          /* 0x50050 - External Interrupt Destination Register 2 */
 710         char    res60[12];
 711         uint    eivpr3;         /* 0x50060 - External Interrupt Vector/Priority Register 3 */
 712         char    res61[12];
 713         uint    eidr3;          /* 0x50070 - External Interrupt Destination Register 3 */
 714         char    res62[12];
 715         uint    eivpr4;         /* 0x50080 - External Interrupt Vector/Priority Register 4 */
 716         char    res63[12];
 717         uint    eidr4;          /* 0x50090 - External Interrupt Destination Register 4 */
 718         char    res64[12];
 719         uint    eivpr5;         /* 0x500a0 - External Interrupt Vector/Priority Register 5 */
 720         char    res65[12];
 721         uint    eidr5;          /* 0x500b0 - External Interrupt Destination Register 5 */
 722         char    res66[12];
 723         uint    eivpr6;         /* 0x500c0 - External Interrupt Vector/Priority Register 6 */
 724         char    res67[12];
 725         uint    eidr6;          /* 0x500d0 - External Interrupt Destination Register 6 */
 726         char    res68[12];
 727         uint    eivpr7;         /* 0x500e0 - External Interrupt Vector/Priority Register 7 */
 728         char    res69[12];
 729         uint    eidr7;          /* 0x500f0 - External Interrupt Destination Register 7 */
 730         char    res70[12];
 731         uint    eivpr8;         /* 0x50100 - External Interrupt Vector/Priority Register 8 */
 732         char    res71[12];
 733         uint    eidr8;          /* 0x50110 - External Interrupt Destination Register 8 */
 734         char    res72[12];
 735         uint    eivpr9;         /* 0x50120 - External Interrupt Vector/Priority Register 9 */
 736         char    res73[12];
 737         uint    eidr9;          /* 0x50130 - External Interrupt Destination Register 9 */
 738         char    res74[12];
 739         uint    eivpr10;        /* 0x50140 - External Interrupt Vector/Priority Register 10 */
 740         char    res75[12];
 741         uint    eidr10;         /* 0x50150 - External Interrupt Destination Register 10 */
 742         char    res76[12];
 743         uint    eivpr11;        /* 0x50160 - External Interrupt Vector/Priority Register 11 */
 744         char    res77[12];
 745         uint    eidr11;         /* 0x50170 - External Interrupt Destination Register 11 */
 746         char    res78[140];
 747         uint    iivpr0;         /* 0x50200 - Internal Interrupt Vector/Priority Register 0 */
 748         char    res79[12];
 749         uint    iidr0;          /* 0x50210 - Internal Interrupt Destination Register 0 */
 750         char    res80[12];
 751         uint    iivpr1;         /* 0x50220 - Internal Interrupt Vector/Priority Register 1 */
 752         char    res81[12];
 753         uint    iidr1;          /* 0x50230 - Internal Interrupt Destination Register 1 */
 754         char    res82[12];
 755         uint    iivpr2;         /* 0x50240 - Internal Interrupt Vector/Priority Register 2 */
 756         char    res83[12];
 757         uint    iidr2;          /* 0x50250 - Internal Interrupt Destination Register 2 */
 758         char    res84[12];
 759         uint    iivpr3;         /* 0x50260 - Internal Interrupt Vector/Priority Register 3 */
 760         char    res85[12];
 761         uint    iidr3;          /* 0x50270 - Internal Interrupt Destination Register 3 */
 762         char    res86[12];
 763         uint    iivpr4;         /* 0x50280 - Internal Interrupt Vector/Priority Register 4 */
 764         char    res87[12];
 765         uint    iidr4;          /* 0x50290 - Internal Interrupt Destination Register 4 */
 766         char    res88[12];
 767         uint    iivpr5;         /* 0x502a0 - Internal Interrupt Vector/Priority Register 5 */
 768         char    res89[12];
 769         uint    iidr5;          /* 0x502b0 - Internal Interrupt Destination Register 5 */
 770         char    res90[12];
 771         uint    iivpr6;         /* 0x502c0 - Internal Interrupt Vector/Priority Register 6 */
 772         char    res91[12];
 773         uint    iidr6;          /* 0x502d0 - Internal Interrupt Destination Register 6 */
 774         char    res92[12];
 775         uint    iivpr7;         /* 0x502e0 - Internal Interrupt Vector/Priority Register 7 */
 776         char    res93[12];
 777         uint    iidr7;          /* 0x502f0 - Internal Interrupt Destination Register 7 */
 778         char    res94[12];
 779         uint    iivpr8;         /* 0x50300 - Internal Interrupt Vector/Priority Register 8 */
 780         char    res95[12];
 781         uint    iidr8;          /* 0x50310 - Internal Interrupt Destination Register 8 */
 782         char    res96[12];
 783         uint    iivpr9;         /* 0x50320 - Internal Interrupt Vector/Priority Register 9 */
 784         char    res97[12];
 785         uint    iidr9;          /* 0x50330 - Internal Interrupt Destination Register 9 */
 786         char    res98[12];
 787         uint    iivpr10;        /* 0x50340 - Internal Interrupt Vector/Priority Register 10 */
 788         char    res99[12];
 789         uint    iidr10;         /* 0x50350 - Internal Interrupt Destination Register 10 */
 790         char    res100[12];
 791         uint    iivpr11;        /* 0x50360 - Internal Interrupt Vector/Priority Register 11 */
 792         char    res101[12];
 793         uint    iidr11;         /* 0x50370 - Internal Interrupt Destination Register 11 */
 794         char    res102[12];
 795         uint    iivpr12;        /* 0x50380 - Internal Interrupt Vector/Priority Register 12 */
 796         char    res103[12];
 797         uint    iidr12;         /* 0x50390 - Internal Interrupt Destination Register 12 */
 798         char    res104[12];
 799         uint    iivpr13;        /* 0x503a0 - Internal Interrupt Vector/Priority Register 13 */
 800         char    res105[12];
 801         uint    iidr13;         /* 0x503b0 - Internal Interrupt Destination Register 13 */
 802         char    res106[12];
 803         uint    iivpr14;        /* 0x503c0 - Internal Interrupt Vector/Priority Register 14 */
 804         char    res107[12];
 805         uint    iidr14;         /* 0x503d0 - Internal Interrupt Destination Register 14 */
 806         char    res108[12];
 807         uint    iivpr15;        /* 0x503e0 - Internal Interrupt Vector/Priority Register 15 */
 808         char    res109[12];
 809         uint    iidr15;         /* 0x503f0 - Internal Interrupt Destination Register 15 */
 810         char    res110[12];
 811         uint    iivpr16;        /* 0x50400 - Internal Interrupt Vector/Priority Register 16 */
 812         char    res111[12];
 813         uint    iidr16;         /* 0x50410 - Internal Interrupt Destination Register 16 */
 814         char    res112[12];
 815         uint    iivpr17;        /* 0x50420 - Internal Interrupt Vector/Priority Register 17 */
 816         char    res113[12];
 817         uint    iidr17;         /* 0x50430 - Internal Interrupt Destination Register 17 */
 818         char    res114[12];
 819         uint    iivpr18;        /* 0x50440 - Internal Interrupt Vector/Priority Register 18 */
 820         char    res115[12];
 821         uint    iidr18;         /* 0x50450 - Internal Interrupt Destination Register 18 */
 822         char    res116[12];
 823         uint    iivpr19;        /* 0x50460 - Internal Interrupt Vector/Priority Register 19 */
 824         char    res117[12];
 825         uint    iidr19;         /* 0x50470 - Internal Interrupt Destination Register 19 */
 826         char    res118[12];
 827         uint    iivpr20;        /* 0x50480 - Internal Interrupt Vector/Priority Register 20 */
 828         char    res119[12];
 829         uint    iidr20;         /* 0x50490 - Internal Interrupt Destination Register 20 */
 830         char    res120[12];
 831         uint    iivpr21;        /* 0x504a0 - Internal Interrupt Vector/Priority Register 21 */
 832         char    res121[12];
 833         uint    iidr21;         /* 0x504b0 - Internal Interrupt Destination Register 21 */
 834         char    res122[12];
 835         uint    iivpr22;        /* 0x504c0 - Internal Interrupt Vector/Priority Register 22 */
 836         char    res123[12];
 837         uint    iidr22;         /* 0x504d0 - Internal Interrupt Destination Register 22 */
 838         char    res124[12];
 839         uint    iivpr23;        /* 0x504e0 - Internal Interrupt Vector/Priority Register 23 */
 840         char    res125[12];
 841         uint    iidr23;         /* 0x504f0 - Internal Interrupt Destination Register 23 */
 842         char    res126[12];
 843         uint    iivpr24;        /* 0x50500 - Internal Interrupt Vector/Priority Register 24 */
 844         char    res127[12];
 845         uint    iidr24;         /* 0x50510 - Internal Interrupt Destination Register 24 */
 846         char    res128[12];
 847         uint    iivpr25;        /* 0x50520 - Internal Interrupt Vector/Priority Register 25 */
 848         char    res129[12];
 849         uint    iidr25;         /* 0x50530 - Internal Interrupt Destination Register 25 */
 850         char    res130[12];
 851         uint    iivpr26;        /* 0x50540 - Internal Interrupt Vector/Priority Register 26 */
 852         char    res131[12];
 853         uint    iidr26;         /* 0x50550 - Internal Interrupt Destination Register 26 */
 854         char    res132[12];
 855         uint    iivpr27;        /* 0x50560 - Internal Interrupt Vector/Priority Register 27 */
 856         char    res133[12];
 857         uint    iidr27;         /* 0x50570 - Internal Interrupt Destination Register 27 */
 858         char    res134[12];
 859         uint    iivpr28;        /* 0x50580 - Internal Interrupt Vector/Priority Register 28 */
 860         char    res135[12];
 861         uint    iidr28;         /* 0x50590 - Internal Interrupt Destination Register 28 */
 862         char    res136[12];
 863         uint    iivpr29;        /* 0x505a0 - Internal Interrupt Vector/Priority Register 29 */
 864         char    res137[12];
 865         uint    iidr29;         /* 0x505b0 - Internal Interrupt Destination Register 29 */
 866         char    res138[12];
 867         uint    iivpr30;        /* 0x505c0 - Internal Interrupt Vector/Priority Register 30 */
 868         char    res139[12];
 869         uint    iidr30;         /* 0x505d0 - Internal Interrupt Destination Register 30 */
 870         char    res140[12];
 871         uint    iivpr31;        /* 0x505e0 - Internal Interrupt Vector/Priority Register 31 */
 872         char    res141[12];
 873         uint    iidr31;         /* 0x505f0 - Internal Interrupt Destination Register 31 */
 874         char    res142[4108];
 875         uint    mivpr0;         /* 0x51600 - Messaging Interrupt Vector/Priority Register 0 */
 876         char    res143[12];
 877         uint    midr0;          /* 0x51610 - Messaging Interrupt Destination Register 0 */
 878         char    res144[12];
 879         uint    mivpr1;         /* 0x51620 - Messaging Interrupt Vector/Priority Register 1 */
 880         char    res145[12];
 881         uint    midr1;          /* 0x51630 - Messaging Interrupt Destination Register 1 */
 882         char    res146[12];
 883         uint    mivpr2;         /* 0x51640 - Messaging Interrupt Vector/Priority Register 2 */
 884         char    res147[12];
 885         uint    midr2;          /* 0x51650 - Messaging Interrupt Destination Register 2 */
 886         char    res148[12];
 887         uint    mivpr3;         /* 0x51660 - Messaging Interrupt Vector/Priority Register 3 */
 888         char    res149[12];
 889         uint    midr3;          /* 0x51670 - Messaging Interrupt Destination Register 3 */
 890         char    res150[59852];
 891         uint    ipi0dr0;        /* 0x60040 - Processor 0 Interprocessor Interrupt Dispatch Register 0 */
 892         char    res151[12];
 893         uint    ipi0dr1;        /* 0x60050 - Processor 0 Interprocessor Interrupt Dispatch Register 1 */
 894         char    res152[12];
 895         uint    ipi0dr2;        /* 0x60060 - Processor 0 Interprocessor Interrupt Dispatch Register 2 */
 896         char    res153[12];
 897         uint    ipi0dr3;        /* 0x60070 - Processor 0 Interprocessor Interrupt Dispatch Register 3 */
 898         char    res154[12];
 899         uint    ctpr0;          /* 0x60080 - Current Task Priority Register for Processor 0 */
 900         char    res155[12];
 901         uint    whoami0;        /* 0x60090 - Who Am I Register for Processor 0 */
 902         char    res156[12];
 903         uint    iack0;          /* 0x600a0 - Interrupt Acknowledge Register for Processor 0 */
 904         char    res157[12];
 905         uint    eoi0;           /* 0x600b0 - End Of Interrupt Register for Processor 0 */
 906         char    res158[3916];
 907 } ccsr_pic_t;
 908
 909 /* RapidIO Registers(0xc_0000-0xe_0000) */
 910
 911 typedef struct ccsr_rio {
 912         uint    didcar;         /* 0xc0000 - Device Identity Capability Register */
 913         uint    dicar;          /* 0xc0004 - Device Information Capability Register */
 914         uint    aidcar;         /* 0xc0008 - Assembly Identity Capability Register */
 915         uint    aicar;          /* 0xc000c - Assembly Information Capability Register */
 916         uint    pefcar;         /* 0xc0010 - Processing Element Features Capability Register */
 917         uint    spicar;         /* 0xc0014 - Switch Port Information Capability Register */
 918         uint    socar;          /* 0xc0018 - Source Operations Capability Register */
 919         uint    docar;          /* 0xc001c - Destination Operations Capability Register */
 920         char    res1[32];
 921         uint    msr;            /* 0xc0040 - Mailbox Command And Status Register */
 922         uint    pwdcsr;         /* 0xc0044 - Port-Write and Doorbell Command And Status Register */
 923         char    res2[4];
 924         uint    pellccsr;       /* 0xc004c - Processing Element Logic Layer Control Command and Status Register */
 925         char    res3[12];
 926         uint    lcsbacsr;       /* 0xc005c - Local Configuration Space Base Address Command and Status Register */
 927         uint    bdidcsr;        /* 0xc0060 - Base Device ID Command and Status Register */
 928         char    res4[4];
 929         uint    hbdidlcsr;      /* 0xc0068 - Host Base Device ID Lock Command and Status Register */
 930         uint    ctcsr;          /* 0xc006c - Component Tag Command and Status Register */
 931         char    res5[144];
 932         uint    pmbh0csr;       /* 0xc0100 - 8/16 LP-LVDS Port Maintenance Block Header 0 Command and Status Register */
 933         char    res6[28];
 934         uint    pltoccsr;       /* 0xc0120 - Port Link Time-out Control Command and Status Register */
 935         uint    prtoccsr;       /* 0xc0124 - Port Response Time-out Control Command and Status Register */
 936         char    res7[20];
 937         uint    pgccsr;         /* 0xc013c - Port General Command and Status Register */
 938         uint    plmreqcsr;      /* 0xc0140 - Port Link Maintenance Request Command and Status Register */
 939         uint    plmrespcsr;     /* 0xc0144 - Port Link Maintenance Response Command and Status Register */
 940         uint    plascsr;        /* 0xc0148 - Port Local Ackid Status Command and Status Register */
 941         char    res8[12];
 942         uint    pescsr;         /* 0xc0158 - Port Error and Status Command and Status Register */
 943         uint    pccsr;          /* 0xc015c - Port Control Command and Status Register */
 944         char    res9[1184];
 945         uint    erbh;           /* 0xc0600 - Error Reporting Block Header Register */
 946         char    res10[4];
 947         uint    ltledcsr;       /* 0xc0608 - Logical/Transport layer error detect status register */
 948         uint    ltleecsr;       /* 0xc060c - Logical/Transport layer error enable register */
 949         char    res11[4];
 950         uint    ltlaccsr;       /* 0xc0614 - Logical/Transport layer addresss capture register */
 951         uint    ltldidccsr;     /* 0xc0618 - Logical/Transport layer device ID capture register */
 952         uint    ltlcccsr;       /* 0xc061c - Logical/Transport layer control capture register */
 953         char    res12[32];
 954         uint    edcsr;          /* 0xc0640 - Port 0 error detect status register */
 955         uint    erecsr;         /* 0xc0644 - Port 0 error rate enable status register */
 956         uint    ecacsr;         /* 0xc0648 - Port 0 error capture attributes register */
 957         uint    pcseccsr0;      /* 0xc064c - Port 0 packet/control symbol error capture register 0 */
 958         uint    peccsr1;        /* 0xc0650 - Port 0 error capture command and status register 1 */
 959         uint    peccsr2;        /* 0xc0654 - Port 0 error capture command and status register 2 */
 960         uint    peccsr3;        /* 0xc0658 - Port 0 error capture command and status register 3 */
 961         char    res13[12];
 962         uint    ercsr;          /* 0xc0668 - Port 0 error rate command and status register */
 963         uint    ertcsr;         /* 0xc066C - Port 0 error rate threshold status register*/
 964         char    res14[63892];
 965         uint    llcr;           /* 0xd0004 - Logical Layer Configuration Register */
 966         char    res15[12];
 967         uint    epwisr;         /* 0xd0010 - Error / Port-Write Interrupt Status Register */
 968         char    res16[12];
 969         uint    lretcr;         /* 0xd0020 - Logical Retry Error Threshold Configuration Register */
 970         char    res17[92];
 971         uint    pretcr;         /* 0xd0080 - Physical Retry Erorr Threshold Configuration Register */
 972         char    res18[124];
 973         uint    adidcsr;        /* 0xd0100 - Port 0 Alt. Device ID Command and Status Register */
 974         char    res19[28];
 975         uint    ptaacr;         /* 0xd0120 - Port 0 Pass-Through/Accept-All Configuration Register */
 976         char    res20[12];
 977         uint    iecsr;          /* 0xd0130 - Port 0 Implementation Error Status Register */
 978         char    res21[12];
 979         uint    pcr;            /* 0xd0140 - Port 0 Phsyical Configuration RegisterRegister */
 980         char    res22[20];
 981         uint    slcsr;          /* 0xd0158 - Port 0 Serial Link Command and Status Register */
 982         char    res23[4];
 983         uint    sleir;          /* 0xd0160 - Port 0 Serial Link Error Injection Register */
 984         char    res24[2716];
 985         uint    rowtar0;        /* 0xd0c00 - RapidIO Outbound Window Translation Address Register 0 */
 986         uint    rowtear0;       /* 0xd0c04 - RapidIO Outbound Window Translation Ext. Address Register 0 */
 987         char    res25[8];
 988         uint    rowar0;         /* 0xd0c10 - RapidIO Outbound Attributes Register 0 */
 989         char    res26[12];
 990         uint    rowtar1;        /* 0xd0c20 - RapidIO Outbound Window Translation Address Register 1 */
 991         uint    rowtear1;       /* 0xd0c24 - RapidIO Outbound Window Translation Ext. Address Register 1 */
 992         uint    rowbar1;        /* 0xd0c28 - RapidIO Outbound Window Base Address Register 1 */
 993         char    res27[4];
 994         uint    rowar1;         /* 0xd0c30 - RapidIO Outbound Attributes Register 1 */
 995         uint    rows1r1;        /* 0xd0c34 - RapidIO Outbound Window Segment 1 Register 1 */
 996         uint    rows2r1;        /* 0xd0c38 - RapidIO Outbound Window Segment 2 Register 1 */
 997         uint    rows3r1;        /* 0xd0c3c - RapidIO Outbound Window Segment 3 Register 1 */
 998         uint    rowtar2;        /* 0xd0c40 - RapidIO Outbound Window Translation Address Register 2 */
 999         uint    rowtear2;       /* 0xd0c44 - RapidIO Outbound Window Translation Ext. Address Register 2 */
1000         uint    rowbar2;        /* 0xd0c48 - RapidIO Outbound Window Base Address Register 2 */
1001         char    res28[4];
1002         uint    rowar2;         /* 0xd0c50 - RapidIO Outbound Attributes Register 2 */
1003         uint    rows1r2;        /* 0xd0c54 - RapidIO Outbound Window Segment 1 Register 2 */
1004         uint    rows2r2;        /* 0xd0c58 - RapidIO Outbound Window Segment 2 Register 2 */
1005         uint    rows3r2;        /* 0xd0c5c - RapidIO Outbound Window Segment 3 Register 2 */
1006         uint    rowtar3;        /* 0xd0c60 - RapidIO Outbound Window Translation Address Register 3 */
1007         uint    rowtear3;       /* 0xd0c64 - RapidIO Outbound Window Translation Ext. Address Register 3 */
1008         uint    rowbar3;        /* 0xd0c68 - RapidIO Outbound Window Base Address Register 3 */
1009         char    res29[4];
1010         uint    rowar3;         /* 0xd0c70 - RapidIO Outbound Attributes Register 3 */
1011         uint    rows1r3;        /* 0xd0c74 - RapidIO Outbound Window Segment 1 Register 3 */
1012         uint    rows2r3;        /* 0xd0c78 - RapidIO Outbound Window Segment 2 Register 3 */
1013         uint    rows3r3;        /* 0xd0c7c - RapidIO Outbound Window Segment 3 Register 3 */
1014         uint    rowtar4;        /* 0xd0c80 - RapidIO Outbound Window Translation Address Register 4 */
1015         uint    rowtear4;       /* 0xd0c84 - RapidIO Outbound Window Translation Ext. Address Register 4 */
1016         uint    rowbar4;        /* 0xd0c88 - RapidIO Outbound Window Base Address Register 4 */
1017         char    res30[4];
1018         uint    rowar4;         /* 0xd0c90 - RapidIO Outbound Attributes Register 4 */
1019         uint    rows1r4;        /* 0xd0c94 - RapidIO Outbound Window Segment 1 Register 4 */
1020         uint    rows2r4;        /* 0xd0c98 - RapidIO Outbound Window Segment 2 Register 4 */
1021         uint    rows3r4;        /* 0xd0c9c - RapidIO Outbound Window Segment 3 Register 4 */
1022         uint    rowtar5;        /* 0xd0ca0 - RapidIO Outbound Window Translation Address Register 5 */
1023         uint    rowtear5;       /* 0xd0ca4 - RapidIO Outbound Window Translation Ext. Address Register 5 */
1024         uint    rowbar5;        /* 0xd0ca8 - RapidIO Outbound Window Base Address Register 5 */
1025         char    res31[4];
1026         uint    rowar5;         /* 0xd0cb0 - RapidIO Outbound Attributes Register 5 */
1027         uint    rows1r5;        /* 0xd0cb4 - RapidIO Outbound Window Segment 1 Register 5 */
1028         uint    rows2r5;        /* 0xd0cb8 - RapidIO Outbound Window Segment 2 Register 5 */
1029         uint    rows3r5;        /* 0xd0cbc - RapidIO Outbound Window Segment 3 Register 5 */
1030         uint    rowtar6;        /* 0xd0cc0 - RapidIO Outbound Window Translation Address Register 6 */
1031         uint    rowtear6;       /* 0xd0cc4 - RapidIO Outbound Window Translation Ext. Address Register 6 */
1032         uint    rowbar6;        /* 0xd0cc8 - RapidIO Outbound Window Base Address Register 6 */
1033         char    res32[4];
1034         uint    rowar6;         /* 0xd0cd0 - RapidIO Outbound Attributes Register 6 */
1035         uint    rows1r6;        /* 0xd0cd4 - RapidIO Outbound Window Segment 1 Register 6 */
1036         uint    rows2r6;        /* 0xd0cd8 - RapidIO Outbound Window Segment 2 Register 6 */
1037         uint    rows3r6;        /* 0xd0cdc - RapidIO Outbound Window Segment 3 Register 6 */
1038         uint    rowtar7;        /* 0xd0ce0 - RapidIO Outbound Window Translation Address Register 7 */
1039         uint    rowtear7;       /* 0xd0ce4 - RapidIO Outbound Window Translation Ext. Address Register 7 */
1040         uint    rowbar7;        /* 0xd0ce8 - RapidIO Outbound Window Base Address Register 7 */
1041         char    res33[4];
1042         uint    rowar7;         /* 0xd0cf0 - RapidIO Outbound Attributes Register 7 */
1043         uint    rows1r7;        /* 0xd0cf4 - RapidIO Outbound Window Segment 1 Register 7 */
1044         uint    rows2r7;        /* 0xd0cf8 - RapidIO Outbound Window Segment 2 Register 7 */
1045         uint    rows3r7;        /* 0xd0cfc - RapidIO Outbound Window Segment 3 Register 7 */
1046         uint    rowtar8;        /* 0xd0d00 - RapidIO Outbound Window Translation Address Register 8 */
1047         uint    rowtear8;       /* 0xd0d04 - RapidIO Outbound Window Translation Ext. Address Register 8 */
1048         uint    rowbar8;        /* 0xd0d08 - RapidIO Outbound Window Base Address Register 8 */
1049         char    res34[4];
1050         uint    rowar8;         /* 0xd0d10 - RapidIO Outbound Attributes Register 8 */
1051         uint    rows1r8;        /* 0xd0d14 - RapidIO Outbound Window Segment 1 Register 8 */
1052         uint    rows2r8;        /* 0xd0d18 - RapidIO Outbound Window Segment 2 Register 8 */
1053         uint    rows3r8;        /* 0xd0d1c - RapidIO Outbound Window Segment 3 Register 8 */
1054         char    res35[64];
1055         uint    riwtar4;        /* 0xd0d60 - RapidIO Inbound Window Translation Address Register 4 */
1056         uint    riwbar4;        /* 0xd0d68 - RapidIO Inbound Window Base Address Register 4 */
1057         char    res36[4];
1058         uint    riwar4;         /* 0xd0d70 - RapidIO Inbound Attributes Register 4 */
1059         char    res37[12];
1060         uint    riwtar3;        /* 0xd0d80 - RapidIO Inbound Window Translation Address Register 3 */
1061         char    res38[4];
1062         uint    riwbar3;        /* 0xd0d88 - RapidIO Inbound Window Base Address Register 3 */
1063         char    res39[4];
1064         uint    riwar3;         /* 0xd0d90 - RapidIO Inbound Attributes Register 3 */
1065         char    res40[12];
1066         uint    riwtar2;        /* 0xd0da0 - RapidIO Inbound Window Translation Address Register 2 */
1067         char    res41[4];
1068         uint    riwbar2;        /* 0xd0da8 - RapidIO Inbound Window Base Address Register 2 */
1069         char    res42[4];
1070         uint    riwar2;         /* 0xd0db0 - RapidIO Inbound Attributes Register 2 */
1071         char    res43[12];
1072         uint    riwtar1;        /* 0xd0dc0 - RapidIO Inbound Window Translation Address Register 1 */
1073         char    res44[4];
1074         uint    riwbar1;        /* 0xd0dc8 - RapidIO Inbound Window Base Address Register 1 */
1075         char    res45[4];
1076         uint    riwar1;         /* 0xd0dd0 - RapidIO Inbound Attributes Register 1 */
1077         char    res46[12];
1078         uint    riwtar0;        /* 0xd0de0 - RapidIO Inbound Window Translation Address Register 0 */
1079         char    res47[12];
1080         uint    riwar0;         /* 0xd0df0 - RapidIO Inbound Attributes Register 0 */
1081         char    res48[12];
1082         uint    pnfedr;         /* 0xd0e00 - Port Notification/Fatal Error Detect Register */
1083         uint    pnfedir;        /* 0xd0e04 - Port Notification/Fatal Error Detect Register */
1084         uint    pnfeier;        /* 0xd0e08 - Port Notification/Fatal Error Interrupt Enable Register */
1085         uint    pecr;           /* 0xd0e0c - Port Error Control Register */
1086         uint    pepcsr0;        /* 0xd0e10 - Port Error Packet/Control Symbol Register 0 */
1087         uint    pepr1;          /* 0xd0e14 - Port Error Packet Register 1 */
1088         uint    pepr2;          /* 0xd0e18 - Port Error Packet Register 2 */
1089         char    res49[4];
1090         uint    predr;          /* 0xd0e20 - Port Recoverable Error Detect Register */
1091         char    res50[4];
1092         uint    pertr;          /* 0xd0e28 - Port Error Recovery Threshold Register */
1093         uint    prtr;           /* 0xd0e2c - Port Retry Threshold Register */
1094         char    res51[8656];
1095         uint    omr;            /* 0xd3000 - Outbound Mode Register */
1096         uint    osr;            /* 0xd3004 - Outbound Status Register */
1097         uint    eodqtpar;       /* 0xd3008 - Extended Outbound Descriptor Queue Tail Pointer Address Register */
1098         uint    odqtpar;        /* 0xd300c - Outbound Descriptor Queue Tail Pointer Address Register */
1099         uint    eosar;          /* 0xd3010 - Extended Outbound Unit Source Address Register */
1100         uint    osar;           /* 0xd3014 - Outbound Unit Source Address Register */
1101         uint    odpr;           /* 0xd3018 - Outbound Destination Port Register */
1102         uint    odatr;          /* 0xd301c - Outbound Destination Attributes Register */
1103         uint    odcr;           /* 0xd3020 - Outbound Doubleword Count Register */
1104         uint    eodqhpar;       /* 0xd3024 - Extended Outbound Descriptor Queue Head Pointer Address Register */
1105         uint    odqhpar;        /* 0xd3028 - Outbound Descriptor Queue Head Pointer Address Register */
1106         uint    oretr;          /* 0xd302C - Outbound Retry Error Threshold Register */
1107         uint    omgr;           /* 0xd3030 - Outbound Multicast Group Register */
1108         uint    omlr;           /* 0xd3034 - Outbound Multicast List Register */
1109         char    res52[40];
1110         uint    imr;            /* 0xd3060 - Outbound Mode Register */
1111         uint    isr;            /* 0xd3064 - Inbound Status Register */
1112         uint    eidqtpar;       /* 0xd3068 - Extended Inbound Descriptor Queue Tail Pointer Address Register */
1113         uint    idqtpar;        /* 0xd306c - Inbound Descriptor Queue Tail Pointer Address Register */
1114         uint    eifqhpar;       /* 0xd3070 - Extended Inbound Frame Queue Head Pointer Address Register */
1115         uint    ifqhpar;        /* 0xd3074 - Inbound Frame Queue Head Pointer Address Register */
1116         uint    imirir;         /* 0xd3078 - Inbound Maximum Interrutp Report Interval Register */
1117         char    res53[900];
1118         uint    oddmr;          /* 0xd3400 - Outbound Doorbell Mode Register */
1119         uint    oddsr;          /* 0xd3404 - Outbound Doorbell Status Register */
1120         char    res54[16];
1121         uint    oddpr;          /* 0xd3418 - Outbound Doorbell Destination Port Register */
1122         uint    oddatr;         /* 0xd341C - Outbound Doorbell Destination Attributes Register */
1123         char    res55[12];
1124         uint    oddretr;        /* 0xd342C - Outbound Doorbell Retry Threshold Configuration Register */
1125         char    res56[48];
1126         uint    idmr;           /* 0xd3460 - Inbound Doorbell Mode Register */
1127         uint    idsr;           /* 0xd3464 - Inbound Doorbell Status Register */
1128         uint    iedqtpar;       /* 0xd3468 - Extended Inbound Doorbell Queue Tail Pointer Address Register */
1129         uint    iqtpar;         /* 0xd346c - Inbound Doorbell Queue Tail Pointer Address Register */
1130         uint    iedqhpar;       /* 0xd3470 - Extended Inbound Doorbell Queue Head Pointer Address Register */
1131         uint    idqhpar;        /* 0xd3474 - Inbound Doorbell Queue Head Pointer Address Register */
1132         uint    idmirir;        /* 0xd3478 - Inbound Doorbell Max Interrupt Report Interval Register */
1133         char    res57[100];
1134         uint    pwmr;           /* 0xd34e0 - Port-Write Mode Register */
1135         uint    pwsr;           /* 0xd34e4 - Port-Write Status Register */
1136         uint    epwqbar;        /* 0xd34e8 - Extended Port-Write Queue Base Address Register */
1137         uint    pwqbar;         /* 0xd34ec - Port-Write Queue Base Address Register */
1138         char    res58[51984];
1139 } ccsr_rio_t;
1140
1141 /* Global Utilities Register Block(0xe_0000-0xf_ffff) */
1142 typedef struct ccsr_gur {
1143         uint    porpllsr;       /* 0xe0000 - POR PLL ratio status register */
1144         uint    porbmsr;        /* 0xe0004 - POR boot mode status register */
1145         uint    porimpscr;      /* 0xe0008 - POR I/O impedance status and control register */
1146         uint    pordevsr;       /* 0xe000c - POR I/O device status regsiter */
1147         uint    pordbgmsr;      /* 0xe0010 - POR debug mode status register */
1148         char    res1[12];
1149         uint    gpporcr;        /* 0xe0020 - General-purpose POR configuration register */
1150         char    res2[12];
1151         uint    gpiocr;         /* 0xe0030 - GPIO control register */
1152         char    res3[12];
1153         uint    gpoutdr;        /* 0xe0040 - General-purpose output data register */
1154         char    res4[12];
1155         uint    gpindr;         /* 0xe0050 - General-purpose input data register */
1156         char    res5[12];
1157         uint    pmuxcr;         /* 0xe0060 - Alternate function signal multiplex control */
1158         char    res6[12];
1159         uint    devdisr;        /* 0xe0070 - Device disable control */
1160         char    res7[12];
1161         uint    powmgtcsr;      /* 0xe0080 - Power management status and control register */
1162         char    res8[12];
1163         uint    mcpsumr;        /* 0xe0090 - Machine check summary register */
1164         uint    rstrscr;        /* 0xe0094 - Reset request status and control register */
1165         char    res9[8];
1166         uint    pvr;            /* 0xe00a0 - Processor version register */
1167         uint    svr;            /* 0xe00a4 - System version register */
1168         char    res10a[8];
1169         uint    rstcr;          /* 0xe00b0 - Reset control register */
1170         char    res10b[1868];
1171         uint    clkdvdr;        /* 0xe0800 - Clock Divide register */
1172         char    res10c[796];
1173         uint    ddr1clkdr;      /* 0xe0b20 - DDRC1 Clock Disable register */
1174         char    res10d[4];
1175         uint    ddr2clkdr;      /* 0xe0b28 - DDRC2 Clock Disable register */
1176         char    res10e[724];
1177         uint    clkocr;         /* 0xe0e00 - Clock out select register */
1178         char    res11[12];
1179         uint    ddrdllcr;       /* 0xe0e10 - DDR DLL control register */
1180         char    res12[12];
1181         uint    lbcdllcr;       /* 0xe0e20 - LBC DLL control register */
1182         char    res13a[224];
1183         uint    srds1cr0;       /* 0xe0f04 - SerDes1 control register 0 */
1184         char    res13b[4];
1185         uint    srds1cr1;       /* 0xe0f08 - SerDes1 control register 1 */
1186         char    res14[24];
1187         uint    ddrioovcr;      /* 0xe0f24 - DDR IO Overdrive Control register */
1188         char    res15a[24];
1189         uint    srds2cr0;       /* 0xe0f40 - SerDes2 control register 0 */
1190         uint    srds2cr1;       /* 0xe0f44 - SerDes2 control register 1 */
1191         char    res16[184];
1192 } ccsr_gur_t;
1193
1194 #define MPC8610_PORBMSR_HA      0x00070000
1195 #define MPC8610_PORBMSR_HA_SHIFT        16
1196 #define MPC8641_PORBMSR_HA      0x00060000
1197 #define MPC8641_PORBMSR_HA_SHIFT        17
1198 #define MPC8610_PORDEVSR_IO_SEL         0x00380000
1199 #define MPC8610_PORDEVSR_IO_SEL_SHIFT           19
1200 #define MPC8641_PORDEVSR_IO_SEL         0x000F0000
1201 #define MPC8641_PORDEVSR_IO_SEL_SHIFT           16
1202 #define MPC86xx_PORDEVSR_CORE1TE        0x00000080 /* ASMP (Core1 addr trans) */
1203 #define MPC86xx_DEVDISR_PCIEX1  0x80000000
1204 #define MPC86xx_DEVDISR_PCIEX2  0x40000000
1205 #define MPC86xx_DEVDISR_PCI1    0x80000000
1206 #define MPC86xx_DEVDISR_PCIE1   0x40000000
1207 #define MPC86xx_DEVDISR_PCIE2   0x20000000
1208 #define MPC86xx_DEVDISR_SRIO    0x00080000
1209 #define MPC86xx_DEVDISR_RMSG    0x00040000
1210 #define MPC86xx_DEVDISR_CPU0    0x00008000
1211 #define MPC86xx_DEVDISR_CPU1    0x00004000
1212 #define MPC86xx_RSTCR_HRST_REQ  0x00000002
1213
1214 /*
1215  * Watchdog register block(0xe_4000-0xe_4fff)
1216  */
1217 typedef struct ccsr_wdt {
1218         uint    res0;
1219         uint    swcrr; /* System watchdog control register */
1220         uint    swcnr; /* System watchdog count register */
1221         char    res1[2];
1222         ushort  swsrr; /* System watchdog service register */
1223         char    res2[4080];
1224 } ccsr_wdt_t;
1225
1226 typedef struct immap {
1227         ccsr_local_mcm_t        im_local_mcm;
1228         ccsr_ddr_t              im_ddr1;
1229         ccsr_i2c_t              im_i2c;
1230         ccsr_duart_t            im_duart;
1231         fsl_lbc_t               im_lbc;
1232         ccsr_ddr_t              im_ddr2;
1233         char                    res1[4096];
1234         ccsr_pex_t              im_pex1;
1235         ccsr_pex_t              im_pex2;
1236         ccsr_ht_t               im_ht;
1237         char                    res2[90112];
1238         ccsr_dma_t              im_dma;
1239         char                    res3[8192];
1240         ccsr_tsec_t             im_tsec1;
1241         ccsr_tsec_t             im_tsec2;
1242         ccsr_tsec_t             im_tsec3;
1243         ccsr_tsec_t             im_tsec4;
1244         char                    res4[98304];
1245         ccsr_pic_t              im_pic;
1246         char                    res5[389120];
1247         ccsr_rio_t              im_rio;
1248         ccsr_gur_t              im_gur;
1249         char                    res6[12288];
1250         ccsr_wdt_t              im_wdt;
1251 } immap_t;
1252
1253 extern immap_t  *immr;
1254
1255 #define CONFIG_SYS_MPC8xxx_DDR_OFFSET   0x2000
1256 #define CONFIG_SYS_FSL_DDR_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC8xxx_DDR_OFFSET)
1257 #define CONFIG_SYS_MPC8xxx_DDR2_OFFSET  0x6000
1258 #define CONFIG_SYS_FSL_DDR2_ADDR        (CONFIG_SYS_IMMR + CONFIG_SYS_MPC8xxx_DDR2_OFFSET)
1259 #define CONFIG_SYS_MPC86xx_DMA_OFFSET   0x21000
1260 #define CONFIG_SYS_MPC86xx_DMA_ADDR     (CONFIG_SYS_IMMR + CONFIG_SYS_MPC86xx_DMA_OFFSET)
1261 #define CONFIG_SYS_MPC86xx_PIC_OFFSET   0x40000
1262 #define CONFIG_SYS_MPC8xxx_PIC_ADDR     (CONFIG_SYS_IMMR + CONFIG_SYS_MPC86xx_PIC_OFFSET)
1263
1264
1265 #define CONFIG_SYS_MPC86xx_PCI1_OFFSET          0x8000
1266 #ifdef CONFIG_MPC8610
1267 #define CONFIG_SYS_MPC86xx_PCIE1_OFFSET         0xa000
1268 #else
1269 #define CONFIG_SYS_MPC86xx_PCIE1_OFFSET         0x8000
1270 #endif
1271 #define CONFIG_SYS_MPC86xx_PCIE2_OFFSET         0x9000
1272
1273 #define CONFIG_SYS_PCI1_ADDR \
1274         (CONFIG_SYS_IMMR + CONFIG_SYS_MPC86xx_PCI1_OFFSET)
1275 #define CONFIG_SYS_PCI2_ADDR \
1276         (CONFIG_SYS_IMMR + CONFIG_SYS_MPC86xx_PCI2_OFFSET)
1277 #define CONFIG_SYS_PCIE1_ADDR \
1278         (CONFIG_SYS_IMMR + CONFIG_SYS_MPC86xx_PCIE1_OFFSET)
1279 #define CONFIG_SYS_PCIE2_ADDR \
1280         (CONFIG_SYS_IMMR + CONFIG_SYS_MPC86xx_PCIE2_OFFSET)
1281
1282 #define CONFIG_SYS_TSEC1_OFFSET         0x24000
1283 #define CONFIG_SYS_MDIO1_OFFSET         0x24000
1284 #define CONFIG_SYS_LBC_ADDR             (&((immap_t *)CONFIG_SYS_IMMR)->im_lbc)
1285
1286 #define TSEC_BASE_ADDR          (CONFIG_SYS_IMMR + CONFIG_SYS_TSEC1_OFFSET)
1287 #define MDIO_BASE_ADDR          (CONFIG_SYS_IMMR + CONFIG_SYS_MDIO1_OFFSET)
1288
1289 #endif /*__IMMAP_86xx__*/