arch/powerpc/include/asm/ppc405ex.h

   1 /*
   2  * (C) Copyright 2010
   3  * Stefan Roese, DENX Software Engineering, sr@denx.de.
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0+
   6  */
   7
   8 #ifndef _PPC405EX_H_
   9 #define _PPC405EX_H_
  10
  11 #define CONFIG_SDRAM_PPC4xx_IBM_DDR2    /* IBM DDR(2) controller */
  12
  13 #define CONFIG_NAND_NDFC
  14
  15 /* Memory mapped register */
  16 #define CONFIG_SYS_PERIPHERAL_BASE      0xef600000 /* Internal Peripherals */
  17
  18 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_PERIPHERAL_BASE + 0x0200)
  19 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_PERIPHERAL_BASE + 0x0300)
  20
  21 #define GPIO0_BASE              (CONFIG_SYS_PERIPHERAL_BASE + 0x0800)
  22
  23 /* SDR */
  24 #define SDR0_SDCS0              0x0060
  25 #define SDR0_UART0              0x0120  /* UART0 Config */
  26 #define SDR0_UART1              0x0121  /* UART1 Config */
  27 #define SDR0_SRST               0x0200
  28 #define SDR0_CUST0              0x4000
  29 #define SDR0_PFC0               0x4100
  30 #define SDR0_PFC1               0x4101
  31 #define SDR0_MFR                0x4300  /* SDR0_MFR reg */
  32
  33 #define SDR0_ECID0              0x0080
  34 #define SDR0_ECID1              0x0081
  35 #define SDR0_ECID2              0x0082
  36 #define SDR0_ECID3              0x0083
  37
  38 #define SDR0_SDCS_SDD           (0x80000000 >> 31)
  39
  40 #define SDR0_SRST_DMC           (0x80000000 >> 10)
  41
  42 #define SDR0_CUST0_MUX_E_N_G_MASK       0xC0000000 /* Mux_Emac_NDFC_GPIO */
  43 #define SDR0_CUST0_MUX_EMAC_SEL         0x40000000 /* Emac Selection */
  44 #define SDR0_CUST0_MUX_NDFC_SEL         0x80000000 /* NDFC Selection */
  45 #define SDR0_CUST0_MUX_GPIO_SEL         0xC0000000 /* GPIO Selection */
  46
  47 #define SDR0_CUST0_NDFC_EN_MASK         0x20000000 /* NDFC Enable Mask */
  48 #define SDR0_CUST0_NDFC_ENABLE          0x20000000 /* NDFC Enable */
  49 #define SDR0_CUST0_NDFC_DISABLE         0x00000000 /* NDFC Disable */
  50
  51 #define SDR0_CUST0_NDFC_BW_MASK         0x10000000 /* NDFC Boot Width */
  52 #define SDR0_CUST0_NDFC_BW_16_BIT       0x10000000 /* NDFC Boot Width= 16 Bit */
  53 #define SDR0_CUST0_NDFC_BW_8_BIT        0x00000000 /* NDFC Boot Width=  8 Bit */
  54
  55 #define SDR0_CUST0_NDFC_BP_MASK         0x0F000000 /* NDFC Boot Page */
  56 #define SDR0_CUST0_NDFC_BP_ENCODE(n)    ((((u32)(n)) & 0xF) << 24)
  57 #define SDR0_CUST0_NDFC_BP_DECODE(n)    ((((u32)(n)) >> 24) & 0xF)
  58
  59 #define SDR0_CUST0_NDFC_BAC_MASK        0x00C00000 /* NDFC Boot Address Cycle */
  60 #define SDR0_CUST0_NDFC_BAC_ENCODE(n)   ((((u32)(n)) & 0x3) << 22)
  61 #define SDR0_CUST0_NDFC_BAC_DECODE(n)   ((((u32)(n)) >> 22) & 0x3)
  62
  63 #define SDR0_CUST0_NDFC_ARE_MASK        0x00200000 /* NDFC Auto Read Enable */
  64 #define SDR0_CUST0_NDFC_ARE_ENABLE      0x00200000 /* NDFC Auto Read Enable */
  65 #define SDR0_CUST0_NDFC_ARE_DISABLE     0x00000000 /* NDFC Auto Read Disable */
  66
  67 #define SDR0_CUST0_NRB_MASK             0x00100000 /* NDFC Ready / Busy */
  68 #define SDR0_CUST0_NRB_BUSY             0x00100000 /* Busy */
  69 #define SDR0_CUST0_NRB_READY            0x00000000 /* Ready */
  70
  71 #define SDR0_PFC1_U1ME                  0x02000000
  72 #define SDR0_PFC1_U0ME                  0x00080000
  73 #define SDR0_PFC1_U0IM                  0x00040000
  74 #define SDR0_PFC1_SIS                   0x00020000
  75 #define SDR0_PFC1_DMAAEN                0x00010000
  76 #define SDR0_PFC1_DMADEN                0x00008000
  77 #define SDR0_PFC1_USBEN                 0x00004000
  78 #define SDR0_PFC1_AHBSWAP               0x00000020
  79 #define SDR0_PFC1_USBBIGEN              0x00000010
  80 #define SDR0_PFC1_GPT_FREQ              0x0000000f
  81
  82 #endif /* _PPC405EX_H_ */