arch/powerpc/include/asm/ppc440.h

   1 /*----------------------------------------------------------------------------+
   2 |   This source code is dual-licensed.  You may use it under the terms of the
   3 |   GNU General Public License version 2, or under the license below.
   4 |
   5 |       This source code has been made available to you by IBM on an AS-IS
   6 |       basis.  Anyone receiving this source is licensed under IBM
   7 |       copyrights to use it in any way he or she deems fit, including
   8 |       copying it, modifying it, compiling it, and redistributing it either
   9 |       with or without modifications.  No license under IBM patents or
  10 |       patent applications is to be implied by the copyright license.
  11 |
  12 |       Any user of this software should understand that IBM cannot provide
  13 |       technical support for this software and will not be responsible for
  14 |       any consequences resulting from the use of this software.
  15 |
  16 |       Any person who transfers this source code or any derivative work
  17 |       must include the IBM copyright notice, this paragraph, and the
  18 |       preceding two paragraphs in the transferred software.
  19 |
  20 |       COPYRIGHT   I B M   CORPORATION 1999
  21 |       LICENSED MATERIAL  -  PROGRAM PROPERTY OF I B M
  22 +----------------------------------------------------------------------------*/
  23
  24 /*
  25  * (C) Copyright 2006
  26  * Sylvie Gohl,             AMCC/IBM, gohl.sylvie@fr.ibm.com
  27  * Jacqueline Pira-Ferriol, AMCC/IBM, jpira-ferriol@fr.ibm.com
  28  * Thierry Roman,           AMCC/IBM, thierry_roman@fr.ibm.com
  29  * Alain Saurel,            AMCC/IBM, alain.saurel@fr.ibm.com
  30  * Robert Snyder,           AMCC/IBM, rob.snyder@fr.ibm.com
  31  *
  32  * (C) Copyright 2010
  33  * Stefan Roese, DENX Software Engineering, sr@denx.de.
  34  *
  35  * SPDX-License-Identifier:     GPL-2.0+
  36  */
  37
  38 #ifndef __PPC440_H__
  39 #define __PPC440_H__
  40
  41 #define CONFIG_SYS_DCACHE_SIZE          (32 << 10)      /* For AMCC 440 CPUs */
  42
  43 /*
  44  * DCRs & Related
  45  */
  46
  47 /* Memory mapped registers */
  48 #define PCIL0_CFGADR    (CONFIG_SYS_PCI_BASE + 0x0ec00000)
  49 #define PCIL0_CFGDATA   (CONFIG_SYS_PCI_BASE + 0x0ec00004)
  50 #define PCIL0_CFGBASE   (CONFIG_SYS_PCI_BASE + 0x0ec80000)
  51 #define PCIL0_IOBASE    (CONFIG_SYS_PCI_BASE + 0x08000000)
  52
  53 /* DCR registers */
  54
  55 /* CPR register declarations */
  56 #define CPR0_PLLC       0x0040
  57 #define CPR0_PLLD       0x0060
  58 #define CPR0_PRIMAD0    0x0080
  59 #define CPR0_PRIMBD0    0x00a0
  60 #define CPR0_OPBD0      0x00c0
  61 #define CPR0_PERD       0x00e0
  62 #define CPR0_MALD       0x0100
  63 #define CPR0_SPCID      0x0120
  64 #define CPR0_ICFG       0x0140
  65
  66 /* SDR register definations */
  67 #define SDR0_SDSTP0     0x0020
  68 #define SDR0_SDSTP1     0x0021
  69 #define SDR0_PINSTP     0x0040
  70 #define SDR0_SDCS0      0x0060
  71 #define SDR0_ECID0      0x0080
  72 #define SDR0_ECID1      0x0081
  73 #define SDR0_ECID2      0x0082
  74 #define SDR0_ECID3      0x0083
  75 #define SDR0_DDR0       0x00e1
  76 #define SDR0_EBC        0x0100
  77 #define SDR0_UART0      0x0120
  78 #define SDR0_UART1      0x0121
  79 #define SDR0_UART2      0x0122
  80 #define SDR0_UART3      0x0123
  81 #define SDR0_CP440      0x0180
  82 #define SDR0_XCR        0x01c0
  83 #define SDR0_XCR0       0x01c0
  84 #define SDR0_XPLLC      0x01c1
  85 #define SDR0_XPLLD      0x01c2
  86 #define SDR0_SRST       0x0200
  87 #define SDR0_SRST0      SDR0_SRST
  88 #define SDR0_SRST1      0x0201
  89 #define SDR0_AMP0       0x0240
  90 #define SDR0_AMP1       0x0241
  91 #define SDR0_USB0       0x0320
  92 #define SDR0_CUST0      0x4000
  93 #define SDR0_CUST1      0x4002
  94 #define SDR0_CUST2      0x4004
  95 #define SDR0_CUST3      0x4006
  96 #define SDR0_PFC0       0x4100
  97 #define SDR0_PFC1       0x4101
  98 #define SDR0_PFC2       0x4102
  99 #define SDR0_PFC4       0x4104
 100 #define SDR0_MFR        0x4300
 101
 102 #define SDR0_DDR0_DDRM_DECODE(n)        ((((u32)(n)) >> 29) & 0x03)
 103
 104 #define SDR0_PCI0_PAE_MASK              (0x80000000 >> 0)
 105 #define SDR0_XCR0_PAE_MASK              (0x80000000 >> 0)
 106
 107 #define SDR0_PFC0_GEIE_MASK             0x00003e00
 108 #define SDR0_PFC0_GEIE_TRE              0x00003e00
 109 #define SDR0_PFC0_GEIE_NOTRE            0x00000000
 110 #define SDR0_PFC0_TRE_MASK              (0x80000000 >> 23)
 111 #define SDR0_PFC0_TRE_DISABLE           0x00000000
 112 #define SDR0_PFC0_TRE_ENABLE            (0x80000000 >> 23)
 113
 114 /*
 115  * Core Configuration/MMU configuration for 440
 116  */
 117 #define CCR0_DAPUIB             0x00100000
 118 #define CCR0_DTB                0x00008000
 119
 120 #define SDR0_SDCS_SDD           (0x80000000 >> 31)
 121
 122 /* todo: move this code from macro offsets to struct */
 123 #define PCIL0_VENDID            (PCIL0_CFGBASE + PCI_VENDOR_ID )
 124 #define PCIL0_DEVID             (PCIL0_CFGBASE + PCI_DEVICE_ID )
 125 #define PCIL0_CMD               (PCIL0_CFGBASE + PCI_COMMAND )
 126 #define PCIL0_STATUS            (PCIL0_CFGBASE + PCI_STATUS )
 127 #define PCIL0_REVID             (PCIL0_CFGBASE + PCI_REVISION_ID )
 128 #define PCIL0_CLS               (PCIL0_CFGBASE + PCI_CLASS_CODE)
 129 #define PCIL0_CACHELS           (PCIL0_CFGBASE + PCI_CACHE_LINE_SIZE )
 130 #define PCIL0_LATTIM            (PCIL0_CFGBASE + PCI_LATENCY_TIMER )
 131 #define PCIL0_HDTYPE            (PCIL0_CFGBASE + PCI_HEADER_TYPE )
 132 #define PCIL0_BIST              (PCIL0_CFGBASE + PCI_BIST )
 133 #define PCIL0_BAR0              (PCIL0_CFGBASE + PCI_BASE_ADDRESS_0 )
 134 #define PCIL0_BAR1              (PCIL0_CFGBASE + PCI_BASE_ADDRESS_1 )
 135 #define PCIL0_BAR2              (PCIL0_CFGBASE + PCI_BASE_ADDRESS_2 )
 136 #define PCIL0_BAR3              (PCIL0_CFGBASE + PCI_BASE_ADDRESS_3 )
 137 #define PCIL0_BAR4              (PCIL0_CFGBASE + PCI_BASE_ADDRESS_4 )
 138 #define PCIL0_BAR5              (PCIL0_CFGBASE + PCI_BASE_ADDRESS_5 )
 139 #define PCIL0_CISPTR            (PCIL0_CFGBASE + PCI_CARDBUS_CIS )
 140 #define PCIL0_SBSYSVID          (PCIL0_CFGBASE + PCI_SUBSYSTEM_VENDOR_ID )
 141 #define PCIL0_SBSYSID           (PCIL0_CFGBASE + PCI_SUBSYSTEM_ID )
 142 #define PCIL0_EROMBA            (PCIL0_CFGBASE + PCI_ROM_ADDRESS )
 143 #define PCIL0_CAP               (PCIL0_CFGBASE + PCI_CAPABILITY_LIST )
 144 #define PCIL0_RES0              (PCIL0_CFGBASE + 0x0035 )
 145 #define PCIL0_RES1              (PCIL0_CFGBASE + 0x0036 )
 146 #define PCIL0_RES2              (PCIL0_CFGBASE + 0x0038 )
 147 #define PCIL0_INTLN             (PCIL0_CFGBASE + PCI_INTERRUPT_LINE )
 148 #define PCIL0_INTPN             (PCIL0_CFGBASE + PCI_INTERRUPT_PIN )
 149
 150 #define PCIL0_MINGNT            (PCIL0_CFGBASE + PCI_MIN_GNT )
 151 #define PCIL0_MAXLTNCY          (PCIL0_CFGBASE + PCI_MAX_LAT )
 152
 153 #define PCIL0_POM0LAL           (PCIL0_CFGBASE + 0x0068)
 154 #define PCIL0_POM0LAH           (PCIL0_CFGBASE + 0x006c)
 155 #define PCIL0_POM0SA            (PCIL0_CFGBASE + 0x0070)
 156 #define PCIL0_POM0PCIAL         (PCIL0_CFGBASE + 0x0074)
 157 #define PCIL0_POM0PCIAH         (PCIL0_CFGBASE + 0x0078)
 158 #define PCIL0_POM1LAL           (PCIL0_CFGBASE + 0x007c)
 159 #define PCIL0_POM1LAH           (PCIL0_CFGBASE + 0x0080)
 160 #define PCIL0_POM1SA            (PCIL0_CFGBASE + 0x0084)
 161 #define PCIL0_POM1PCIAL         (PCIL0_CFGBASE + 0x0088)
 162 #define PCIL0_POM1PCIAH         (PCIL0_CFGBASE + 0x008c)
 163 #define PCIL0_POM2SA            (PCIL0_CFGBASE + 0x0090)
 164
 165 #define PCIL0_PIM0SA            (PCIL0_CFGBASE + 0x0098)
 166 #define PCIL0_PIM0LAL           (PCIL0_CFGBASE + 0x009c)
 167 #define PCIL0_PIM0LAH           (PCIL0_CFGBASE + 0x00a0)
 168 #define PCIL0_PIM1SA            (PCIL0_CFGBASE + 0x00a4)
 169 #define PCIL0_PIM1LAL           (PCIL0_CFGBASE + 0x00a8)
 170 #define PCIL0_PIM1LAH           (PCIL0_CFGBASE + 0x00ac)
 171 #define PCIL0_PIM2SA            (PCIL0_CFGBASE + 0x00b0)
 172 #define PCIL0_PIM2LAL           (PCIL0_CFGBASE + 0x00b4)
 173 #define PCIL0_PIM2LAH           (PCIL0_CFGBASE + 0x00b8)
 174
 175 #define PCIL0_STS               (PCIL0_CFGBASE + 0x00e0)
 176
 177 #endif  /* __PPC440_H__ */